coreboot-gerrit May 2020

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Change in coreboot[master]: mb/google/cyan/*: fixup GPIOs
by Matt DeVillier (Code Review) 11 May '20

11 May '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41176 ) Change subject: mb/google/cyan/*: fixup GPIOs ...................................................................... mb/google/cyan/*: fixup GPIOs Commit 73b723d [google/cyan: Switch Touchpad and Touchscreen...] in additon to changing the touchpad/touchscreen interrupts from edge to level triggered, also marked them as maskable. This was partially reverted in a86bbea0 [google/cyan: set touchscreen GPIO to non_maskable], but did not resolve all of the issues. Additionally, 73b723d also accidentally changed the pad interrupt select from L3 to L1 for all touchscreen GPIOs. Clean up this mess by setting all touchpad/touchscreen GPIOs back to maskable, and set the pad level to L3 for all touchscreen GPIOs. Tested on several cyan variants Change-Id: I70e8e2d4ff317c3b9b4108ed6c5bc80e9b0bbc75 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/variants/banon/gpio.c M src/mainboard/google/cyan/variants/cyan/gpio.c M src/mainboard/google/cyan/variants/edgar/gpio.c M src/mainboard/google/cyan/variants/kefka/gpio.c M src/mainboard/google/cyan/variants/reks/gpio.c M src/mainboard/google/cyan/variants/relm/gpio.c M src/mainboard/google/cyan/variants/setzer/gpio.c M src/mainboard/google/cyan/variants/terra/gpio.c M src/mainboard/google/cyan/variants/ultima/gpio.c M src/mainboard/google/cyan/variants/wizpig/gpio.c 10 files changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/41176/1 diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c index fa1ef88..5b4854e 100644 --- a/src/mainboard/google/cyan/variants/banon/gpio.c +++ b/src/mainboard/google/cyan/variants/banon/gpio.c @@ -147,9 +147,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), - /* 18 GPIO_SUS7 */ GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */ diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index c9cd286..9c8a87f 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -150,7 +150,7 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index f90ca79..342199d 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -147,7 +147,7 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ GPIO_NC, /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index ccff082..492b207 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -146,9 +146,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), - /* 18 GPIO_SUS7 */ GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */ diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index 6d8cb50..d9112d7 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -149,9 +149,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), - /* 18 GPIO_SUS7 */ GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */ diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index 61ede38..8b78834 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -149,9 +149,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), - /* 18 GPIO_SUS7 */ GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */ diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index c2acb2b..31fb71e 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -147,9 +147,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), - /* 18 GPIO_SUS7 */ GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */ diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index 2e16bb8..d39da33 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -146,7 +146,7 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ GPIO_NC, /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index fc8776a..2f4d5af 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -149,9 +149,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), - /* 18 GPIO_SUS7 */ GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */ diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index 603e91d..2074099 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -148,9 +148,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), - /* 18 GPIO_SUS7 */ GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_INPUT_NO_PULL, /* 21 SEC_GPIO_SUS11 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70e8e2d4ff317c3b9b4108ed6c5bc80e9b0bbc75 Gerrit-Change-Number: 41176 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: 3rdparty/libgfxinit: Update submodule pointer
by Matt DeVillier (Code Review) 11 May '20

11 May '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41181 ) Change subject: 3rdparty/libgfxinit: Update submodule pointer ...................................................................... 3rdparty/libgfxinit: Update submodule pointer Update libgfxinit submodule pointer to pull in fix for VT-d. Change-Id: I09f811bdb917365f4e97b7ab385781337d4c9cf7 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M 3rdparty/libgfxinit 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/41181/1 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index cdbfce2..12d71aa 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit cdbfce275777f2fd142e3a3c73469807a4c40207 +Subproject commit 12d71aa3a542da31a26591ab6a09ed8602d3d34f -- To view, visit https://review.coreboot.org/c/coreboot/+/41181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09f811bdb917365f4e97b7ab385781337d4c9cf7 Gerrit-Change-Number: 41181 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/google/octopus/variants/dood: Disable XHCI LFPS power management
by Kenneth Chan (Code Review) 11 May '20

11 May '20

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41143 ) Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ...................................................................... mb/google/octopus/variants/dood: Disable XHCI LFPS power management LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41143/1 diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index 6df9f53..e1f12cf 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -149,4 +149,5 @@ # Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index e728fe3..ab049a8 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -8,6 +8,7 @@ #include <delay.h> #include <gpio.h> #include <ec/google/chromeec/ec.h> +#include <soc/intel/apollolake/chip.h> enum { SKU_1_LTE = 1, /* Wifi + LTE */ @@ -61,3 +62,21 @@ return; } } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && cfg->disable_xhci_lfps_pm) { + switch (google_chromeec_get_board_sku()) { + case SKU_1_LTE: + case SKU_3_LTE_2CAM: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c Gerrit-Change-Number: 41143 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: soc/intel/tirgerlake: Update CState
by Wonkyu Kim (Code Review) 11 May '20

11 May '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40816 ) Change subject: soc/intel/tirgerlake: Update CState ...................................................................... soc/intel/tirgerlake: Update CState Update CState latency info in _CST method based on silicon referece code. Reference: https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ ClientOneSiliconPkg/Cpu/Include/CpuPowerMgmt.h BUG=b:155223704 BRANCH=None TEST=Boot to OS and check CState Latenecy >cat /sys/devices/system/cpu/cpu0/cpuidle/state*/ Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I8bf2976ad35b4cf6f637a99c26b4f98f9f6ee563 --- M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/cpu.h 2 files changed, 21 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/40816/1 diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index a331b72..29a5a4c 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -53,70 +53,70 @@ static const acpi_cstate_t cstate_map[NUM_C_STATES] = { [C_STATE_C0] = {}, [C_STATE_C1] = { - .latency = 0, + .latency = C1_LATENCY, .power = C1_POWER, .resource = MWAIT_RES(0, 0), }, [C_STATE_C1E] = { - .latency = 0, + .latency = C1_LATENCY, .power = C1_POWER, .resource = MWAIT_RES(0, 1), }, [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C6_LATENCY, .power = C6_POWER, .resource = MWAIT_RES(2, 0), }, [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C6_LATENCY, .power = C6_POWER, .resource = MWAIT_RES(2, 1), }, [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 0), }, [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 1), }, [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 2), }, [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 3), }, [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C8_LATENCY, .power = C8_POWER, .resource = MWAIT_RES(4, 0), }, [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C9_LATENCY, .power = C9_POWER, .resource = MWAIT_RES(5, 0), }, [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C10_LATENCY, .power = C10_POWER, .resource = MWAIT_RES(6, 0), }, }; static int cstate_set_non_s0ix[] = { - C_STATE_C1E, + C_STATE_C1, C_STATE_C6_LONG_LAT, C_STATE_C7S_LONG_LAT }; static int cstate_set_s0ix[] = { - C_STATE_C1E, + C_STATE_C1, C_STATE_C7S_LONG_LAT, C_STATE_C10 }; diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index 0d8e17f..a6a2a79 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -14,6 +14,14 @@ #define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d #define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d +/* Latency times in us */ +#define C1_LATENCY 1 +#define C6_LATENCY 127 +#define C7_LATENCY 253 +#define C8_LATENCY 260 +#define C9_LATENCY 487 +#define C10_LATENCY 1048 + /* Power in units of mW */ #define C1_POWER 0x3e8 #define C6_POWER 0x15e -- To view, visit https://review.coreboot.org/c/coreboot/+/40816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bf2976ad35b4cf6f637a99c26b4f98f9f6ee563 Gerrit-Change-Number: 40816 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Add SATA related UPDs configuration
by Aamir Bohra (Code Review) 11 May '20

11 May '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41029 ) Change subject: soc/intel/jasperlake: Add SATA related UPDs configuration ...................................................................... Patch Set 11: (2 comments) https://review.coreboot.org/c/coreboot/+/41029/11/src/soc/intel/jasperlake/… File src/soc/intel/jasperlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/41029/11/src/soc/intel/jasperlake/… PS11, Line 143: memcpy add _Static_assert? https://review.coreboot.org/c/coreboot/+/41029/11/src/soc/intel/jasperlake/… PS11, Line 145: memcpy same. -- To view, visit https://review.coreboot.org/c/coreboot/+/41029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f7e7508b8cd483508293ee3e7b760574d8f025f Gerrit-Change-Number: 41029 Gerrit-PatchSet: 11 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 11 May 2020 08:50:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX
by 9elements QA (Code Review) 11 May '20

11 May '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41116 ) Change subject: soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3309 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3308 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3307 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3306 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/41116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cd25edd167ec71ee98c7ffa4fa6f95ca73a75e9 Gerrit-Change-Number: 41116 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 11 May 2020 08:49:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Add SATA related UPDs configuration
by Maulik V Vaghela (Code Review) 11 May '20

11 May '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41029 ) Change subject: soc/intel/jasperlake: Add SATA related UPDs configuration ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/41029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f7e7508b8cd483508293ee3e7b760574d8f025f Gerrit-Change-Number: 41029 Gerrit-PatchSet: 11 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 11 May 2020 08:44:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Add ACPI device name for Storage controllers
by Karthik Ramasubramanian (Code Review) 11 May '20

11 May '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40420 ) Change subject: soc/intel/jasperlake: Add ACPI device name for Storage controllers ...................................................................... soc/intel/jasperlake: Add ACPI device name for Storage controllers This enables adding ACPI objects at run-time for SD Card and EMMC devices. BUG=b:150872580 TEST=Build and boot the mainboard. Observe ACPI objects like card detect gpio are added to the SSDT. Change-Id: I754aee3b0fd343994bd06d9c28e038f651009d6d Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/jasperlake/chip.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/40420/1 diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index 7b53e17..13b714d 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -87,6 +87,8 @@ case PCH_DEVFN_GSPI1: return "SPI1"; case PCH_DEVFN_GSPI2: return "SPI2"; case PCH_DEVFN_GSPI3: return "SPI3"; + case PCH_DEVFN_EMMC: return "EMMC"; + case PCH_DEVFN_SDCARD: return "SDXC"; /* Keeping ACPI device name coherent with ec.asl */ case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_HDA: return "HDAS"; -- To view, visit https://review.coreboot.org/c/coreboot/+/40420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I754aee3b0fd343994bd06d9c28e038f651009d6d Gerrit-Change-Number: 40420 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Turn off unused I2C lanes
by Varshit B Pandya (Code Review) 11 May '20

11 May '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40859 ) Change subject: mb/intel/jasperlake_rvp: Turn off unused I2C lanes ...................................................................... mb/intel/jasperlake_rvp: Turn off unused I2C lanes Change-Id: Id49032c0f9b701fe12873c80e1bc0e4b64ba7106 Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/40859/1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index cb3d1f3..4ef8ecd 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -81,9 +81,9 @@ register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoPci, }" @@ -267,10 +267,10 @@ register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end - end # I2C 0 Audio - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 + end # I2C #0 Audio + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R -- To view, visit https://review.coreboot.org/c/coreboot/+/40859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id49032c0f9b701fe12873c80e1bc0e4b64ba7106 Gerrit-Change-Number: 40859 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/ocp/ipmi: Implement set POST start/end command
by Tim Chu (Code Review) 11 May '20

11 May '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41229 ) Change subject: drivers/ocp/ipmi: Implement set POST start/end command ...................................................................... drivers/ocp/ipmi: Implement set POST start/end command Implemented to send POST start and POST end command to BMC in ramstage. Tested=Read POST command in OpenBMC, if success message may show as below, root@bmc:~# cat /var/log/messages |grep -i "POST" Aug 10 00:11:24 bmc user.info ipmid: POST Start Event for Payload#1 Aug 10 00:11:28 bmc user.info ipmid: POST End Event for Payload#1 root@bmc:~# Signed-off-by: TimChu <Tim.Chu(a)quantatw.com> Change-Id: I25fe435eeeef06ca9378ca9a0b3654806a3222ad --- A src/drivers/ocp/ipmi/Kconfig A src/drivers/ocp/ipmi/Makefile.inc A src/drivers/ocp/ipmi/ipmi_ocp.c A src/drivers/ocp/ipmi/ipmi_ocp.h M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/devicetree.cb 6 files changed, 138 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/41229/1 diff --git a/src/drivers/ocp/ipmi/Kconfig b/src/drivers/ocp/ipmi/Kconfig new file mode 100644 index 0000000..74a886e --- /dev/null +++ b/src/drivers/ocp/ipmi/Kconfig @@ -0,0 +1,3 @@ +config IPMI_OCP + bool + default n \ No newline at end of file diff --git a/src/drivers/ocp/ipmi/Makefile.inc b/src/drivers/ocp/ipmi/Makefile.inc new file mode 100644 index 0000000..f8be839 --- /dev/null +++ b/src/drivers/ocp/ipmi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_IPMI_OCP) += ipmi_ocp.c \ No newline at end of file diff --git a/src/drivers/ocp/ipmi/ipmi_ocp.c b/src/drivers/ocp/ipmi/ipmi_ocp.c new file mode 100644 index 0000000..08bca43 --- /dev/null +++ b/src/drivers/ocp/ipmi/ipmi_ocp.c @@ -0,0 +1,120 @@ +/* This file is part of the coreboot project. */ +/* + * Place in devicetree.cb: + * + * chip drivers/ocp/ipmi # OCP specific IPMI porting + device pnp ca2.1 on end + * end + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "drivers/ipmi/ipmi_kcs.h" +#include "ipmi_ocp.h" + +static int ipmi_set_post_start(struct device *dev, struct ipmi_rsp *rsp) +{ + int ret; + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM, 0, + IPMI_BMC_SET_POST_START, NULL, 0, (u8 *)rsp, + sizeof(*rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp->completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp->completion_code); + return 1; + } + if (ret != sizeof(*rsp)) { + printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); + return 1; + } + return 0; +} + +static int ipmi_set_post_end(struct device *dev, struct ipmi_rsp *rsp) +{ + int ret; + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM, 0, + IPMI_BMC_SET_POST_END, NULL, 0, (u8 *)rsp, + sizeof(*rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp->completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp->completion_code); + return 1; + } + if (ret != sizeof(*rsp)) { + printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); + return 1; + } + return 0; +} + +static void ipmi_ocp_init(struct device *dev) +{ + struct ipmi_rsp postrsp; + + /* Send POST start to BMC. */ + if(!ipmi_set_post_start(dev, &postrsp)){ + printk(BIOS_DEBUG, "IPMI BMC POST is started\n"); + } +} + +static void ipmi_ocp_final(struct device *dev) +{ + struct ipmi_rsp postrsp; + + /* Send POST end to BMC. */ + if(!ipmi_set_post_end(dev, &postrsp)){ + printk(BIOS_DEBUG, "IPMI BMC POST is ended\n"); + } +} + +static void ipmi_set_resources(struct device *dev) +{ + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_ASSIGNED)) + continue; + + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +} + +static void ipmi_read_resources(struct device *dev) +{ + struct resource *res = new_resource(dev, 0); + res->base = dev->path.pnp.port; + res->size = 2; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static struct device_operations ops = { + .read_resources = ipmi_read_resources, + .set_resources = ipmi_set_resources, + .init = ipmi_ocp_init, + .final = ipmi_ocp_final, +}; + +static void enable_dev(struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PNP) + printk(BIOS_ERR, "%s: Unsupported device type\n", + dev_path(dev)); + else if (dev->path.pnp.port & 1) + printk(BIOS_ERR, "%s: Base address needs to be aligned to 2\n", + dev_path(dev)); + else + dev->ops = &ops; +} + +struct chip_operations drivers_ocp_ipmi_ops = { + CHIP_NAME("IPMI OCP") + .enable_dev = enable_dev, +}; \ No newline at end of file diff --git a/src/drivers/ocp/ipmi/ipmi_ocp.h b/src/drivers/ocp/ipmi/ipmi_ocp.h new file mode 100644 index 0000000..6747e0a --- /dev/null +++ b/src/drivers/ocp/ipmi/ipmi_ocp.h @@ -0,0 +1,10 @@ +/* This file is part of the coreboot project. */ + +#ifndef __IPMI_OCP_H +#define __IPMI_OCP_H + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_BMC_SET_POST_START 0x73 +#define IPMI_BMC_SET_POST_END 0x74 + +#endif \ No newline at end of file diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index f9b5e7f..73eeca1 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -21,6 +21,7 @@ select HAVE_ACPI_TABLES select MAINBOARD_USES_FSP2_0 select IPMI_KCS + select IPMI_OCP select SOC_INTEL_SKYLAKE_SP select SUPERIO_ASPEED_AST2400 diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 51e6a62..8b0caab 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -89,6 +89,9 @@ register "bmc_i2c_address" = "0x20" register "bmc_boot_timeout" = "60" end + chip drivers/ocp/ipmi # OCP specific IPMI porting + device pnp ca2.1 on end + end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus -- To view, visit https://review.coreboot.org/c/coreboot/+/41229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25fe435eeeef06ca9378ca9a0b3654806a3222ad Gerrit-Change-Number: 41229 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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