Hello build bot (Jenkins), Patrick Georgi, Maulik V Vaghela, Subrata Banik, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41029
to look at the new patch set (#12).
Change subject: soc/intel/jasperlake: Add SATA related UPDs configuration
......................................................................
soc/intel/jasperlake: Add SATA related UPDs configuration
This patch control SATA related UPDs based on the devicetree
configuration as per each board's requirement.
BUG=b:155595624
BRANCH=None
TEST=Build, boot JSLRVP, Verified UPD values from FSP log
Change-Id: I4f7e7508b8cd483508293ee3e7b760574d8f025f
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
---
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
2 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/41029/12
--
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Gerrit-Branch: master
Gerrit-Change-Id: I4f7e7508b8cd483508293ee3e7b760574d8f025f
Gerrit-Change-Number: 41029
Gerrit-PatchSet: 12
Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
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Gerrit-MessageType: newpatchset
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41047 )
Change subject: mainboard/asus/p3b-f: Reintroduce as variant of p2b
......................................................................
mainboard/asus/p3b-f: Reintroduce as variant of p2b
Fold this last ASUS 440BX board into the P2B family, while bringing in
some changes:
- Devicetree becomes overridetree.
- Remove non-existent IR device and disable ACPI device on Super I/O to
match OEM firmware.
- Add SB GPO settings from OEM firmware to devicetree. This disables
the SPD enabling magic this board needs. By moving the enabling part
to bootblock the hacky enable_spd hook can be eliminated.
- Serial port now initialized in bootblock, like all other P2B family boards.
Boot tested on hardware.
Change-Id: I65f2cb9d1bd4c82550de43889e3502526a46bd18
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p2b/Kconfig
M src/mainboard/asus/p2b/Kconfig.name
M src/mainboard/asus/p2b/Makefile.inc
R src/mainboard/asus/p2b/variants/p3b-f/board_info.txt
R src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c
A src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb
A src/mainboard/asus/p2b/variants/p3b-f/romstage.c
D src/mainboard/asus/p3b-f/Kconfig
D src/mainboard/asus/p3b-f/Kconfig.name
D src/mainboard/asus/p3b-f/devicetree.cb
D src/mainboard/asus/p3b-f/romstage.c
11 files changed, 58 insertions(+), 162 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/41047/1
diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig
index 0bee04f..1ad25e1 100644
--- a/src/mainboard/asus/p2b/Kconfig
+++ b/src/mainboard/asus/p2b/Kconfig
@@ -11,7 +11,7 @@
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
-if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS
+if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F
config BASE_ASUS_P2B_D
def_bool n
@@ -28,7 +28,7 @@
select SUPERIO_WINBOND_W83977TF
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
- select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS
+ select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F
select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS
select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS
@@ -47,6 +47,7 @@
default "P2B-DS" if BOARD_ASUS_P2B_DS
default "P2B-F" if BOARD_ASUS_P2B_F
default "P2B-LS" if BOARD_ASUS_P2B_LS
+ default "P3B-F" if BOARD_ASUS_P3B_F
config VARIANT_DIR
string
@@ -55,6 +56,7 @@
default "p2b-ds" if BOARD_ASUS_P2B_DS
default "p2b-f" if BOARD_ASUS_P2B_F
default "p2b-ls" if BOARD_ASUS_P2B_LS
+ default "p3b-f" if BOARD_ASUS_P3B_F
config OVERRIDE_DEVICETREE
string
@@ -62,7 +64,7 @@
config IRQ_SLOT_COUNT
int
- default 8 if BOARD_ASUS_P2B_LS
+ default 8 if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F
default 7 if BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_DS
default 6
diff --git a/src/mainboard/asus/p2b/Kconfig.name b/src/mainboard/asus/p2b/Kconfig.name
index 106e694..f36fb0d 100644
--- a/src/mainboard/asus/p2b/Kconfig.name
+++ b/src/mainboard/asus/p2b/Kconfig.name
@@ -12,3 +12,6 @@
config BOARD_ASUS_P2B_LS
bool "P2B-LS"
+
+config BOARD_ASUS_P3B_F
+ bool "P3B-F"
diff --git a/src/mainboard/asus/p2b/Makefile.inc b/src/mainboard/asus/p2b/Makefile.inc
index cc55c25..eb48944 100644
--- a/src/mainboard/asus/p2b/Makefile.inc
+++ b/src/mainboard/asus/p2b/Makefile.inc
@@ -1,4 +1,5 @@
bootblock-y += bootblock.c
+romstage-$(CONFIG_BOARD_ASUS_P3B_F) += variants/$(VARIANT_DIR)/romstage.c
ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += variants/$(VARIANT_DIR)/irq_tables.c
ramstage-$(CONFIG_GENERATE_MP_TABLE) += variants/$(VARIANT_DIR)/mptable.c
diff --git a/src/mainboard/asus/p3b-f/board_info.txt b/src/mainboard/asus/p2b/variants/p3b-f/board_info.txt
similarity index 100%
rename from src/mainboard/asus/p3b-f/board_info.txt
rename to src/mainboard/asus/p2b/variants/p3b-f/board_info.txt
diff --git a/src/mainboard/asus/p3b-f/irq_tables.c b/src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c
similarity index 100%
rename from src/mainboard/asus/p3b-f/irq_tables.c
rename to src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c
diff --git a/src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb b/src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb
new file mode 100644
index 0000000..0a60812
--- /dev/null
+++ b/src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb
@@ -0,0 +1,12 @@
+chip northbridge/intel/i440bx # Northbridge
+ device domain 0 on # PCI domain
+ chip southbridge/intel/i82371eb # Southbridge
+ register "gpo" = "0x67ffbfff" # GPIO: This value sets GPIOs 27,28 to expose HWM
+ device pci 4.0 on # ISA bridge
+ chip superio/winbond/w83977tf # Super I/O
+ device pnp 3f0.a off end # ACPI
+ end
+ end
+ end
+ end
+end
diff --git a/src/mainboard/asus/p2b/variants/p3b-f/romstage.c b/src/mainboard/asus/p2b/variants/p3b-f/romstage.c
new file mode 100644
index 0000000..1794549
--- /dev/null
+++ b/src/mainboard/asus/p2b/variants/p3b-f/romstage.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <arch/io.h>
+#include <southbridge/intel/i82371eb/i82371eb.h>
+#include <northbridge/intel/i440bx/raminit.h>
+
+/*
+ * ASUS P3B-F specific SPD enable magic.
+ *
+ * Setting the byte at offset 0x37 in the PM I/O space to 0x6f will make the
+ * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD
+ * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which
+ * will make RAM init fail.
+ *
+ * Tested values for PM I/O offset 0x37:
+ * 0x67: 11 00 111: Only SMBus/I2C offsets 0x48/0x49/0x2d accessible
+ * 0x6f: 11 01 111: Only SMBus/I2C offsets 0x50-0x53 (SPD) accessible
+ * 0x77: 11 10 111: Only SMBus/I2C offset 0x69 accessible
+ *
+ * PM I/O space offset 0x37 is GPOREG[31:24], i.e. it controls the GPIOs
+ * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28
+ * control which SMBus/I2C offsets can be accessed.
+ */
+void enable_spd(void)
+{
+ outb(0x6f, PM_IO_BASE + 0x37);
+}
+
+/*
+ * Disable SPD access after RAM init to allow access to SMBus/I2C offsets
+ * 0x48/0x49/0x2d, which is required e.g. by lm-sensors.
+ */
+void disable_spd(void)
+{
+ outb(0x67, PM_IO_BASE + 0x37);
+}
diff --git a/src/mainboard/asus/p3b-f/Kconfig b/src/mainboard/asus/p3b-f/Kconfig
deleted file mode 100644
index eee97d5..0000000
--- a/src/mainboard/asus/p3b-f/Kconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-if BOARD_ASUS_P3B_F
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select CPU_INTEL_SLOT_1
- select NORTHBRIDGE_INTEL_I440BX
- select SOUTHBRIDGE_INTEL_I82371EB
- select SUPERIO_WINBOND_W83977TF
- select HAVE_PIRQ_TABLE
- select BOARD_ROMSIZE_KB_256
- select SDRAMPWR_4DIMM
-
-config MAINBOARD_DIR
- string
- default "asus/p3b-f"
-
-config MAINBOARD_PART_NUMBER
- string
- default "P3B-F"
-
-config IRQ_SLOT_COUNT
- int
- default 8
-
-endif # BOARD_ASUS_P3B_F
diff --git a/src/mainboard/asus/p3b-f/Kconfig.name b/src/mainboard/asus/p3b-f/Kconfig.name
deleted file mode 100644
index cf1d9b5..0000000
--- a/src/mainboard/asus/p3b-f/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_P3B_F
- bool "P3B-F"
diff --git a/src/mainboard/asus/p3b-f/devicetree.cb b/src/mainboard/asus/p3b-f/devicetree.cb
deleted file mode 100644
index bc9ad17..0000000
--- a/src/mainboard/asus/p3b-f/devicetree.cb
+++ /dev/null
@@ -1,59 +0,0 @@
-chip northbridge/intel/i440bx # Northbridge
- device cpu_cluster 0 on # APIC cluster
- chip cpu/intel/slot_1 # CPU
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- device pci 0.0 on end # Host bridge
- device pci 1.0 on end # PCI/AGP bridge
- chip southbridge/intel/i82371eb # Southbridge
- device pci 4.0 on # ISA bridge
- chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
- device pnp 3f0.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 3f0.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 3f0.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 3f0.3 on # COM2 / IR
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 3f0.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # PS/2 keyboard interrupt
- irq 0x72 = 12 # PS/2 mouse interrupt
- end
- device pnp 3f0.6 on # Consumer IR
- end
- device pnp 3f0.7 on # GPIO 1
- end
- device pnp 3f0.8 on # GPIO 2
- end
- device pnp 3f0.a on # ACPI
- end
- end
- end
- device pci 4.1 on end # IDE
- device pci 4.2 on end # USB
- device pci 4.3 on end # ACPI
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "ide_legacy_enable" = "1"
- # Enable UDMA/33 for higher speed if your IDE device(s) support it.
- register "ide0_drive0_udma33_enable" = "0"
- register "ide0_drive1_udma33_enable" = "0"
- register "ide1_drive0_udma33_enable" = "0"
- register "ide1_drive1_udma33_enable" = "0"
- end
- end
-end
diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c
deleted file mode 100644
index e3a7897..0000000
--- a/src/mainboard/asus/p3b-f/romstage.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <southbridge/intel/i82371eb/i82371eb.h>
-#include <northbridge/intel/i440bx/raminit.h>
-#include <superio/winbond/common/winbond.h>
-/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
-#include <superio/winbond/w83977tf/w83977tf.h>
-
-/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
-#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
-
-/*
- * ASUS P3B-F specific SPD enable magic.
- *
- * Setting the byte at offset 0x37 in the PM I/O space to 0x6f will make the
- * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD
- * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which
- * will make RAM init fail.
- *
- * Tested values for PM I/O offset 0x37:
- * 0x67: 11 00 111: Only SMBus/I2C offsets 0x48/0x49/0x2d accessible
- * 0x6f: 11 01 111: Only SMBus/I2C offsets 0x50-0x53 (SPD) accessible
- * 0x77: 11 10 111: Only SMBus/I2C offset 0x69 accessible
- *
- * PM I/O space offset 0x37 is GPOREG[31:24], i.e. it controls the GPIOs
- * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28
- * control which SMBus/I2C offsets can be accessed.
- */
-void enable_spd(void)
-{
- outb(0x6f, PM_IO_BASE + 0x37);
-}
-
-/*
- * Disable SPD access after RAM init to allow access to SMBus/I2C offsets
- * 0x48/0x49/0x2d, which is required e.g. by lm-sensors.
- */
-void disable_spd(void)
-{
- outb(0x67, PM_IO_BASE + 0x37);
-}
-
-void mainboard_enable_serial(void)
-{
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I65f2cb9d1bd4c82550de43889e3502526a46bd18
Gerrit-Change-Number: 41047
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin(a)gmail.com>
Gerrit-MessageType: newchange
Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40414 )
Change subject: lib/spd_bin: add get_spd_sn function
......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/c/coreboot/+/40414/6/src/soc/intel/common/block…
File src/soc/intel/common/block/smbus/smbuslib.c:
https://review.coreboot.org/c/coreboot/+/40414/6/src/soc/intel/common/block…
PS6, Line 85: It only support DDR3 and DDR4.
> nits: comment format is like below […]
Done
https://review.coreboot.org/c/coreboot/+/40414/6/src/soc/intel/common/block…
PS6, Line 119: } else if (dram_type == SPD_DRAM_DDR3)
> If any branch of an if/else if/else has more than one statement and uses braces {}, then all branche […]
Done
https://review.coreboot.org/c/coreboot/+/40414/6/src/soc/intel/common/block…
PS6, Line 126: }
> nit: blank line after }
Done
--
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Gerrit-MessageType: comment
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Edward O'Callaghan, Angel Pons, Arthur Heymans, Kane Chen, Aaron Durbin, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40414
to look at the new patch set (#8).
Change subject: lib/spd_bin: add get_spd_sn function
......................................................................
lib/spd_bin: add get_spd_sn function
This patch adds the get_spd_sn function. It's for reading SODIMM serial
number. In spd_cache implementation it can use to get serial number
before reading whole SPD by smbus.
BUG=b:146457985
BRANCH=None
TEST=Wrote sample code to get the serial number and ran on puff.
It can get the serial number correctly.
Change-Id: I406bba7cc56debbd9851d430f069e4fb96ec937c
Signed-off-by: Jamie Chen <jamie.chen(a)intel.com>
---
M src/include/spd_bin.h
M src/soc/intel/common/block/smbus/smbuslib.c
2 files changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/40414/8
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Gerrit-MessageType: newpatchset
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Edward O'Callaghan, Kane Chen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40415
to look at the new patch set (#8).
Change subject: mb/google/puff: add a region to cache SPD data
......................................................................
mb/google/puff: add a region to cache SPD data
This patch adds a SPI rom region RW_SPD_CACHE on Puff and it can be used
on spd_cache to reduce reading SPD data from SODIMM by smbus. It's for
saving the boot time and it can be used to trigger MRC retraining when
memory DIMM is changed.
BUG=b:146457985
BRANCH=None
TEST=Build puff successfully and verified below two items.
1. To change memory DIMM can trigger retraining.
2. one DIMM save the boot time : 158ms
two DIMM save the boot time : 265ms
Change-Id: I8d07fddf113a767d62394cb31e33b56f22f74351
Signed-off-by: Jamie Chen <jamie.chen(a)intel.com>
---
M src/mainboard/google/hatch/Kconfig
A src/mainboard/google/hatch/chromeos-16MiB-spd.fmd
A src/mainboard/google/hatch/chromeos-spd.fmd
M src/mainboard/google/hatch/romstage_spd_smbus.c
4 files changed, 131 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/40415/8
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Gerrit-Change-Number: 40415
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Edward O'Callaghan, Angel Pons, Arthur Heymans, Kane Chen, Aaron Durbin, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
Change subject: lib/spd_bin: add get_spd_sn function
......................................................................
lib/spd_bin: add get_spd_sn function
This patch adds the get_spd_sn function. It's for reading SODIMM serial
number. In spd_cache implementation it can use to get serial number
before reading whole SPD by smbus.
BUG=b:146457985
BRANCH=None
TEST=Wrote sample code to get the serial number and ran on puff.
It can get the serial number correctly.
Change-Id: I406bba7cc56debbd9851d430f069e4fb96ec937c
Signed-off-by: Jamie Chen <jamie.chen(a)intel.com>
---
M src/include/spd_bin.h
M src/soc/intel/common/block/smbus/smbuslib.c
2 files changed, 55 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/40414/7
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Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Jonathan Zhang, Maxim Polyakov, David Hendricks, Jingle Hsu, Morgan Jang,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#33).
Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data
......................................................................
drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data
It implements the SMBIOS IPMI FRU mapping table defined in
https://www.opencompute.org/documents/facebook-xeon-motherboard-v31
22.3 SMBIOS FRU mapping table.
Need to configure the correct values for FRU_DEVICE_ID and BMC_KCS_BASE.
For type 11 string 1 to 6 are common and implemented in this driver, the
rest are project dependent and can be added in the mainboard code.
Tested on OCP Tioga Pass.
Change-Id: I08c958dfad83216cd12545760a19d205efc2515b
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
A src/drivers/ocp/dmi/Kconfig
A src/drivers/ocp/dmi/Makefile.inc
A src/drivers/ocp/dmi/ocp_dmi.h
A src/drivers/ocp/dmi/smbios.c
4 files changed, 341 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/40308/33
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