Change in coreboot[master]: mb/google/octopus/variants/dood: Disable XHCI LFPS power management
Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41143 )
Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ......................................................................
mb/google/octopus/variants/dood: Disable XHCI LFPS power management
LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition.
Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Kenneth Chan kenneth.chan@quanta.corp-partner.google.com Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41143/1
diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index 6df9f53..e1f12cf 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -149,4 +149,5 @@
# Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index e728fe3..ab049a8 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -8,6 +8,7 @@ #include <delay.h> #include <gpio.h> #include <ec/google/chromeec/ec.h> +#include <soc/intel/apollolake/chip.h>
enum { SKU_1_LTE = 1, /* Wifi + LTE */ @@ -61,3 +62,21 @@ return; } } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && cfg->disable_xhci_lfps_pm) { + switch (google_chromeec_get_board_sku()) { + case SKU_1_LTE: + case SKU_3_LTE_2CAM: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +}
Kenneth Chan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41143 )
Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ......................................................................
Patch Set 1: Code-Review+1
Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41143 )
Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ......................................................................
Patch Set 1: Code-Review+2
Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41143 )
Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ......................................................................
Patch Set 1: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41143 )
Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/41143/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41143/1//COMMIT_MSG@9 PS1, Line 9: LTE module Please add the model.
https://review.coreboot.org/c/coreboot/+/41143/1//COMMIT_MSG@14 PS1, Line 14: If the option is set in the devicetree, the bits[7:4] in Please add it to the line above (no line break).
https://review.coreboot.org/c/coreboot/+/41143/1//COMMIT_MSG@22 PS1, Line 22: is are?
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Henry Sun, Justin TerAvest, Ren Kuo, Marco Chen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41143
to look at the new patch set (#2).
Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ......................................................................
mb/google/octopus/variants/dood: Disable XHCI LFPS power management
LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition.
Disable XHCI LFPS power management.If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] are set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Kenneth Chan kenneth.chan@quanta.corp-partner.google.com Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41143/2
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Henry Sun, Justin TerAvest, Ren Kuo, Marco Chen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41143
to look at the new patch set (#3).
Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ......................................................................
mb/google/octopus/variants/dood: Disable XHCI LFPS power management
LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition.
Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] are set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Kenneth Chan kenneth.chan@quanta.corp-partner.google.com Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41143/3
Ren Kuo has uploaded a new patch set (#4) to the change originally created by Kenneth Chan. ( https://review.coreboot.org/c/coreboot/+/41143 )
Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ......................................................................
mb/google/octopus/variants/dood: Disable XHCI LFPS power management
LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition.
Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] are set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Kenneth Chan kenneth.chan@quanta.corp-partner.google.com Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41143/4
Kenneth Chan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41143 )
Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ......................................................................
Patch Set 3:
(3 comments)
Patch Set 1:
(3 comments)
Done.
https://review.coreboot.org/c/coreboot/+/41143/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41143/1//COMMIT_MSG@9 PS1, Line 9: LTE module
Please add the model.
Done.
https://review.coreboot.org/c/coreboot/+/41143/1//COMMIT_MSG@14 PS1, Line 14: If the option is set in the devicetree, the bits[7:4] in
Please add it to the line above (no line break).
Done.
https://review.coreboot.org/c/coreboot/+/41143/1//COMMIT_MSG@22 PS1, Line 22: is
are?
Done.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Henry Sun, Justin TerAvest, Ren Kuo, Marco Chen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41143
to look at the new patch set (#5).
Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ......................................................................
mb/google/octopus/variants/dood: Disable XHCI LFPS power management
LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition.
Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] are set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Kenneth Chan kenneth.chan@quanta.corp-partner.google.com Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41143/5
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Henry Sun, Justin TerAvest, Ren Kuo, Marco Chen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41143
to look at the new patch set (#6).
Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ......................................................................
mb/google/octopus/variants/dood: Disable XHCI LFPS power management
LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition.
Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] are set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Kenneth Chan kenneth.chan@quanta.corp-partner.google.com Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41143/6
Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41143 )
Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ......................................................................
Patch Set 5:
(3 comments)
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/41143/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41143/1//COMMIT_MSG@9 PS1, Line 9: LTE module
Please add the model.
Fibocom L850-GL
https://review.coreboot.org/c/coreboot/+/41143/1//COMMIT_MSG@14 PS1, Line 14: If the option is set in the devicetree, the bits[7:4] in
Please add it to the line above (no line break).
done!
https://review.coreboot.org/c/coreboot/+/41143/1//COMMIT_MSG@22 PS1, Line 22: is
are?
are
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41143 )
Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ......................................................................
mb/google/octopus/variants/dood: Disable XHCI LFPS power management
LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition.
Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] are set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Kenneth Chan kenneth.chan@quanta.corp-partner.google.com Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41143 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Marco Chen marcochen@google.com Reviewed-by: Ren Kuo ren.kuo@quanta.corp-partner.google.com --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Ren Kuo: Looks good to me, approved Marco Chen: Looks good to me, approved Kenneth Chan: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index 6df9f53..e1f12cf 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -149,4 +149,5 @@
# Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index e728fe3..ab049a8 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -8,6 +8,7 @@ #include <delay.h> #include <gpio.h> #include <ec/google/chromeec/ec.h> +#include <soc/intel/apollolake/chip.h>
enum { SKU_1_LTE = 1, /* Wifi + LTE */ @@ -61,3 +62,21 @@ return; } } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && cfg->disable_xhci_lfps_pm) { + switch (google_chromeec_get_board_sku()) { + case SKU_1_LTE: + case SKU_3_LTE_2CAM: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +}
-
Kenneth Chan (Code Review) -
Marco Chen (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
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Ren Kuo (Code Review)