Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39427
to look at the new patch set (#26).
Change subject: mb/ocp/tiogapass: use common GPIO config [WIP]
......................................................................
mb/ocp/tiogapass: use common GPIO config [WIP]
According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the common pad configuration from soc/intel/
common, using macros PAD_CFG_ instead of the FSP-style GPIO definitions.
This patch adds the GPIO configuration, which has the format required by
the driver from common/gpio. The data for this was taken from the
inteltool register dump with AMI firmware and converted to macros using
intelp2m (pch-pads-parser) [3,4].
[1] https://review.coreboot.org/c/coreboot/+/39425
[2] https://review.coreboot.org/c/coreboot/+/39428
[3] https://review.coreboot.org/c/coreboot/+/35643
[4] https://github.com/maxpoliak/pch-pads-parser
Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/mainboard/ocp/tiogapass/Makefile.inc
M src/mainboard/ocp/tiogapass/bootblock.c
A src/mainboard/ocp/tiogapass/gpio.h
M src/mainboard/ocp/tiogapass/ramstage.c
M src/mainboard/ocp/tiogapass/romstage.c
5 files changed, 619 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39427/26
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Gerrit-MessageType: newpatchset
Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Angel Pons, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39425
to look at the new patch set (#20).
Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
......................................................................
soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
Adds definitions that allow to use the common GPIO driver to configure
the Lewisburg PCH pads. Using the GPIO configuration from common/gpio,
unlike the FSP-style definitions from Intel RefCode [1] definitions,
is more understandable and makes the motherboards code much cleaner.
In addition, we can use utilities, such as inteltool, to analyze the
configuration of proprietary firmware to add support for new server
motherboards with Skylake-SP processors.
The pin layout in this patch corresponds to the pinctrl driver in the
Linux kernel v4.14 for Lewisburg PCH GPIO controller [2].
[1] https://designintools.intel.com/product_p/stlgrn45.htm
[2] drivers/pinctrl/intel/pinctrl-lewisburg.c
These changes are in accordance with the documentation:
[*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
(PCH) Datasheet, May 2019. Document Number: 336067-007US.
Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/soc/intel/xeon_sp/Makefile.inc
A src/soc/intel/xeon_sp/gpio.c
A src/soc/intel/xeon_sp/include/soc/gpio.h
A src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h
M src/soc/intel/xeon_sp/include/soc/pcr_ids.h
5 files changed, 884 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39425/20
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Gerrit-MessageType: newpatchset
Felix Singer has uploaded a new patch set (#32) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29480 )
Change subject: mb/kontron/bsl6: Add new Skylake COMe module
......................................................................
mb/kontron/bsl6: Add new Skylake COMe module
Add Kontron/bSL6 together with Siemens/Boxer26, a baseboard for the
bSL6.
Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
Signed-off-by: Felix Singer <felix.singer(a)secunet.com>
---
A src/mainboard/kontron/bsl6/Kconfig
A src/mainboard/kontron/bsl6/Kconfig.name
A src/mainboard/kontron/bsl6/Makefile.inc
A src/mainboard/kontron/bsl6/acpi/ec.asl
A src/mainboard/kontron/bsl6/acpi/superio.asl
A src/mainboard/kontron/bsl6/board_info.txt
A src/mainboard/kontron/bsl6/bootblock.c
A src/mainboard/kontron/bsl6/cmos.default
A src/mainboard/kontron/bsl6/cmos.layout
A src/mainboard/kontron/bsl6/devicetree.cb
A src/mainboard/kontron/bsl6/dsdt.asl
A src/mainboard/kontron/bsl6/gpio.h
A src/mainboard/kontron/bsl6/ramstage.c
A src/mainboard/kontron/bsl6/romstage.c
A src/mainboard/kontron/bsl6/variant.h
A src/mainboard/kontron/bsl6/variants/boxer26/gma-mainboard.ads
A src/mainboard/kontron/bsl6/variants/boxer26/overridetree.cb
A src/mainboard/kontron/bsl6/variants/boxer26/romstage.c
A src/mainboard/kontron/bsl6/variants/bsl6/gma-mainboard.ads
A src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb
A src/mainboard/kontron/bsl6/variants/bsl6/romstage.c
21 files changed, 823 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29480/32
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Gerrit-Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5
Gerrit-Change-Number: 29480
Gerrit-PatchSet: 32
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
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Gerrit-MessageType: newpatchset
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29480 )
Change subject: mb/kontron/bsl6: Add new Skylake COMe module
......................................................................
Patch Set 31:
(1 comment)
https://review.coreboot.org/c/coreboot/+/29480/27/src/mainboard/kontron/bsl…
File src/mainboard/kontron/bsl6/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/29480/27/src/mainboard/kontron/bsl…
PS27, Line 122: device pci 08.0 on end # Gaussian Mixture Model
> *poke*
There is no devicetree option for GmmEnable. It is set by SoC code.
chip.c
```
dev = pcidev_path_on_root(SA_DEVFN_GMM);
params->GmmEnable = dev ? dev->enabled : 0;
```
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Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
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Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
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Gerrit-Comment-Date: Tue, 07 Apr 2020 12:30:13 +0000
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Gerrit-MessageType: comment
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29480 )
Change subject: mb/kontron/bsl6: Add new Skylake COMe module
......................................................................
Patch Set 31:
(3 comments)
https://review.coreboot.org/c/coreboot/+/29480/24//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/29480/24//COMMIT_MSG@11
PS24, Line 11:
> Tested how? Payload and OS?
*poke*
https://review.coreboot.org/c/coreboot/+/29480/29/src/mainboard/kontron/bsl…
File src/mainboard/kontron/bsl6/Kconfig:
https://review.coreboot.org/c/coreboot/+/29480/29/src/mainboard/kontron/bsl…
PS29, Line 46: config CBFS_SIZE
: hex
: default 0x600000
> In the best case, it shifts convenience from one use case to another. In the worst […]
Done
https://review.coreboot.org/c/coreboot/+/29480/27/src/mainboard/kontron/bsl…
File src/mainboard/kontron/bsl6/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/29480/27/src/mainboard/kontron/bsl…
PS27, Line 122: device pci 08.0 on end # Gaussian Mixture Model
> It depends on GmmEnable being set.
*poke*
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Gerrit-MessageType: comment
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40231 )
Change subject: sb/intel/bd82x6x/sata: Set values as described in BIOS spec
......................................................................
Patch Set 5:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2163
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2162
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2161
Please note: This test is under development and might not be accurate at all!
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