coreboot-gerrit April 2020

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Change in coreboot[master]: sb/lynxpoint: Use macros instead of hard-coded IDs
by Felix Singer (Code Review) 07 Apr '20

07 Apr '20

Hello build bot (Jenkins), Nico Huber, Martin Roth, Paul Menzel, Angel Pons, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36706 to look at the new patch set (#6). Change subject: sb/lynxpoint: Use macros instead of hard-coded IDs ...................................................................... sb/lynxpoint: Use macros instead of hard-coded IDs This patch replaces hard-coded PCI IDs with macros from pci_ids.h. Used documents: - 328904-003 - 329003-003 Change-Id: Ib7d0f7122e461b78526692b78f79edcafafd3286 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/include/device/pci_ids.h M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 8 files changed, 143 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/36706/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/36706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d0f7122e461b78526692b78f79edcafafd3286 Gerrit-Change-Number: 36706 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/lynxpoint: Use macros instead of hard-coded IDs
by build bot (Jenkins) (Code Review) 07 Apr '20

07 Apr '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36706 ) Change subject: sb/lynxpoint: Use macros instead of hard-coded IDs ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/36706/5/src/southbridge/intel/lynx… File src/southbridge/intel/lynxpoint/lpc.c: https://review.coreboot.org/c/coreboot/+/36706/5/src/southbridge/intel/lynx… PS5, Line 960: PCI_DEVICE_ID_INTEL_LPT_H_LPC_MOBILE_SAMPLE, /* Mobile Full Featured Engineering Sample */ line over 96 characters https://review.coreboot.org/c/coreboot/+/36706/5/src/southbridge/intel/lynx… PS5, Line 961: PCI_DEVICE_ID_INTEL_LPT_H_LPC_DESKTOP_SAMPLE, /* Desktop Full Featured Engineering Sample */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/36706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d0f7122e461b78526692b78f79edcafafd3286 Gerrit-Change-Number: 36706 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Apr 2020 07:11:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Allow mainboard to override DRAM part number
by Marco Chen (Code Review) 07 Apr '20

07 Apr '20

Hello Marco Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39860 to review the following change. Change subject: soc/intel/tigerlake: Allow mainboard to override DRAM part number ...................................................................... soc/intel/tigerlake: Allow mainboard to override DRAM part number In order to support mainboards that do not store DRAM part number in the traditional way i.e. within the CBFS SPD for soldered memory, this change provides a runtime callback to allow mainboards to provide DRAM part number from a custom location e.g. external EEPROM on volteer / dedede. For other boards it should be a NOP since the weak implementation of mainboard_get_dram_part_num does nothing. BUG=b:152019429 Change-Id: If940a76d36a7645a7441ba418aa7aec9af9f6319 Signed-off-by: Marco Chen <marcochen(a)google.com> --- M src/soc/intel/tigerlake/include/soc/romstage.h M src/soc/intel/tigerlake/romstage/romstage.c 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/39860/1 diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h index 1672e8b..9c8758a 100644 --- a/src/soc/intel/tigerlake/include/soc/romstage.h +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -17,6 +17,8 @@ #include <fsp/api.h> +/* Provide a callback to allow mainboard to override the DRAM part number. */ +void mainboard_get_dram_part_num(const char **part_num, size_t *len); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void pch_init(void); diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index f78ea29..1ad6847 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -33,6 +33,11 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } +void __weak mainboard_get_dram_part_num(const char **part_num, size_t *len) +{ + /* Default weak implementation, no need to override part number. */ +} + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { @@ -47,6 +52,8 @@ const uint8_t smbios_memory_info_guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID; const uint8_t *serial_num; + const char *dram_part_num; + size_t dram_part_num_len; /* Locate the memory info HOB, presence validated by raminit */ meminfo_hob = fsp_find_extension_hob_by_guid( @@ -86,6 +93,14 @@ if (src_dimm->Status != DIMM_PRESENT) continue; + dram_part_num_len = sizeof(src_dimm->ModulePartNum); + dram_part_num = (const char *) + &src_dimm->ModulePartNum[0]; + + /* Allow mainboard to override DRAM part number. */ + mainboard_get_dram_part_num(&dram_part_num, + &dram_part_num_len); + u8 memProfNum = meminfo_hob->MemoryProfile; serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL; -- To view, visit https://review.coreboot.org/c/coreboot/+/39860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If940a76d36a7645a7441ba418aa7aec9af9f6319 Gerrit-Change-Number: 39860 Gerrit-PatchSet: 1 Gerrit-Owner: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
by Andrey Petrov (Code Review) 07 Apr '20

07 Apr '20

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39425 ) Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver ...................................................................... Patch Set 19: Code-Review+2 so we took a deeper dive into GPIO discrepancies between vendor bios and coreboot. we compared outputs of inteltool -G on vendor bios and with coreboot running this patch stack. there are certain differences: sdiff -w 100 -s tiogapass_coreboot_inteltool_gpio.txt tiogapass_vendorbios_inteltool_gpio.txt 0x0080: 0x00000000 (HOSTSW_OWN_GPP_A) | 0x0080: 0x00f7ffff (HOSTSW_OWN_GPP_A) 0x0084: 0x00000000 (HOSTSW_OWN_GPP_B) | 0x0084: 0x00ffffff (HOSTSW_OWN_GPP_B) 0x0088: 0x00000000 (HOSTSW_OWN_GPP_F) | 0x0088: 0x00ffffff (HOSTSW_OWN_GPP_F) 0x0060: 0x00000000 (PADCFGLOCK_GPP_C_0) | 0x0060: 0x00000200 (PADCFGLOCK_GPP_C_0) 0x0064: 0x00000000 (PADCFGLOCKTX_GPP_C_0) | 0x0064: 0x00000200 (PADCFGLOCKTX_GPP_C_0) 0x0070: 0x00000000 (PADCFGLOCK_GPP_E_0) | 0x0070: 0x00000003 (PADCFGLOCK_GPP_E_0) 0x0080: 0x00000000 (HOSTSW_OWN_GPP_C_0) | 0x0080: 0x002fbb04 (HOSTSW_OWN_GPP_C_0) 0x0084: 0x00000000 (HOSTSW_OWN_GPP_D_0) | 0x0084: 0x00fffffe (HOSTSW_OWN_GPP_D_0) 0x0088: 0x00000000 (HOSTSW_OWN_GPP_E_0) | 0x0088: 0x00001fff (HOSTSW_OWN_GPP_E_0) 0x0108: 0x00000000 (GPI_IS_GPP_E_0) | 0x0108: 0x00000003 (GPI_IS_GPP_E_0) 0x0128: 0x00000003 (GPI_GPE_STS_GPP_E_0) | 0x0128: 0x00000000 (GPI_GPE_STS_GPP_E_0) 0x0140: 0x00c00000 (GPI_SMI_STS_GPP_C_0) | 0x0140: 0x00400000 (GPI_SMI_STS_GPP_C_0) 0x0144: 0x00000001 (GPI_SMI_STS_GPP_D_0) | 0x0144: 0x00000000 (GPI_SMI_STS_GPP_D_0) 0x0148: 0x00000003 (GPI_SMI_STS_GPP_E_0) | 0x0148: 0x00000000 (GPI_SMI_STS_GPP_E_0) 0x0154: 0x00000000 (GPI_SMI_EN_GPP_D_0) | 0x0154: 0x00000001 (GPI_SMI_EN_GPP_D_0) 0x0560: 0x0000004444000100 GPP_D20 GPIO| 0x0560: 0x0000004444000102 GPP_D20 GPIO 0x0080: 0x00000000 (HOSTSW_OWN_GPD_0) | 0x0080: 0x00000ffe (HOSTSW_OWN_GPD_0) 0x0080: 0x00000000 (HOSTSW_OWN_GPP_I_0) | 0x0080: 0x000007ff (HOSTSW_OWN_GPP_I_0) 0x0400: 0x0000001844000902 GPP_I0 LAN_| 0x0400: 0x0000001844000900 GPP_I0 LAN_T 0x0080: 0x00000000 (HOSTSW_OWN_GPP_J) | 0x0080: 0x00ffffff (HOSTSW_OWN_GPP_J) 0x0084: 0x00000000 (HOSTSW_OWN_GPP_K) | 0x0084: 0x000007ff (HOSTSW_OWN_GPP_K) 0x0440: 0x0000002044000600 GPP_J8 LAN | 0x0440: 0x0000002044000602 GPP_J8 LAN_I 0x0450: 0x0000002244000600 GPP_J10 LAN | 0x0450: 0x0000002244000602 GPP_J10 LAN_I 0x0460: 0x0000002444000600 GPP_J12 LAN | 0x0460: 0x0000002444000602 GPP_J12 LAN_I 0x0470: 0x0000002644000600 GPP_J14 LAN | 0x0470: 0x0000002644000602 GPP_J14 LAN_I 0x04c0: 0x0000003044000102 GPP_K0 GPI | 0x04c0: 0x0000003044000100 GPP_K0 GPIO 0x0060: 0x00000000 (PADCFGLOCK_GPP_G) | 0x0060: 0x00400000 (PADCFGLOCK_GPP_G) 0x0064: 0x00000000 (PADCFGLOCKTX_GPP_G) | 0x0064: 0x00400000 (PADCFGLOCKTX_GPP_G) 0x0080: 0x00000000 (HOSTSW_OWN_GPP_G) | 0x0080: 0x00efffff (HOSTSW_OWN_GPP_G) 0x0084: 0x00000000 (HOSTSW_OWN_GPP_H) | 0x0084: 0x00fc93df (HOSTSW_OWN_GPP_H) 0x0088: 0x00000000 (HOSTSW_OWN_GPP_L) | 0x0088: 0x000ffffc (HOSTSW_OWN_GPP_L) 0x0570: 0x0000004f44000100 GPP_H22 GPIO| 0x0570: 0x0000004f44000102 GPP_H22 GPIO 0x0578: 0x0000005044000100 GPP_H23 GPIO| 0x0578: 0x0000005044000102 GPP_H23 GPIO So it looks like the difference is mostly in pad ownership. Common gpio code seems to have rather convoluted logic w.r.t setting pad ownership. We may need to add additional macros if we want to replicate pad config with 100% fidelity. But I think this may not be needed. At any rate I think we have good confidence this patch correctly defines all the offsets and community numbers, so I think it can land -- To view, visit https://review.coreboot.org/c/coreboot/+/39425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Gerrit-Change-Number: 39425 Gerrit-PatchSet: 19 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 07 Apr 2020 04:37:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/octopus/variants/phaser: Disable xHCI compliance mode
by Tommie Lin (Code Review) 07 Apr '20

07 Apr '20

Tommie Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39968 ) Change subject: mb/google/octopus/variants/phaser: Disable xHCI compliance mode ...................................................................... mb/google/octopus/variants/phaser: Disable xHCI compliance mode BRANCH=octopus BUG=NONE TEST=Verified usb operation successfully. Signed-off-by: tong.lin <tong.lin(a)bitland.corp-partner.google.com> Change-Id: I3e6ab6ec0c4865cf2467da900f13d18468ff356f --- M src/mainboard/google/octopus/variants/phaser/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/39968/1 diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index 625c2a6..3ae365c 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -173,4 +173,7 @@ end end # - I2C 7 end + + # Disable compliance mode + register "DisableComplianceMode" = "1" end -- To view, visit https://review.coreboot.org/c/coreboot/+/39968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e6ab6ec0c4865cf2467da900f13d18468ff356f Gerrit-Change-Number: 39968 Gerrit-PatchSet: 1 Gerrit-Owner: Tommie Lin <tong.lin(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/delatur: Add support to enable GbE
by Varun Joshi (Code Review) 07 Apr '20

07 Apr '20

Hello Varun Joshi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40236 to review the following change. Change subject: mb/delatur: Add support to enable GbE ...................................................................... mb/delatur: Add support to enable GbE - Change in fmd file to incorporate GbE. Signed-off-by: Varun Joshi <varun.joshi(a)intel.corp-partner.google.com> Change-Id: I7530b13de8888e475dc4a4983572ed85dc1e345b --- M src/mainboard/google/deltaur/chromeos.fmd 1 file changed, 12 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40236/1 diff --git a/src/mainboard/google/deltaur/chromeos.fmd b/src/mainboard/google/deltaur/chromeos.fmd index d0cf8e9..8ab47c2 100644 --- a/src/mainboard/google/deltaur/chromeos.fmd +++ b/src/mainboard/google/deltaur/chromeos.fmd @@ -1,26 +1,27 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x604000 { + SI_ALL@0x0 0x606000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 - SI_ME@0x101000 0x4ff000 - SI_PDR(PRESERVE)@0x600000 0x4000 + SI_GBE@0x101000 0x2000 + SI_ME@0x103000 0x4ff000 + SI_PDR(PRESERVE)@0x602000 0x4000 } - SI_BIOS@0x604000 0x19fc000 { - RW_DIAG@0x0 0x10cc000 { - RW_LEGACY(CBFS)@0x0 0x10bc000 - DIAG_NVRAM@0x10bc000 0x10000 + SI_BIOS@0x606000 0x19fa000 { + RW_DIAG@0x0 0x10ca000 { + RW_LEGACY(CBFS)@0x0 0x10ba000 + DIAG_NVRAM@0x10ba000 0x10000 } - RW_SECTION_A@0x10cc000 0x280000 { + RW_SECTION_A@0x10ca000 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 RW_FWID_A@0x27ffc0 0x40 } - RW_SECTION_B@0x134c000 0x280000 { + RW_SECTION_B@0x134a000 0x280000 { VBLOCK_B@0x0 0x10000 FW_MAIN_B(CBFS)@0x10000 0x26ffc0 RW_FWID_B@0x27ffc0 0x40 } - RW_MISC@0x15cc000 0x30000 { + RW_MISC@0x15ca000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -33,7 +34,7 @@ RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - WP_RO@0x15fc000 0x400000 { + WP_RO@0x15fa000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/40236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7530b13de8888e475dc4a4983572ed85dc1e345b Gerrit-Change-Number: 40236 Gerrit-PatchSet: 1 Gerrit-Owner: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST] dead code in the bootblock? how does the error look like?
by Nico Huber (Code Review) 07 Apr '20

07 Apr '20

Hello Julius Werner, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40241 to review the following change. Change subject: [TEST] dead code in the bootblock? how does the error look like? ...................................................................... [TEST] dead code in the bootblock? how does the error look like? Change-Id: Ib3fab91af136f874843bc59a9824e45bf873f6c8 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/lib/bootblock.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/40241/1 diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 565d619..a7cccb6 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -10,6 +10,7 @@ #include <program_loading.h> #include <symbols.h> #include <timestamp.h> +#include <assert.h> DECLARE_OPTIONAL_REGION(timestamp); @@ -60,6 +61,8 @@ timestamp_add_now(TS_END_BOOTBLOCK); + dead_code(); + run_romstage(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3fab91af136f874843bc59a9824e45bf873f6c8 Gerrit-Change-Number: 40241 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Add ECC detection support
by Angel Pons (Code Review) 07 Apr '20

07 Apr '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22214 ) Change subject: nb/intel/sandybridge/raminit: Add ECC detection support ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/22214/12/src/northbridge/intel/san… File src/northbridge/intel/sandybridge/raminit.c: https://review.coreboot.org/c/coreboot/+/22214/12/src/northbridge/intel/san… PS12, Line 311: ctrl.ecc_forced || > it is needed; when ctrl.ecc_forced is true, ctrl. […] Ah, that's weird... -- To view, visit https://review.coreboot.org/c/coreboot/+/22214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a Gerrit-Change-Number: 22214 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Apr 2020 22:38:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/gru: Use the fmap with vboot
by Angel Pons (Code Review) 07 Apr '20

07 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40142 ) Change subject: mb/google/gru: Use the fmap with vboot ...................................................................... mb/google/gru: Use the fmap with vboot Otherwise, the build process will fail when vboot is selected. Change-Id: Ie7b5d0be9ed0621eb4a9c9117f4f5b7d3cdfe741 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/gru/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40142/1 diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 819c448..e933780 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -94,6 +94,10 @@ depends on DRIVERS_UART default 0xFF1A0000 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if VBOOT + ########################################################## #### Update below when adding a new derivative board. #### ########################################################## -- To view, visit https://review.coreboot.org/c/coreboot/+/40142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7b5d0be9ed0621eb4a9c9117f4f5b7d3cdfe741 Gerrit-Change-Number: 40142 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527.
by Tim Wawrzynczak (Code Review) 07 Apr '20

07 Apr '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40026 ) Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527. ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/40026/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40026/7//COMMIT_MSG@11 PS7, Line 11: FSP-M UPDs added: - PchTraceHubMode - CpuTraceHubMode FSP-S UPDs added: - D3HotEnable - D3ColdEnable - RtcMemoryLock -- To view, visit https://review.coreboot.org/c/coreboot/+/40026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47 Gerrit-Change-Number: 40026 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Apr 2020 22:31:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2020