Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37196 )
Change subject: [WIP]cpu/x86/cache: CLFLUSH programs to memory before running
......................................................................
[WIP]cpu/x86/cache: CLFLUSH programs to memory before running
When cbmem is initialized in romstage and postcar placed in
the stage cache + cbmem where it is run, the assumption is made
that this are all in UC memory such that calling invd in
postcar is ok.
For performance reasons (e.g. postcar decompression) it is desirable
to cache cbmem and the stage cache during romstage. Another reason
is that AGESA sets up MTRR during romstage to cache all dram, which
is currently worked around by using additional MTRR to make that UC.
TODO be nice to reviewers and spit some parts off.
UNTESTED
Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/postcar_loader.c
M src/cpu/x86/cache/Makefile.inc
M src/cpu/x86/cache/cache.c
M src/include/cpu/x86/cache.h
4 files changed, 68 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/37196/1
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index b53cbf8..53ab4f9 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -208,6 +208,21 @@
MTRR_TYPE_WRBACK);
}
+/*
+ * POSTCAR will call invd so don't make assumptions on cbmem
+ * and external stage cache being UC.
+ */
+static void postcar_flush_cache(void)
+{
+ uintptr_t stage_cache_base;
+ size_t stage_cache_size;
+ prog_segment_loaded((uintptr_t)cbmem_top(), cbmem_overhead_size(), SEG_FINAL);
+ if (CONFIG(TSEG_STAGE_CACHE)) {
+ stage_cache_external_region((void **)&stage_cache_base, &stage_cache_size);
+ prog_segment_loaded(stage_cache_base, stage_cache_size, SEG_FINAL);
+ }
+}
+
void run_postcar_phase(struct postcar_frame *pcf)
{
struct prog prog =
@@ -222,8 +237,10 @@
parameters between S3 resume and normal boot. On the
platforms where the values are the same it's a nop. */
finalize_load(prog.arg, pcf->stack);
- } else
+ } else {
load_postcar_cbfs(&prog, pcf);
+ postcar_flush_cache();
+ }
/* As postcar exist, it's end of romstage here */
timestamp_add_now(TS_END_ROMSTAGE);
diff --git a/src/cpu/x86/cache/Makefile.inc b/src/cpu/x86/cache/Makefile.inc
index b33b9ee..759488e 100644
--- a/src/cpu/x86/cache/Makefile.inc
+++ b/src/cpu/x86/cache/Makefile.inc
@@ -1 +1,2 @@
+romstage-y += cache.c
ramstage-y += cache.c
diff --git a/src/cpu/x86/cache/cache.c b/src/cpu/x86/cache/cache.c
index 2313c4d..ac2c45b 100644
--- a/src/cpu/x86/cache/cache.c
+++ b/src/cpu/x86/cache/cache.c
@@ -11,8 +11,11 @@
* GNU General Public License for more details.
*/
+#include <cbmem.h>
+#include <program_loading.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
+#include <arch/cpu.h>
void x86_enable_cache(void)
{
@@ -20,3 +23,47 @@
printk(BIOS_INFO, "Enabling cache\n");
enable_cache();
}
+
+int clflush_supported(void)
+{
+ return (cpuid_edx(1) >> 19) & 1;
+}
+
+static void clflush_region(uintptr_t start, size_t size)
+{
+ uintptr_t addr;
+ size_t cl_size = (cpuid_ebx(1) >> 8) & 0xff;
+ if (!clflush_supported())
+ return;
+ for (addr = (start / cl_size) * cl_size; addr < start + size; addr += cl_size)
+ clflush((void *)addr);
+}
+
+static int dram_ready;
+
+/*
+ * For each segment of a program loaded this function is called
+ * to invalidate caches for the addresses of the loaded segment
+ */
+void arch_segment_loaded(uintptr_t start, size_t size, int flags)
+{
+ /* INVD is only called in postcar stage so we only need
+ to make sure that our things hit dram during romstage. */
+ if (!ENV_ROMSTAGE)
+ return;
+ if (flags != SEG_FINAL)
+ return;
+ if (!dram_ready)
+ return;
+
+ if (!clflush_supported())
+ printk(BIOS_DEBUG, "Not flushing cache to ram, CLFLUSH not supported\n");
+ clflush_region(start, size);
+}
+
+static void set_dram_ready(int unused)
+{
+ dram_ready = 1;
+}
+
+ROMSTAGE_CBMEM_INIT_HOOK(set_dram_ready);
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index 713ca32..2d2727f 100644
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -55,6 +55,8 @@
asm volatile ("clflush (%0)"::"r" (addr));
}
+int clflush_supported(void);
+
/* The following functions require the __always_inline due to AMD
* function STOP_CAR_AND_CPU that disables cache as
* RAM, the cache as RAM stack can no longer be used. Called
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b
Gerrit-Change-Number: 37196
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36674 )
Change subject: arch/x86: Add option to compress postcar stage
......................................................................
arch/x86: Add option to compress postcar stage
The LZ4 decompressor was already linked in romstage.
Change-Id: I89fdc6066027447bf72968c66e6f5eb5fbb630c7
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
M src/arch/x86/Makefile.inc
2 files changed, 19 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/36674/1
diff --git a/src/Kconfig b/src/Kconfig
index 0d56291..17bf545 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -158,6 +158,16 @@
that decompression might slow down booting if the boot flash
is connected through a slow link (i.e. SPI).
+config COMPRESS_POSTCAR
+ bool "Compress postcar with LZ4"
+ depends on POSTCAR_STAGE
+ # Default value set at the end of the file
+ help
+ Compress postcar with LZ4 to save flash space and speed up boot,
+ since the time for reading the image from SPI (and in the vboot
+ case verifying it) is usually much greater than the time spent
+ decompressing.
+
config COMPRESS_PRERAM_STAGES
bool "Compress romstage and verstage with LZ4"
depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
@@ -1203,6 +1213,9 @@
config COMPRESS_RAMSTAGE
default y if !UNCOMPRESSED_RAMSTAGE
+config COMPRESS_POSTCAR
+ default y
+
config COMPRESS_PRERAM_STAGES
depends on !ARCH_X86
default y
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 447fd57..8c35176 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -278,11 +278,16 @@
$(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod
cp $< $@
+CBFS_POSTCAR_COMPRESS_FLAG := none
+ifeq ($(CONFIG_COMPRESS_POSTCAR),y)
+CBFS_POSTCAR_COMPRESS_FLAG := lz4
+endif
+
# Add postcar to CBFS
cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar
$(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf
$(CONFIG_CBFS_PREFIX)/postcar-type := stage
-$(CONFIG_CBFS_PREFIX)/postcar-compression := none
+$(CONFIG_CBFS_PREFIX)/postcar-compression := $(CBFS_POSTCAR_COMPRESS_FLAG)
###############################################################################
# ramstage
--
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Gerrit-Branch: master
Gerrit-Change-Id: I89fdc6066027447bf72968c66e6f5eb5fbb630c7
Gerrit-Change-Number: 36674
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Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32063
Change subject: Mistral: Enable USB in romstage
......................................................................
Mistral: Enable USB in romstage
Enable USB support for mistral in romstage.
TEST=build & run
Change-Id: I5c2bbe16aa3601e014a2b77d192565402ed23794
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
---
M src/mainboard/google/mistral/Makefile.inc
M src/mainboard/google/mistral/mainboard.c
A src/mainboard/google/mistral/romstage.c
3 files changed, 48 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32063/1
diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc
index dfb0bbc..2cb9631 100644
--- a/src/mainboard/google/mistral/Makefile.inc
+++ b/src/mainboard/google/mistral/Makefile.inc
@@ -11,6 +11,7 @@
romstage-y += memlayout.ld
romstage-y += chromeos.c
romstage-y += reset.c
+romstage-y += romstage.c
ramstage-y += memlayout.ld
ramstage-y += chromeos.c
diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c
index b45657f..1d62adb 100644
--- a/src/mainboard/google/mistral/mainboard.c
+++ b/src/mainboard/google/mistral/mainboard.c
@@ -17,6 +17,20 @@
#include <bootblock_common.h>
#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/usb.h>
+
+static struct usb_board_data usb1_board_data = {
+ .parameter_override_x0 = 0x63,
+ .parameter_override_x1 = 0x03,
+ .parameter_override_x0 = 0x1d,
+ .parameter_override_x1 = 0x03,
+};
+
+static void setup_usb(void)
+{
+ /* Setting Secondary usb controller */
+ setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data);
+}
static void mainboard_init(struct device *dev)
{
@@ -24,6 +38,8 @@
/* Copy WIFI calibration data into CBMEM. */
cbmem_add_vpd_calibration_data();
}
+
+ setup_usb();
}
static void mainboard_enable(struct device *dev)
diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c
new file mode 100644
index 0000000..41ee4ed
--- /dev/null
+++ b/src/mainboard/google/mistral/romstage.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/stages.h>
+#include <soc/usb.h>
+
+static void prepare_usb(void)
+{
+ /*
+ * Do DWC3 core and phy reset. Kick these resets off early
+ * so they get atleast 1msec to settle.
+ */
+ reset_usb(HSUSB_HS_PORT_1);
+}
+
+void platform_romstage_main(void)
+{
+ prepare_usb();
+}
--
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Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32719
Change subject: drivers/apple: Add hybrid graphics driver
......................................................................
drivers/apple: Add hybrid graphics driver
Hybrid graphics driver for Apple MacBook Pro.
Change-Id: I22b66622cd2da0e9951ee726d650d204fbb8a5bc
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
A src/drivers/apple/hybrid_graphics/Kconfig
A src/drivers/apple/hybrid_graphics/Makefile.inc
A src/drivers/apple/hybrid_graphics/chip.h
A src/drivers/apple/hybrid_graphics/gmux.c
A src/drivers/apple/hybrid_graphics/gmux.h
A src/drivers/apple/hybrid_graphics/hybrid_graphics.c
A src/drivers/apple/hybrid_graphics/hybrid_graphics.h
A src/drivers/apple/hybrid_graphics/romstage.c
8 files changed, 417 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32719/1
diff --git a/src/drivers/apple/hybrid_graphics/Kconfig b/src/drivers/apple/hybrid_graphics/Kconfig
new file mode 100644
index 0000000..252373f
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/Kconfig
@@ -0,0 +1,3 @@
+config DRIVERS_APPLE_HYBRID_GRAPHICS
+ bool
+ default n
diff --git a/src/drivers/apple/hybrid_graphics/Makefile.inc b/src/drivers/apple/hybrid_graphics/Makefile.inc
new file mode 100644
index 0000000..ea45b45
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/Makefile.inc
@@ -0,0 +1,15 @@
+#
+# This file is part of the coreboot project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-$(CONFIG_DRIVERS_APPLE_HYBRID_GRAPHICS) += gmux.c romstage.c
+ramstage-$(CONFIG_DRIVERS_APPLE_HYBRID_GRAPHICS) += gmux.c hybrid_graphics.c
diff --git a/src/drivers/apple/hybrid_graphics/chip.h b/src/drivers/apple/hybrid_graphics/chip.h
new file mode 100644
index 0000000..39434f8
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/chip.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _APPLE_HYBRID_GRAPHICS_CHIP_H_
+#define _APPLE_HYBRID_GRAPHICS_CHIP_H_
+
+enum hybrid_graphics_req {
+ HYBRID_GRAPHICS_INTEGRATED = 0,
+ HYBRID_GRAPHICS_DISCRETE = 1
+};
+
+#define HYBRID_GRAPHICS_DEFAULT_GPU HYBRID_GRAPHICS_INTEGRATED
+
+struct drivers_apple_hybrid_graphics_config {
+ unsigned int gmux_indexed;
+};
+
+#endif /* _APPLE_HYBRID_GRAPHICS_CHIP_H_ */
diff --git a/src/drivers/apple/hybrid_graphics/gmux.c b/src/drivers/apple/hybrid_graphics/gmux.c
new file mode 100644
index 0000000..e1f763a
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/gmux.c
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) Canonical Ltd. <seth.forshee(a)canonical.com>
+ * Copyright (C) 2010-2012 Andreas Heider <andreas(a)meetr.de>
+ * Copyright (C) 2015 Lukas Wunner <lukas(a)wunner.de>
+ * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <delay.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include "gmux.h"
+#include "chip.h"
+
+static int gmux_index_wait_ready(void)
+{
+ int i = 200;
+ u8 gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE);
+
+ while (i && (gwr & 0x01)) {
+ inb(GMUX_IOSTART + GMUX_PORT_READ);
+ gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE);
+ udelay(100);
+ i--;
+ }
+
+ return !!i;
+}
+
+static int gmux_index_wait_complete(void)
+{
+ int i = 200;
+ u8 gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE);
+
+ while (i && !(gwr & 0x01)) {
+ gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE);
+ udelay(100);
+ i--;
+ }
+
+ if (gwr & 0x01)
+ inb(GMUX_IOSTART + GMUX_PORT_READ);
+
+ return !!i;
+}
+
+u8 gmux_pio_read8(int port)
+{
+ return inb(GMUX_IOSTART + port);
+}
+
+u8 gmux_index_read8(int port)
+{
+ u8 val;
+
+ gmux_index_wait_ready();
+ outb((port & 0xff), GMUX_IOSTART + GMUX_PORT_READ);
+ gmux_index_wait_complete();
+ val = inb(GMUX_IOSTART + GMUX_PORT_VALUE);
+
+ return val;
+}
+
+void gmux_pio_write8(int port, u8 val)
+{
+ outb(val, GMUX_IOSTART + port);
+}
+
+
+void gmux_index_write8(int port, u8 val)
+{
+ outb(val, GMUX_IOSTART + GMUX_PORT_VALUE);
+ gmux_index_wait_ready();
+ outb(port & 0xff, GMUX_IOSTART + GMUX_PORT_WRITE);
+ gmux_index_wait_complete();
+}
+
+u32 gmux_pio_read32(int port)
+{
+ return inl(GMUX_IOSTART + port);
+}
+
+u32 gmux_index_read32(int port)
+{
+ u32 val;
+
+ gmux_index_wait_ready();
+ outb((port & 0xff), GMUX_IOSTART + GMUX_PORT_READ);
+ gmux_index_wait_complete();
+ val = inl(GMUX_IOSTART + GMUX_PORT_VALUE);
+
+ return val;
+}
+
+u8 gmux_read8(const struct device *dev, int port)
+{
+ const struct drivers_apple_hybrid_graphics_config *config = dev->chip_info;
+ if (config->gmux_indexed) {
+ return gmux_index_read8(port);
+ } else {
+ return gmux_pio_read8(port);
+ }
+}
+
+void gmux_write8(const struct device *dev, int port, u8 val)
+{
+ const struct drivers_apple_hybrid_graphics_config *config = dev->chip_info;
+ if (config->gmux_indexed) {
+ gmux_index_write8(port, val);
+ } else {
+ gmux_pio_write8(port, val);
+ }
+}
+
+u32 gmux_read32(const struct device *dev, int port)
+{
+ const struct drivers_apple_hybrid_graphics_config *config = dev->chip_info;
+ if (config->gmux_indexed) {
+ return gmux_index_read32(port);
+ } else {
+ return gmux_pio_read32(port);
+ }
+}
+
+void gmux_dgpu_power_enable(const struct device *dev, bool enable)
+{
+ if (enable) {
+ gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 1);
+ gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 3);
+ } else {
+ gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 1);
+ gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 0);
+ }
+}
+
+void gmux_switch(const struct device *dev, bool dgpu)
+{
+ if (dgpu) {
+ gmux_write8(dev, GMUX_PORT_SWITCH_DDC, 2);
+ gmux_write8(dev, GMUX_PORT_SWITCH_DISPLAY, 3);
+ } else {
+ gmux_write8(dev, GMUX_PORT_SWITCH_DDC, 1);
+ gmux_write8(dev, GMUX_PORT_SWITCH_DISPLAY, 2);
+ }
+}
+
+
diff --git a/src/drivers/apple/hybrid_graphics/gmux.h b/src/drivers/apple/hybrid_graphics/gmux.h
new file mode 100644
index 0000000..18f6722
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/gmux.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) Canonical Ltd. <seth.forshee(a)canonical.com>
+ * Copyright (C) 2010-2012 Andreas Heider <andreas(a)meetr.de>
+ * Copyright (C) 2015 Lukas Wunner <lukas(a)wunner.de>
+ * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef EC_APPLE_GMUX_H
+#define EC_APPLE_GMUX_H
+
+#define GMUX_PORT_VERSION_MAJOR 0x04
+#define GMUX_PORT_VERSION_MINOR 0x05
+#define GMUX_PORT_VERSION_RELEASE 0x06
+
+#define GMUX_PORT_SWITCH_DISPLAY 0x10
+#define GMUX_PORT_SWITCH_DDC 0x28
+#define GMUX_PORT_DISCRETE_POWER 0x50
+#define GMUX_PORT_MAX_BRIGHTNESS 0x70
+#define GMUX_PORT_BRIGHTNESS 0x74
+#define GMUX_PORT_VALUE 0xc2
+#define GMUX_PORT_READ 0xd0
+#define GMUX_PORT_WRITE 0xd4
+
+#define GMUX_PORT_INTERRUPT_ENABLE 0x14
+#define GMUX_INTERRUPT_ENABLE 0xff
+#define GMUX_INTERRUPT_DISABLE 0x00
+
+#define GMUX_BRIGHTNESS_MASK 0x00ffffff
+#define GMUX_MAX_BRIGHTNESS GMUX_BRIGHTNESS_MASK
+
+#define GMUX_IOSTART 0x700
+
+u8 gmux_index_read8(int port);
+u8 gmux_pio_read8(int port);
+u8 gmux_read8(const struct device *dev, int port);
+
+void gmux_index_write8(int port, u8 val);
+void gmux_pio_write8(int port, u8 val);
+void gmux_write8(const struct device *dev, int port, u8 val);
+
+u32 gmux_index_read32(int port);
+u32 gmux_pio_read32(int port);
+u32 gmux_read32(const struct device *dev, int port);
+
+void gmux_switch(const struct device *dev, bool dgpu);
+void gmux_dgpu_power_enable(const struct device *dev, bool enable);
+
+#endif /* EC_APPLE_GMUX_H */
diff --git a/src/drivers/apple/hybrid_graphics/hybrid_graphics.c b/src/drivers/apple/hybrid_graphics/hybrid_graphics.c
new file mode 100644
index 0000000..804eb76
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/hybrid_graphics.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <option.h>
+#include <device/device.h>
+
+#include <southbridge/intel/common/gpio.h>
+#include <console/console.h>
+#include "chip.h"
+#include "gmux.h"
+
+static void enable_dev(struct device *dev)
+{
+ printk(BIOS_INFO, "Hybrid graphics enable_dev\n");
+
+ const struct drivers_lenovo_hybrid_graphics_config *config;
+ enum hybrid_graphics_req mode;
+ u8 ver_major, ver_minor, ver_release;
+ u32 version, max_brightness, brightness;
+
+ /* Don't confuse anyone else and disable the fake device */
+ dev->enabled = 0;
+
+ config = dev->chip_info;
+ if (!config) {
+ printk(BIOS_INFO, "Hybrid graphics: Not installed\n");
+ return;
+ }
+
+ version = gmux_index_read32(GMUX_PORT_VERSION_MAJOR);
+ ver_major = (version >> 24) & 0xff;
+ ver_minor = (version >> 16) & 0xff;
+ ver_release = (version >> 8) & 0xff;
+ max_brightness = gmux_index_read32(GMUX_PORT_MAX_BRIGHTNESS);
+ brightness = gmux_index_read32(GMUX_PORT_BRIGHTNESS) & GMUX_BRIGHTNESS_MASK;
+
+ printk(BIOS_INFO, "gmux version: %d.%d.%d\n",
+ ver_major, ver_minor, ver_release);
+ printk(BIOS_INFO, "gmux max brightness: %d\n", max_brightness);
+ printk(BIOS_INFO, "gmux brightness: %d\n", brightness);
+
+ mode = HYBRID_GRAPHICS_DEFAULT_GPU;
+ get_option(&mode, "hybrid_graphics_mode");
+
+ gmux_switch(dev, mode == HYBRID_GRAPHICS_DISCRETE);
+}
+
+struct chip_operations drivers_apple_hybrid_graphics_ops = {
+ CHIP_NAME("Apple hybrid graphics driver")
+ .enable_dev = enable_dev
+};
diff --git a/src/drivers/apple/hybrid_graphics/hybrid_graphics.h b/src/drivers/apple/hybrid_graphics/hybrid_graphics.h
new file mode 100644
index 0000000..782be44
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/hybrid_graphics.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DRIVERS_APPLE_HYBRID_GRAPHICS_H_
+#define _DRIVERS_APPLE_HYBRID_GRAPHICS_H_
+
+#define HYBRID_GRAPHICS_PORT 0xff
+#define HYBRID_GRAPHICS_DEVICE 0xf
+
+void early_hybrid_graphics(bool *enable_igd, bool *enable_peg);
+
+#endif /* _DRIVERS_APPLE_HYBRID_GRAPHICS_CHIP_H_ */
diff --git a/src/drivers/apple/hybrid_graphics/romstage.c b/src/drivers/apple/hybrid_graphics/romstage.c
new file mode 100644
index 0000000..9cd5098
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/romstage.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org>
+ * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <option.h>
+#include <device/device.h>
+#include <console/console.h>
+#include "hybrid_graphics.h"
+#include "chip.h"
+#include "gmux.h"
+
+void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
+{
+ const struct drivers_apple_hybrid_graphics_config *config;
+ const struct device *dev;
+
+ enum hybrid_graphics_req mode = HYBRID_GRAPHICS_DEFAULT_GPU;
+
+ printk(BIOS_INFO, "Hybrid graphics early_hybrid_graphics\n");
+
+ /* TODO: Use generic device instead of dummy PNP device */
+ dev = dev_find_slot_pnp(HYBRID_GRAPHICS_PORT, HYBRID_GRAPHICS_DEVICE);
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "Hybrid graphics: ERROR\n");
+ *enable_igd = true;
+ *enable_peg = false;
+ return;
+ }
+
+ config = dev->chip_info;
+
+ get_option(&mode, "hybrid_graphics_mode");
+
+ if (mode == HYBRID_GRAPHICS_DISCRETE) {
+ printk(BIOS_DEBUG, "Hybrid graphics:"
+ " Disabling integrated GPU.\n");
+
+ *enable_igd = false;
+ *enable_peg = true;
+ } else if (mode == HYBRID_GRAPHICS_INTEGRATED) {
+ printk(BIOS_DEBUG, "Hybrid graphics:"
+ " Disabling discrete GPU.\n");
+
+ *enable_igd = true;
+ *enable_peg = false;
+ }
+
+ gmux_dgpu_power_enable(dev, *enable_peg);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I22b66622cd2da0e9951ee726d650d204fbb8a5bc
Gerrit-Change-Number: 32719
Gerrit-PatchSet: 1
Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com>
Gerrit-MessageType: newchange