Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29480 )
Change subject: mb/kontron/bsl6: Add new Skylake COMe module
......................................................................
Patch Set 32:
(1 comment)
https://review.coreboot.org/c/coreboot/+/29480/27/src/mainboard/kontron/bsl…
File src/mainboard/kontron/bsl6/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/29480/27/src/mainboard/kontron/bsl…
PS27, Line 122: device pci 08.0 on end # Gaussian Mixture Model
> There is no devicetree option for GmmEnable. It is set by SoC code. […]
Ack
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Gerrit-Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5
Gerrit-Change-Number: 29480
Gerrit-PatchSet: 32
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
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Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net>
Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: comment
Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39427
to look at the new patch set (#27).
Change subject: mb/ocp/tiogapass: use common GPIO config [WIP]
......................................................................
mb/ocp/tiogapass: use common GPIO config [WIP]
According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the common pad configuration from soc/intel/
common, using macros PAD_CFG_ instead of the FSP-style GPIO definitions.
This patch adds the GPIO configuration, which has the format required by
the driver from common/gpio. The data for this was taken from the
inteltool register dump with AMI firmware and converted to macros using
intelp2m (pch-pads-parser) [3,4].
[1] https://review.coreboot.org/c/coreboot/+/39425
[2] https://review.coreboot.org/c/coreboot/+/39428
[3] https://review.coreboot.org/c/coreboot/+/35643
[4] https://github.com/maxpoliak/pch-pads-parser
Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/mainboard/ocp/tiogapass/Makefile.inc
M src/mainboard/ocp/tiogapass/bootblock.c
A src/mainboard/ocp/tiogapass/gpio.h
M src/mainboard/ocp/tiogapass/ramstage.c
M src/mainboard/ocp/tiogapass/romstage.c
5 files changed, 619 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39427/27
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Gerrit-Change-Number: 39427
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Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
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Gerrit-MessageType: newpatchset
Hello build bot (Jenkins), Andrey Petrov, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39428
to look at the new patch set (#22).
Change subject: soc/xeon_sp: add configs to use common/gpio diver
......................................................................
soc/xeon_sp: add configs to use common/gpio diver
Allow the use of the common/gpio driver to create Lewisburg PCH pad
configurations for server motherboards with Skylake-SP processors.
This patch should only be applied after adding Lewisburg PCH definitions
to the soc/intel/xeon_sp code [1].
[1] https://review.coreboot.org/c/coreboot/+/39425
Change-Id: I4a8e83cad0729bbbb50ba5a2b336f6cf7c1eca13
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/soc/intel/xeon_sp/Kconfig
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/39428/22
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Gerrit-Change-Number: 39428
Gerrit-PatchSet: 22
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: newpatchset
Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Angel Pons, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39425
to look at the new patch set (#21).
Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
......................................................................
soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
Adds definitions that allow to use the common GPIO driver to configure
the Lewisburg PCH pads. Using the GPIO configuration from common/gpio,
unlike the FSP-style definitions from Intel RefCode [1] definitions,
is more understandable and makes the motherboards code much cleaner.
In addition, we can use utilities, such as inteltool, to analyze the
configuration of proprietary firmware to add support for new server
motherboards with Skylake-SP processors.
The pin layout in this patch corresponds to the pinctrl driver in the
Linux kernel v4.14 for the Lewisburg PCH GPIO controller [2].
[1] https://designintools.intel.com/product_p/stlgrn45.htm
[2] drivers/pinctrl/intel/pinctrl-lewisburg.c
These changes are in accordance with the documentation:
[*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
(PCH) Datasheet, May 2019. Document Number: 336067-007US.
Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/soc/intel/xeon_sp/Makefile.inc
A src/soc/intel/xeon_sp/gpio.c
A src/soc/intel/xeon_sp/include/soc/gpio.h
A src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h
M src/soc/intel/xeon_sp/include/soc/pcr_ids.h
5 files changed, 884 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39425/21
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