coreboot-gerrit April 2020

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Change in coreboot[master]: mb/kontron/bsl6: Add new Skylake COMe module
by Felix Singer (Code Review) 07 Apr '20

07 Apr '20

Felix Singer has uploaded a new patch set (#31) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29480 ) Change subject: mb/kontron/bsl6: Add new Skylake COMe module ...................................................................... mb/kontron/bsl6: Add new Skylake COMe module Add Kontron/bSL6 together with Siemens/Boxer26, a baseboard for the bSL6. Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- A src/mainboard/kontron/bsl6/Kconfig A src/mainboard/kontron/bsl6/Kconfig.name A src/mainboard/kontron/bsl6/Makefile.inc A src/mainboard/kontron/bsl6/acpi/ec.asl A src/mainboard/kontron/bsl6/acpi/superio.asl A src/mainboard/kontron/bsl6/board_info.txt A src/mainboard/kontron/bsl6/bootblock.c A src/mainboard/kontron/bsl6/cmos.default A src/mainboard/kontron/bsl6/cmos.layout A src/mainboard/kontron/bsl6/devicetree.cb A src/mainboard/kontron/bsl6/dsdt.asl A src/mainboard/kontron/bsl6/gpio.h A src/mainboard/kontron/bsl6/ramstage.c A src/mainboard/kontron/bsl6/romstage.c A src/mainboard/kontron/bsl6/variant.h A src/mainboard/kontron/bsl6/variants/boxer26/gma-mainboard.ads A src/mainboard/kontron/bsl6/variants/boxer26/overridetree.cb A src/mainboard/kontron/bsl6/variants/boxer26/romstage.c A src/mainboard/kontron/bsl6/variants/bsl6/gma-mainboard.ads A src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb A src/mainboard/kontron/bsl6/variants/bsl6/romstage.c 21 files changed, 823 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29480/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/29480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5 Gerrit-Change-Number: 29480 Gerrit-PatchSet: 31 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel/bd82x6x/sata: Set values as described in BIOS spec
by Nico Huber (Code Review) 07 Apr '20

07 Apr '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40231 ) Change subject: sb/intel/bd82x6x/sata: Set values as described in BIOS spec ...................................................................... sb/intel/bd82x6x/sata: Set values as described in BIOS spec Set some things missed originally because of formatting issues in the BIOS spec. Values were compared with a vendor dump. Change-Id: I27360d6ea5d1f00b1ed350f47ff40a22f19dfb05 Signed-off-by: Felix Singer <felix.singer(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40231 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/bd82x6x/sata.c 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 2693e2b..c1b61f2 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -186,6 +186,11 @@ pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); + + pci_update_config32(dev, 0x98, + ~(1 << 16 | 0x3f << 7 | 3 << 5 | 3 << 3), + 1 << 24 | 1 << 22 | 1 << 20 | 1 << 19 | + 1 << 18 | 1 << 14 | 0x04 << 7 | 1 << 3); } static void sata_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/40231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27360d6ea5d1f00b1ed350f47ff40a22f19dfb05 Gerrit-Change-Number: 40231 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/bd82x6x: Drop PCI resource reg override
by Nico Huber (Code Review) 07 Apr '20

07 Apr '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40230 ) Change subject: sb/intel/bd82x6x: Drop PCI resource reg override ...................................................................... sb/intel/bd82x6x: Drop PCI resource reg override Assignment of PCI resource registers is up to the allocator. Therefore, drop override of the PCI resource register. Change-Id: I184a263c81aa8a434fcd153406b73058914cb2f9 Signed-off-by: Felix Singer <felix.singer(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40230 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/bd82x6x/sata.c 1 file changed, 1 insertion(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 310d1a2..2693e2b 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -114,10 +114,7 @@ /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - - /* And without AHCI BAR no memory decoding */ + /* Without AHCI BAR no memory decoding */ reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); -- To view, visit https://review.coreboot.org/c/coreboot/+/40230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I184a263c81aa8a434fcd153406b73058914cb2f9 Gerrit-Change-Number: 40230 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake/acpi: Fix typo
by Subrata Banik (Code Review) 07 Apr '20

07 Apr '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40232 ) Change subject: soc/intel/tigerlake/acpi: Fix typo ...................................................................... soc/intel/tigerlake/acpi: Fix typo HSA -> HDA (High Definition Audio) Change-Id: Ic0e6ad7b26105fdd6eca6cd11edcf2236e5c7123 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/tigerlake/acpi/pci_irqs.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/40232/1 diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 7f632ba..62520b1 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -16,7 +16,7 @@ #include <soc/irq.h> Name (PICP, Package () { - /* D31:HSA, SMBUS, TraceHUB */ + /* D31:HDA, SMBUS, TraceHUB */ Package(){0x001FFFFF, 3, 0, HDA_IRQ }, Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, @@ -89,7 +89,7 @@ }) Name (PICN, Package () { - /* D31:HSA, SMBUS, TraceHUB*/ + /* D31:HDA, SMBUS, TraceHUB*/ Package () { 0x001FFFFF, 3, 0, 11 }, Package () { 0x001FFFFF, 4, 0, 11 }, Package () { 0x001FFFFF, 7, 0, 11 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/40232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0e6ad7b26105fdd6eca6cd11edcf2236e5c7123 Gerrit-Change-Number: 40232 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/pc80/tpm/tis.c: change the _HID and _CID for TPM2 device
by Michał Żygowski (Code Review) 07 Apr '20

07 Apr '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39699 ) Change subject: drivers/pc80/tpm/tis.c: change the _HID and _CID for TPM2 device ...................................................................... drivers/pc80/tpm/tis.c: change the _HID and _CID for TPM2 device According TCG PC Client Platform Firmware Profile Specification Revision 1.04 Chapter 8.1 the TPM device object should have the _CID and _HID value set to MSFT0101 for TPM2. FreeBSD also detects TPM2 device only MSFT0101 _HID and _CID only. TEST=boot FreeBSD 12.1 on PC Engines apu2 and check in dmesg that TPM2.0 is detected Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I45123f272038e664b834cabd9d8525baca0eb583 --- M src/drivers/pc80/tpm/tis.c 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39699/1 diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index a35ef83..0c8e9c3 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -896,11 +896,16 @@ acpigen_write_scope(path); acpigen_write_device(acpi_device_name(dev)); - acpigen_write_name("_HID"); - acpigen_emit_eisaid("PNP0C31"); + if (CONFIG(TPM2)) { + acpigen_write_name_string("_HID", "MSFT0101"); + acpigen_write_name_string("_CID", "MSFT0101"); + } else { + acpigen_write_name("_HID"); + acpigen_emit_eisaid("PNP0C31"); - acpigen_write_name("_CID"); - acpigen_emit_eisaid("PNP0C31"); + acpigen_write_name("_CID"); + acpigen_emit_eisaid("PNP0C31"); + } acpi_device_write_uid(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/39699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45123f272038e664b834cabd9d8525baca0eb583 Gerrit-Change-Number: 39699 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add SD Card gpio config for JSLRVP
by Ronak Kanabar (Code Review) 07 Apr '20

07 Apr '20

Hello build bot (Jenkins), Deepti Vaidya, Maulik V Vaghela, Meera Ravindranath, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39492 to look at the new patch set (#3). Change subject: mb/intel/jasperlake_rvp: Add SD Card gpio config for JSLRVP ...................................................................... mb/intel/jasperlake_rvp: Add SD Card gpio config for JSLRVP Change-Id: I8114d6980a2a542538b05f812ca2cffc15c88c22 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/39492/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/39492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8114d6980a2a542538b05f812ca2cffc15c88c22 Gerrit-Change-Number: 39492 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Deepti Vaidya <deepti.vaidya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/amd/pi/00730F01/northbridge.c: refactor IVRS generation
by Michał Żygowski (Code Review) 07 Apr '20

07 Apr '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40042 ) Change subject: nb/amd/pi/00730F01/northbridge.c: refactor IVRS generation ...................................................................... nb/amd/pi/00730F01/northbridge.c: refactor IVRS generation Use defined structures to assemble IVRS and IVHD entries. Additionally assemble IVHD type 11h which supersedes IVHD type 10h. In order to utilize all IOMMU features firmware should also expose IVHD type 11h. The new type is already supported and parsed since Xen 1.13. IVHD type 10h should still be present for backwards compatibility. TEST=boot PC Engines apu2 and disassemble IVRS using newest IASL Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I9a2c24b67adfa8ebd718caeb5eec88687dcbcc9d --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 239 insertions(+), 145 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40042/1 diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index f611bd6..56fab07 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <arch/acpi.h> +#include <arch/acpi_ivrs.h> #include <arch/ioapic.h> #include <stdint.h> #include <device/device.h> @@ -22,6 +23,7 @@ #include <device/pci_ids.h> #include <device/hypertransport.h> #include <string.h> +#include <stdlib.h> #include <lib.h> #include <cpu/cpu.h> #include <Porting.h> @@ -33,6 +35,7 @@ #include <arch/acpigen.h> #include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> +#include <southbridge/amd/pi/hudson/pci_devs.h> #define MAX_NODE_NUMS MAX_NODES #define PCIE_CAP_AER BIT(5) @@ -439,59 +442,145 @@ return (unsigned long)current; } -static void add_ivhd_dev_entry(struct device *parent, struct device *dev, - unsigned long *current, uint16_t *length, - uint8_t type, uint8_t data) +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) { - uint8_t *p; - p = (uint8_t *) *current; + /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ + unsigned long offset = ((current + 0x7) & (~ 0x7)) - current; + ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)(current + offset); - if (type == 0x2) { - /* Entry type */ - p[0] = type; - /* Device */ - p[1] = dev->path.pci.devfn; - /* Bus */ - p[2] = dev->bus->secondary; - /* Data */ - p[3] = data; - /* [4:7] Padding */ - p[4] = 0x0; - p[5] = 0x0; - p[6] = 0x0; - p[7] = 0x0; - *length += 8; - *current += 8; - } else if (type == 0x42) { - /* Entry type */ - p[0] = type; - /* Device */ - p[1] = dev->path.pci.devfn; - /* Bus */ - p[2] = dev->bus->secondary; - /* Data */ - p[3] = 0x0; - /* Reserved */ - p[4] = 0x0; - /* Device */ - p[5] = parent->path.pci.devfn; - /* Bus */ - p[6] = parent->bus->secondary; - /* Reserved */ - p[7] = 0x0; - *length += 8; - *current += 8; + ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; + ivhd_ioapic->reserved = 0x0000; + ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | + IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | + IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; + ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */ + ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); + ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; + current += sizeof(ivrs_ivhd_special_t) + offset; + + ivhd_ioapic = (ivrs_ivhd_special_t *)current; + + ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; + ivhd_ioapic->reserved = 0x0000; + ivhd_ioapic->dte_setting = 0x00; + ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */ + ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); + ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; + current += sizeof(ivrs_ivhd_special_t); + + return current; +} + +static unsigned long ivhd_describe_hpet(unsigned long current, uint16_t *ivhd_length) +{ + /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ + unsigned long offset = ((current + 0x7) & (~ 0x7)) - current; + ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)(current + offset); + + ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; + ivhd_hpet->reserved = 0x0000; + ivhd_hpet->dte_setting = 0x00; + ivhd_hpet->handle = 0x00; + ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); + ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; + current += sizeof(ivrs_ivhd_special_t) + offset; + *ivhd_length += sizeof(ivrs_ivhd_special_t) + offset; + + return current; +} + +static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, + uint16_t end_devid, uint8_t setting, uint16_t *ivhd_length) +{ + /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ + unsigned long offset = ((current + 0x3) & (~ 0x3)) - current; + ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)(current + offset); + + /* Create the start range IVHD entry */ + ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; + ivhd_range->dev_id = start_devid; + ivhd_range->dte_setting = setting; + + current += sizeof(ivrs_ivhd_generic_t) + offset; + *ivhd_length += sizeof(ivrs_ivhd_generic_t) + offset; + + /* Create the end range IVHD entry */ + ivhd_range = (ivrs_ivhd_generic_t *)current; + ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; + ivhd_range->dev_id = end_devid; + ivhd_range->dte_setting = setting; + + current += sizeof(ivrs_ivhd_generic_t) + offset; + *ivhd_length += sizeof(ivrs_ivhd_generic_t) + offset; + + return current; +} + +static void add_ivhd_dev_entry(struct device *parent, struct device *dev, + unsigned long *current, uint16_t *ivhd_length, uint8_t type, + uint8_t data) +{ + unsigned long offset; + + if (type == IVHD_DEV_4_BYTE_SELECT) { + /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ + offset = ((*current + 0x3) & (~ 0x3)) - *current; + ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)(*current + offset); + + ivhd_entry->type = type; + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dte_setting = data; + + *current += sizeof(ivrs_ivhd_generic_t) + offset; + *ivhd_length += sizeof(ivrs_ivhd_generic_t) + offset; + } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { + /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ + offset = ((*current + 0x7) & (~ 0x7)) - *current; + ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)(*current + offset); + + ivhd_entry->type = type; + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dte_setting = data; + ivhd_entry->reserved1 = 0; + ivhd_entry->reserved2 = 0; + ivhd_entry->source_dev_id = parent->path.pci.devfn | (parent->bus->secondary << 8); + + *current += sizeof(ivrs_ivhd_alias_t) + offset; + *ivhd_length += sizeof(ivrs_ivhd_alias_t) + offset; } } -static void add_ivrs_device_entries(struct device *parent, struct device *dev, +static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, + unsigned long *current, uint16_t *ivhd_length) +{ + unsigned int header_type, is_pcie; + + header_type = dev->hdr_type & 0x7f; + is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); + + if (((header_type == PCI_HEADER_TYPE_NORMAL) || + (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { + /* Device or Bridge is PCIe */ + add_ivhd_dev_entry(parent, dev, current, ivhd_length, IVHD_DEV_4_BYTE_SELECT, + 0x0); + } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { + /* Device is legacy PCI or PCI-X */ + add_ivhd_dev_entry(parent, dev, current, ivhd_length, + IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); + } +} + +static void add_ivhd_device_entries(struct device *parent, struct device *dev, unsigned int depth, int linknum, int8_t *root_level, - unsigned long *current, uint16_t *length) + unsigned long *current, uint16_t *ivhd_length) { struct device *sibling; struct bus *link; - unsigned int header_type; - unsigned int is_pcie; + + if (!root_level) { + root_level = malloc(sizeof(int8_t)); + *root_level = -1; + } if (dev->path.type == DEVICE_PATH_PCI) { @@ -500,30 +589,8 @@ *root_level = depth; if ((*root_level != -1) && (dev->enabled)) { - if (depth == *root_level) { - if (dev->path.pci.devfn == (0x14 << 3)) { - /* SMBUS controller */ - add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x97); - } else if (dev->path.pci.devfn != 0x2 && - dev->path.pci.devfn < (0x2 << 3)) { - /* FCH control device */ - } else { - /* Other devices */ - add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0); - } - } else { - header_type = dev->hdr_type & 0x7f; - is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); - if (((header_type == PCI_HEADER_TYPE_NORMAL) || - (header_type == PCI_HEADER_TYPE_BRIDGE)) - && is_pcie) { - /* Device or Bridge is PCIe */ - add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0); - } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && - !is_pcie) { - add_ivhd_dev_entry(parent, dev, current, length, 0x42, 0x0); - /* Device is legacy PCI or PCI-X */ - } + if (depth != *root_level) { + ivrs_add_device_or_bridge(parent, dev, current, ivhd_length); } } } @@ -531,123 +598,150 @@ for (link = dev->link_list; link; link = link->next) for (sibling = link->children; sibling; sibling = sibling->sibling) - add_ivrs_device_entries(dev, sibling, depth + 1, depth, - root_level, current, length); + add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, + current, ivhd_length); + + free(root_level); } -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) +#define IOMMU_MMIO32(x) *((volatile uint32_t *)(x)) +#define EFR_SUPPORT BIT(27) + +static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs_agesa) { - uint8_t *p; + acpi_ivrs_ivhd11_t *ivhd_11; + unsigned long current_backup; - uint32_t apicid_sb800; - uint32_t apicid_northbridge; + /* + * These devices should be already found by previous function. + * Do not perform NULL checks. + */ + struct device *nb_dev = pcidev_on_root(0, 0); + struct device *iommu_dev = pcidev_on_root(0, 2); - apicid_sb800 = CONFIG_MAX_CPUS; - apicid_northbridge = CONFIG_MAX_CPUS + 1; + /* + * In order ot utilize all features, firmware should expose type 11h + * IVHD which supersedes the type 10h. + */ + memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); + ivhd_11 = (acpi_ivrs_ivhd11_t *)current; - /* Describe NB IOAPIC */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0x0; /* Data */ - p[4] = apicid_northbridge; /* IOAPIC ID */ - p[5] = 0x0; /* Device 0 Function 0 */ - p[6] = 0x0; /* Northbridge bus */ - p[7] = 0x1; /* Variety */ - current += 8; + /* Enable EFR */ + ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; + /* For type 11h bits 6 and 7 are reserved */ + ivhd_11->flags = ivrs_agesa->ivhd.flags & 0x3f; + ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); + /* BDF <bus>:00.2 */ + ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); + /* PCI Capability block 0x40 (type 0xf, "Secure device") */ + ivhd_11->capability_offset = 0x40; + ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; + ivhd_11->iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; + ivhd_11->pci_segment_group = 0x0000; + ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info; + ivhd_11->iommu_attributes.perf_counters = + (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 7) & 0xf; + ivhd_11->iommu_attributes.perf_counter_banks = + (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 12) & 0x3f; + ivhd_11->iommu_attributes.msi_num_ppr = + (pci_read_config32(iommu_dev, ivhd_11->capability_offset + 0x10) >> 27) & 0x1f; - /* Describe SB IOAPIC */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0xd7; /* Data */ - p[4] = apicid_sb800; /* IOAPIC ID */ - p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ - p[6] = 0x0; /* Southbridge bus */ - p[7] = 0x1; /* Variety */ - current += 8; + if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_SUPPORT) { + ivhd_11->efr_reg_image_low = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x30); + ivhd_11->efr_reg_image_high = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x34); + } - return current; + current += sizeof(acpi_ivrs_ivhd11_t); + + /* Now repeat all the device entries from type 10h */ + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), + 0, &ivhd_11->length); + + add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, &current, &ivhd_11->length); + + current = ivhd_describe_hpet(current, &ivhd_11->length); + + current_backup = current; + + current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); + + ivhd_11->length += (current - current_backup); + + return current; } static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) { - uint8_t *p; acpi_ivrs_t *ivrs_agesa; + unsigned long current_backup; - struct device *nb_dev = pcidev_on_root(0x0, 0); + struct device *nb_dev = pcidev_on_root(0, 0); if (!nb_dev) { - printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); return (unsigned long)ivrs; } + struct device *iommu_dev = pcidev_on_root(0, 2); - /* obtain IOMMU base address */ + if (!iommu_dev) { + printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); + + return (unsigned long)ivrs; + } + ivrs_agesa = agesawrapper_getlateinitptr(PICK_IVRS); if (ivrs_agesa != NULL) { - ivrs->iv_info = 0x0; - /* Maximum supported virtual address size */ - ivrs->iv_info |= (0x40 << 15); - /* Maximum supported physical address size */ - ivrs->iv_info |= (0x30 << 8); - /* Guest virtual address width */ - ivrs->iv_info |= (0x2 << 5); - - ivrs->ivhd.type = 0x10; - ivrs->ivhd.flags = 0x0e; - /* Enable ATS support */ - ivrs->ivhd.flags |= 0x10; + ivrs->iv_info = ivrs_agesa->iv_info; + ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; + ivrs->ivhd.flags = ivrs_agesa->ivhd.flags; ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); /* BDF <bus>:00.2 */ - ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); - /* Capability block 0x40 (type 0xf, "Secure device") */ + ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); + /* PCI Capability block 0x40 (type 0xf, "Secure device") */ ivrs->ivhd.capability_offset = 0x40; ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; - ivrs->ivhd.pci_segment_group = 0x0; - ivrs->ivhd.iommu_info = 0x0; - ivrs->ivhd.iommu_info |= (0x13 << 8); - /* use only performance counters related bits: - * PNCounters[16:13] and - * PNBanks[22:17], - * otherwise 0 */ - ivrs->ivhd.iommu_feature_info = - ivrs_agesa->ivhd.iommu_feature_info & 0x7fe000; + ivrs->ivhd.pci_segment_group = 0x0000; + ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info; + ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info; + /* Enable EFR if supported */ + if (pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset) & EFR_SUPPORT) + ivrs->iv_info |= IVINFO_EFR_SUPPORTED; } else { printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); return (unsigned long)ivrs; } - /* Describe HPET */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0xd7; /* Data */ - p[4] = 0x0; /* HPET number */ - p[5] = 0x14 << 3; /* HPET device */ - p[6] = nb_dev->bus->secondary; /* HPET bus */ - p[7] = 0x2; /* Variety */ - ivrs->ivhd.length += 8; - current += 8; + /* + * Add all possible PCI devices on bus 0 that can generate transactions + * processed by IOMMU. Start with device 00:01.0 since IOMMU does not + * translate transactions generated by itself. + */ + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), + 0, &ivrs->ivhd.length); /* Describe PCI devices */ - int8_t root_level = -1; - add_ivrs_device_entries(NULL, all_devices, 0, -1, &root_level, &current, + add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, &current, &ivrs->ivhd.length); - /* Describe IOAPICs */ - unsigned long prev_current = current; - current = acpi_fill_ivrs_ioapic(ivrs, current); - ivrs->ivhd.length += (current - prev_current); + /* Describe HPET */ + current = ivhd_describe_hpet(current, &ivrs->ivhd.length); - return current; + current_backup = current; + + /* Describe IOAPICs */ + current = acpi_fill_ivrs_ioapic(ivrs, current); + /* Add IOAPIC entries size to currently assembled IVHD */ + ivrs->ivhd.length += (current - current_backup); + + /* If EFR is not supported, IVHD type 11h is reserved */ + if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) + return current; + + return acpi_fill_ivrs11(current, ivrs_agesa); } static void northbridge_fill_ssdt_generator(struct device *device) -- To view, visit https://review.coreboot.org/c/coreboot/+/40042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a2c24b67adfa8ebd718caeb5eec88687dcbcc9d Gerrit-Change-Number: 40042 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: sb/lynxpoint: Use macros instead of hard-coded IDs
by Felix Singer (Code Review) 07 Apr '20

07 Apr '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36706 ) Change subject: sb/lynxpoint: Use macros instead of hard-coded IDs ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/36706/6/src/include/device/pci_ids… File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/36706/6/src/include/device/pci_ids… PS6, Line 2750: #define PCI_DEVICE_ID_INTEL_LPT_LP_LPC_VALUE 0x9c47 > The renaming is not mentioned in the commit message. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/36706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d0f7122e461b78526692b78f79edcafafd3286 Gerrit-Change-Number: 36706 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Apr 2020 08:42:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sb/lynxpoint: Use macros instead of hard-coded IDs
by Felix Singer (Code Review) 07 Apr '20

07 Apr '20

Hello build bot (Jenkins), Nico Huber, Martin Roth, Paul Menzel, Angel Pons, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36706 to look at the new patch set (#7). Change subject: sb/lynxpoint: Use macros instead of hard-coded IDs ...................................................................... sb/lynxpoint: Use macros instead of hard-coded IDs This patch replaces hard-coded PCI IDs with macros from pci_ids.h. To be consistent with the naming scheme of other PCI device classes, this commit introduces the "LPC" extension for LPC devices. Used documents: - 328904-003 - 329003-003 Change-Id: Ib7d0f7122e461b78526692b78f79edcafafd3286 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/include/device/pci_ids.h M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 8 files changed, 143 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/36706/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/36706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d0f7122e461b78526692b78f79edcafafd3286 Gerrit-Change-Number: 36706 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: sb/lynxpoint: Use macros instead of hard-coded IDs
by Paul Menzel (Code Review) 07 Apr '20

07 Apr '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36706 ) Change subject: sb/lynxpoint: Use macros instead of hard-coded IDs ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/36706/6/src/include/device/pci_ids… File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/36706/6/src/include/device/pci_ids… PS6, Line 2750: #define PCI_DEVICE_ID_INTEL_LPT_LP_LPC_VALUE 0x9c47 The renaming is not mentioned in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/36706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d0f7122e461b78526692b78f79edcafafd3286 Gerrit-Change-Number: 36706 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Apr 2020 08:25:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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