coreboot-gerrit April 2020

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Change in coreboot[master]: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
by Andrey Petrov (Code Review) 01 Apr '20

01 Apr '20

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39425 ) Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver ...................................................................... Patch Set 15: thanks this looks good. I will try to re-run it on HW asap -- To view, visit https://review.coreboot.org/c/coreboot/+/39425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Gerrit-Change-Number: 39425 Gerrit-PatchSet: 15 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Apr 2020 07:24:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA
by Michał Żygowski (Code Review) 01 Apr '20

01 Apr '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39970 ) Change subject: mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA ...................................................................... mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA Certain PCIe endpoints cause an exception inside AmdInitMid when PCIe ClockPM is enabled in AGESA PCIe initialization structures. Disable it to allow platform to boot with such devices. coreboot driver enables the ClockPM correctly on such devices anyway. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I7fb13f915861c26cf773960abb12a3a1c0211cdc --- M src/mainboard/pcengines/apu2/OemCustomize.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/39970/1 diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index e47a2c8..8b6cd03 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -35,7 +35,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_PORT3_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { @@ -47,7 +47,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -59,7 +59,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -71,7 +71,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { @@ -83,7 +83,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_GFX_RESET_ID, - ClkPmSupportEnabled) + 0) } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/39970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fb13f915861c26cf773960abb12a3a1c0211cdc Gerrit-Change-Number: 39970 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs
by Matt DeVillier (Code Review) 01 Apr '20

01 Apr '20

Hello build bot (Jenkins), Paul Menzel, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/24989 to look at the new patch set (#4). Change subject: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs ...................................................................... mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs The jack detect GPIOs are initialized as dual edge-triggered GPIs, and Linux doesn't care if they are set to ActiveLow, ActiveHigh, or ActiveBoth -- a single interrupt is detected on jack insertion or removal. The Windows drivers on the other hand, will not function unless the codec and LPE ACPI interrupts entries are set as in the Intel Cherrytrail Tianocore platform reference code. So adjust the ACPI interrupt triggers to make Windows happy, since Linux doesn't care either way. Test: boot Linux and Windows 10 on google/edgar, observe functional audio output for both built-in speakers and headphones. Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/24989/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/24989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Gerrit-Change-Number: 24989 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/vboot: Provide stub functions for TPM in bootblock
by Werner Zeh (Code Review) 01 Apr '20

01 Apr '20

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39971 ) Change subject: security/vboot: Provide stub functions for TPM in bootblock ...................................................................... security/vboot: Provide stub functions for TPM in bootblock With commit c79e96b4eb310db9d44e36e2dff072c01469c380 (security/vboot: Decouple measured boot from verified boot) the measured boot logic was decoupled from VBOOT and the TSS layer of the TPM driver was added to the bootblock. If now TPM_MEASURED_BOOT and VBOOT are selected at the same time, the TPM functions called by the TSS layer are missing during link time of the bootblock as at least the LPC TPM driver is not enabled for bootblcok. On the other side enabling the LPC TPM driver in bootblock leads to an increased bootblock which on Apollo Lake does not fit anymore. Since the intention of the mentioned patch was to decouple the both features MEASURED_BOOT and VBOOT while still keep it possible to have both enabled at the same time the missing functions need to be available in bootblock though they are not needed (just to be able to link). For this reason this patch provides a new Kconfig switch called 'TPM_IN_BOOTBLOCK' which, when set, will enable the full TPM functionality in bootblock. As it is disabled per default just empty stubs will be compiled for bootblock. If a platform needs the full TPM driver in bootblock it can simply select 'TPM_IN_BOOTBLOCK'. Change-Id: I888928a6577f4b920b5ee8b65daf23aa46e3aff8 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/crb/tis.c M src/drivers/i2c/tpm/tis.c M src/drivers/i2c/tpm/tis_atmel.c M src/drivers/pc80/tpm/Makefile.inc M src/drivers/pc80/tpm/tis.c M src/drivers/spi/tpm/tis.c M src/security/tpm/Kconfig 7 files changed, 77 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/39971/1 diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index b1fbad0..ef10002 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -44,6 +44,10 @@ int tis_open(void) { + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return -1; + } + if (tpm_is_open) { printk(BIOS_ERR, "%s called twice.\n", __func__); return -1; @@ -62,6 +66,10 @@ int tis_close(void) { + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return -1; + } + if (tpm_is_open) { /* @@ -78,6 +86,10 @@ { struct tpm2_info info; + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return -1; + } + // Wake TPM up (if necessary) if (tpm2_init() != 0) return -1; @@ -93,6 +105,10 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, size_t *rbuf_len) { + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return -1; + } + int len = tpm2_process_command(sendbuf, sbuf_size, recvbuf, *rbuf_len); if (len == 0) diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index 8b07bb7..b7b9009 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -35,6 +35,10 @@ { int rc; + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return -1; + } + if (chip.is_open) { printk(BIOS_DEBUG, "tis_open() called twice.\n"); return -1; @@ -53,6 +57,10 @@ int tis_close(void) { + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return -1; + } + if (chip.is_open) { tpm_vendor_cleanup(&chip); chip.is_open = 0; @@ -63,6 +71,10 @@ int tis_init(void) { + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return -1; + } + return tpm_vendor_probe(CONFIG_DRIVER_TPM_I2C_BUS, CONFIG_DRIVER_TPM_I2C_ADDR); } @@ -133,6 +145,10 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, size_t *rbuf_len) { + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return -1; + } + ASSERT(sbuf_size >= 10); /* Display the TPM command */ diff --git a/src/drivers/i2c/tpm/tis_atmel.c b/src/drivers/i2c/tpm/tis_atmel.c index 74b4830..497e4fe 100644 --- a/src/drivers/i2c/tpm/tis_atmel.c +++ b/src/drivers/i2c/tpm/tis_atmel.c @@ -59,6 +59,10 @@ int status; struct stopwatch sw; + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return -1; + } + ASSERT(sbuf_size >= 10); if (CONFIG(DRIVER_TPM_DISPLAY_TIS_BYTES)) { /* Display the TPM command */ diff --git a/src/drivers/pc80/tpm/Makefile.inc b/src/drivers/pc80/tpm/Makefile.inc index 0de1b76..cba3e43 100644 --- a/src/drivers/pc80/tpm/Makefile.inc +++ b/src/drivers/pc80/tpm/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-$(CONFIG_LPC_TPM) += tis.c verstage-$(CONFIG_LPC_TPM) += tis.c romstage-$(CONFIG_LPC_TPM) += tis.c ramstage-$(CONFIG_LPC_TPM) += tis.c diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index a35ef83..000abe1 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -635,6 +635,10 @@ */ int tis_init(void) { + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return TPM_DRIVER_ERR; + } + if (tis_probe()) return TPM_DRIVER_ERR; return 0; @@ -652,6 +656,10 @@ { u8 locality = 0; /* we use locality zero for everything */ + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return TPM_DRIVER_ERR; + } + if (tis_close()) return TPM_DRIVER_ERR; @@ -684,6 +692,11 @@ int tis_close(void) { u8 locality = 0; + + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return TPM_DRIVER_ERR; + } + if (tis_has_access(locality)) { tis_drop_access(locality); if (tis_wait_dropped_access(locality)) { @@ -711,6 +724,10 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t send_size, uint8_t *recvbuf, size_t *recv_len) { + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return TPM_DRIVER_ERR; + } + if (tis_senddata(sendbuf, send_size)) { printf("%s:%d failed sending data to TPM\n", __FILE__, __LINE__); diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c index 6230751..2f2fe4a 100644 --- a/src/drivers/spi/tpm/tis.c +++ b/src/drivers/spi/tpm/tis.c @@ -33,6 +33,9 @@ int tis_open(void) { + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return -1; + } if (tpm_is_open) { printk(BIOS_ERR, "tis_open() called twice.\n"); return -1; @@ -42,6 +45,10 @@ int tis_close(void) { + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return -1; + } + if (tpm_is_open) { /* @@ -59,6 +66,10 @@ struct spi_slave spi; struct tpm2_info info; + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return -1; + } + if (spi_setup_slave(CONFIG_DRIVER_TPM_SPI_BUS, CONFIG_DRIVER_TPM_SPI_CHIP, &spi)) { printk(BIOS_ERR, "Failed to setup TPM SPI slave\n"); @@ -82,6 +93,10 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, size_t *rbuf_len) { + if (ENV_BOOTBLOCK && !CONFIG(TPM_IN_BOOTBLOCK)) { + return -1; + } + int len = tpm2_process_command(sendbuf, sbuf_size, recvbuf, *rbuf_len); if (len == 0) diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index d8652b2..5c6f1aa 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -117,4 +117,12 @@ Runtime data whitelist of cbfs filenames. Needs to be a comma separated list +config TPM_IN_BOOTBLOCK + bool "Enable TPM driver in bootblock" + default n + depends on TPM_MEASURED_BOOT + help + Enable the TPM driver in bootblock. Select this option if the bootblock + has enough space to include the TPM driver. + endmenu # Trusted Platform Module (tpm) -- To view, visit https://review.coreboot.org/c/coreboot/+/39971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I888928a6577f4b920b5ee8b65daf23aa46e3aff8 Gerrit-Change-Number: 39971 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs
by Matt DeVillier (Code Review) 01 Apr '20

01 Apr '20

Hello build bot (Jenkins), Paul Menzel, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/24989 to look at the new patch set (#3). Change subject: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs ...................................................................... mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs The jack detect GPIOs are initialized as dual edge-triggered GPIs, and Linux doesn't care if they are set to ActiveLow, ActiveHigh, or ActiveBoth -- a single interrupt is detected on jack insertion or removal. The Windows drivers on the other hand, will not function unless the codec and LPE ACPI interrupts entries are set as in the Intel Cherrytrail Tianocore platform reference code. So adjust the ACPI interrupt triggers to make Windows happy, since Linux doesn't care either way. Test: boot Linux and Windows 10 on google/edgar, observe functional audio output for both built-in speakers and headphones. Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/24989/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/24989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Gerrit-Change-Number: 24989 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: google/cyan: fix ACPI interrupt triggering for audio codecs
by Matt DeVillier (Code Review) 01 Apr '20

01 Apr '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/24989 ) Change subject: google/cyan: fix ACPI interrupt triggering for audio codecs ...................................................................... Patch Set 2: > Patch Set 2: > > Yes, the question is why it is fixed. Is this because there's an inversion being done somewhere where it shouldn't? > > We should dump the the gpio config for the one in question and compare w/ the coreboot settings vs what the kerne's pinmux might be doing. every cyan variant has the jack detect GPIO defined as 95, PCIE_CLKREQ3B/AUDIO_CODEC_IRQ, and every one sets it as a GPI, edge triggered both. The kernel cherrytrail pinmux driver actually skips over 95 since it's only listed as having a single/primary function (PCIE_CLKREQ3B) Given that, 'ActiveBoth' would seem to be the correct setting for both the codec and LPE device. I'll test and adjust the patch if that works here -- To view, visit https://review.coreboot.org/c/coreboot/+/24989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Gerrit-Change-Number: 24989 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 01:53:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
by Johnny Lin (Code Review) 01 Apr '20

01 Apr '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39895 ) Change subject: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time ...................................................................... Patch Set 6: (20 comments) https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… File src/mainboard/ocp/tiogapass/skxsp_tp_iio.h: https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 23: Socket0_Iou0 = 0, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 23: Socket0_Iou0 = 0, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 24: Socket0_Iou1, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 24: Socket0_Iou1, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 25: Socket0_Iou2, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 25: Socket0_Iou2, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 26: Socket0_Mcp0, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 26: Socket0_Mcp0, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 27: Socket0_Mcp1, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 27: Socket0_Mcp1, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 28: Socket1_Iou0, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 28: Socket1_Iou0, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 29: Socket1_Iou1, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 29: Socket1_Iou1, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 30: Socket1_Iou2, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 30: Socket1_Iou2, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 31: Socket1_Mcp0, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 31: Socket1_Mcp0, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 32: Socket1_Mcp1 > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 32: Socket1_Mcp1 > code indent should use tabs where possible Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Gerrit-Change-Number: 39895 Gerrit-PatchSet: 6 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 01:05:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
by Johnny Lin (Code Review) 01 Apr '20

01 Apr '20

Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39895 to look at the new patch set (#6). Change subject: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time ...................................................................... mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time Update UPD IIO bifurcation at run-time accroding to different hardware configurations such as different Riser cards. With the engineering build FSP, it can only configure IIO for one socket so my local test need to remove all socket1 elements from tp_iio_bifur_table. Tested=OCP Tioga Pass can see socket0 IIO being updated with an engineering build FSP. Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/tiogapass/romstage.c M src/mainboard/ocp/tiogapass/skxsp_tp_iio.h 2 files changed, 30 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39895/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/39895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Gerrit-Change-Number: 39895 Gerrit-PatchSet: 6 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
by Johnny Lin (Code Review) 01 Apr '20

01 Apr '20

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Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572
by Benjamin Doron (Code Review) 01 Apr '20

01 Apr '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mainboard: Add Acer ES1-572 ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@31 PS5, Line 31: - Battery. I have it somewhere. > yes but no. […] ACPI code needs to be added to communicate with the EC. Check the vendor's DSDT https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… PS5, Line 266: device pci 1f.5 off end # PCH SPI > breaks rom console, too Off-topic, but presently, lpc_set_lock_enable in the common code locks BIOS write-enable=1. Is there any reason why this is the case, or should we fix it (preferably with a check against a lockdown related config, CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION or CB:32704)? -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Apr 2020 00:12:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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coreboot-gerrit April 2020