April 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: security/tpm: Fix compile-time elimination for SEPARATE_VERSTAGE
by Julius Werner (Code Review) April 1, 2020

April 1, 2020

Hello Philipp Deppenwiese, Bill XIE, Werner Zeh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39993 to review the following change. Change subject: security/tpm: Fix compile-time elimination for SEPARATE_VERSTAGE ...................................................................... security/tpm: Fix compile-time elimination for SEPARATE_VERSTAGE CB:35077 pulled TPM measurement code into the bootblock, with the catch that we'll only cache PCR extensions and not actually write them to the TPM until it gets initialized in a later stage. The goal of this was to keep the heavy TPM driver code out of the size-constrained bootblock. Unfortunately, a small mistake in the tspi_tpm_is_setup() function prevents the compiler from eliminating references to the TPM driver code in the bootblock on platforms with CONFIG_VBOOT and CONFIG_SEPARATE_VERSTAGE. In those cases vboot_logic_executed() is known at compile-time to be 0, but that still makes the final expression `return 0 || tpm_is_setup;`. We know that tpm_is_setup can never be set to 1 in the bootblock, but the compiler doesn't. This patch rewrites the logic slightly to achieve the same effect in a way that the compiler can follow (because we only really need to check tpm_is_setup in the stage that actually runs the vboot code). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Idc25acf1e6c02d929639e83d529cc14af80e0870 --- M src/security/tpm/tspi/tspi.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/39993/1 diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 4f0cc97..4b32657 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -104,8 +104,11 @@ static int tpm_is_setup; static inline int tspi_tpm_is_setup(void) { - if (CONFIG(VBOOT)) - return vboot_logic_executed() || tpm_is_setup; + if (CONFIG(VBOOT)) { + if (verification_should_run()) + return tpm_is_setup; + return vboot_logic_executed(); + } if (ENV_RAMSTAGE) return tpm_is_setup; -- To view, visit https://review.coreboot.org/c/coreboot/+/39993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc25acf1e6c02d929639e83d529cc14af80e0870 Gerrit-Change-Number: 39993 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Michael Niewöhner (Code Review) April 1, 2020

April 1, 2020

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Patch Set 3: I tried to find out more about the PSI3/4 states. Some facts: - "optional for server" in IMVP7 (doc#397113) simply means there are VRs for the server segment which don't support PS3 or PS4 - PS4 is only available on SoCs supporting C10 - Intel doc#334661-006 says PS4 is "shut the VR nearly completely off" - Intel doc#334661-006 says that C-States should be limited to C9 when the SoC supports C10 but the platform (well, I guess they mean the whole machine but basicly the VR itself) does not support PS4 - There are VRs where the DS says "compliant with IMVP8 PS4", e.g. MP2949A - PS3 means only one phase is on in dynamic mode - PS4 means all PWM outputs are tristated / all phases are disabled. The VR is still enabled/alive to be able to respond with nearly no delay - The PS4 command MUST be acknowledged by the VR according to some Intel doc I forgot to note the id for :/ Long story short: if we have the datasheet for the VR of the machine, we can simply check if it supports PSI3, PSI4, both, or none. If we don't have a datasheet, we have a problem. I could not find out, yet, what would happen when the SoC tries to request PSI3/4 but the VR does not acknowlege it. In case some error flag gets set, we could simply test it by letting the machine go to C10 and check that flag. -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 21:24:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Michael Niewöhner (Code Review) April 1, 2020

April 1, 2020

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG@18 PS3, Line 18: Boards that have a domain_vr_config and set their specific settings are > I've found that a lot of information is available in the vendor's advanced settings. […] Those settings are not in the bios/uefi on any of the firmwares I have checked. That's simply too low-level I assume -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 21:14:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Benjamin Doron (Code Review) April 1, 2020

April 1, 2020

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 20:37:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Benjamin Doron (Code Review) April 1, 2020

April 1, 2020

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG@18 PS3, Line 18: Boards that have a domain_vr_config and set their specific settings are > I'd like to have a way to dump the vendor information from the vendor image and/or read it by intelt […] I've found that a lot of information is available in the vendor's advanced settings. For me, they were not visible by default (laptops seem to be particularly guilty in this regard) and I de-suppressed and enabled an option named "i-Page" (Intel page, perhaps) in the IFR (by hex) of the vendor's Setup utility UEFI module. -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 20:34:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs
by Angel Pons (Code Review) April 1, 2020

April 1, 2020

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/24989 ) Change subject: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/24989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Gerrit-Change-Number: 24989 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 20:18:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Christian Walter (Code Review) April 1, 2020

April 1, 2020

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Patch Set 3: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/39980/3/src/soc/intel/skylake/vr_c… File src/soc/intel/skylake/vr_config.c: https://review.coreboot.org/c/coreboot/+/39980/3/src/soc/intel/skylake/vr_c… PS3, Line 24: /* Default values for domain configuration. PSI3 and PSI4 are disabled. */ Update comment? -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 19:48:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/psp: make BootDone command conditional
by Felix Held (Code Review) April 1, 2020

April 1, 2020

Hello Marshall Dawson, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40017 to review the following change. Change subject: soc/amd/common/psp: make BootDone command conditional ...................................................................... soc/amd/common/psp: make BootDone command conditional The common PSP code automatically sends the command, however for fam17h FSP also sends it in response to a Notify. The 2nd instance of the command generates a timeout error. Change-Id: I819ab0b80d2a3cf6cd24f3e7170cae779dcc7cef Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020369 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/psp/psp.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40017/1 diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index b48ff30..3aa3b86 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -180,10 +180,12 @@ return cmd_status; } +#if CONFIG(SOC_AMD_STONEYRIDGE) /* * Notify the PSP that the system is completing the boot process. Upon * receiving this command, the PSP will only honor commands where the buffer - * is in SMM space. + * is in SMM space. In FSP-based families, this is done by the FSP code and + * calling it a second time results in a hang. */ static void psp_notify_boot_done(void *unused) { @@ -201,6 +203,7 @@ /* buffer's status shouldn't change but report it if it does */ print_cmd_status(cmd_status, &buffer); } +#endif /* Notify PSP the system is going to a sleep state. */ void psp_notify_sx_info(u8 sleep_type) @@ -276,5 +279,8 @@ return cmd_status; } +#if CONFIG(SOC_AMD_STONEYRIDGE) +/* only run psp_notify_boot_done on non-FSP families */ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, psp_notify_boot_done, NULL); +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/40017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819ab0b80d2a3cf6cd24f3e7170cae779dcc7cef Gerrit-Change-Number: 40017 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mb/google/volteer: Add camera ACPI configuration
by Daniel Kang (Code Review) April 1, 2020

April 1, 2020

Daniel Kang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39684 ) Change subject: src/mb/google/volteer: Add camera ACPI configuration ...................................................................... src/mb/google/volteer: Add camera ACPI configuration Add camera ACPI configuration for Ripto/Volteer BUG=None BRANCH=None TEST=Build and boot Ripto or Volteer. Start camera app and able to capture images. Signed-off-by: Daniel Kang <daniel.h.kang(a)intel.com> Change-Id: I2b47ccd989192273a29f09bf097e12e357929334 --- A src/mainboard/google/volteer/acpi/mipi_camera.asl M src/mainboard/google/volteer/dsdt.asl 2 files changed, 616 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/39684/1 diff --git a/src/mainboard/google/volteer/acpi/mipi_camera.asl b/src/mainboard/google/volteer/acpi/mipi_camera.asl new file mode 100644 index 0000000..1b12360 --- /dev/null +++ b/src/mainboard/google/volteer/acpi/mipi_camera.asl @@ -0,0 +1,613 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 5 + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 1 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM0, + Zero, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C2.CAM1, + Zero, + Zero + } + } + } + }) +} + +Scope (\_SB.PCI0.I2C3) +{ + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(3,1) /* Clock 3, 19.2MHz */ + + /* Pull RST low */ +#if CONFIG_BOARD_GOOGLE_VOLTEER + CTXS(GPP_F15) +#else + CTXS(GPP_D4) +#endif + + /* Pull PWREN high */ + STXS(GPP_H20) + Sleep(2) /* reset pulse width */ + + /* Pull RST high */ +#if CONFIG_BOARD_GOOGLE_VOLTEER + STXS(GPP_F15) +#else + STXS(GPP_D4) +#endif + Sleep(1) /* t2 */ + + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(3) /* Clock 3 */ + + /* Pull RST low */ +#if CONFIG_BOARD_GOOGLE_VOLTEER + CTXS(GPP_F15) +#else + CTXS(GPP_D4) +#endif + + /* Pull PWREN low */ + CTXS(GPP_H20) + + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI8856") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 8856 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x02) + { + 0x15752A00, + 0xABA9500 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } + + Device (VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + Name (_UID, 0x03) /* _UID: Unique ID */ + Name (_DDN, "GT9769 VCM") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM0 + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "compatible", + "giantec,gt9769-vcm" + } + } + }) + } + Device (NVM0) + { + Name (_HID, "PRP0001") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_DDN, "GT9769 EEPROM") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBusV2 (0x0058, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + CAM0 + }) + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + RCPR + }) + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + RCPR + }) + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x05) + { + Package (0x02) + { + "size", + 0x2800 + }, + Package (0x02) + { + "pagesize", + One + }, + Package (0x02) + { + "read-only", + One + }, + Package (0x02) + { + "address-width", + 0x0D + }, + Package (0x02) + { + "compatible", + "giantec,gt9769-eeprom" + } + } + }) + } +} + +Scope (\_SB.PCI0.I2C2) +{ + PowerResource (FCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(2,1) /* Clock 2, 19.2MHz */ + + /* Pull RST low */ + CTXS(GPP_D4) + + /* Pull SNRPWR_EN high */ + STXS(GPP_D18) + + /* Pull PWREN high */ + STXS(GPP_D17) + Sleep(10) /* t9 */ + + /* Pull RST high */ + STXS(GPP_D4) + Sleep(1) /* t2 */ + + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(2) /* Clock 2 */ + + /* Pull RST low */ + CTXS(GPP_D4) + + /* Pull PWREN low */ + CTXS(GPP_D17) + + /* Pull SNRPWR_EN low */ + CTXS(GPP_D18) + + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device (CAM1) + { + Name (_HID, "OVTI2740") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 2740 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C2", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0xABA9500 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 4533f89..d259926 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -47,4 +47,7 @@ } #include <southbridge/intel/common/acpi/sleepstates.asl> + /* Camera */ + #include <soc/intel/tigerlake/acpi/ipu.asl> + #include "acpi/mipi_camera.asl" } -- To view, visit https://review.coreboot.org/c/coreboot/+/39684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b47ccd989192273a29f09bf097e12e357929334 Gerrit-Change-Number: 39684 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Remove Jasper Lake SoC references
by 9elements QA (Code Review) April 1, 2020

April 1, 2020

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39774 ) Change subject: soc/intel/tigerlake: Remove Jasper Lake SoC references ...................................................................... Patch Set 14: Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1981 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1980 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1979 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/39774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727 Gerrit-Change-Number: 39774 Gerrit-PatchSet: 14 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Justin TerAvest <teravest(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 01 Apr 2020 19:23:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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