coreboot-gerrit April 2020

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Change in coreboot[master]: soc/intel/tigerlake: Remove Jasper Lake SoC references
by Aamir Bohra (Code Review) 01 Apr '20

01 Apr '20

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Change in coreboot[master]: soc/intel/tigerlake: Remove Jasper Lake SoC references
by Aamir Bohra (Code Review) 01 Apr '20

01 Apr '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39774 ) Change subject: soc/intel/tigerlake: Remove Jasper Lake SoC references ...................................................................... Patch Set 13: (7 comments) https://review.coreboot.org/c/coreboot/+/39774/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39774/5//COMMIT_MSG@7 PS5, Line 7: soc/intel/{tigerlake, jasperlake}: Split Jasper Lake SoC code from Tiger Lake > soc/intel: Split Jasper Lake SoC from Tiger Lake SoC code Done. Commit message reworded. https://review.coreboot.org/c/coreboot/+/39774/5//COMMIT_MSG@14 PS5, Line 14: This > lowercase? Done https://review.coreboot.org/c/coreboot/+/39774/5//COMMIT_MSG@15 PS5, Line 15: code(tgl > Please add as space before (. Done https://review.coreboot.org/c/coreboot/+/39774/4/src/soc/intel/jasperlake/i… File src/soc/intel/jasperlake/include/soc/romstage.h: https://review.coreboot.org/c/coreboot/+/39774/4/src/soc/intel/jasperlake/i… PS4, Line 20: void mainboard_memory_init_params(FSPM_UPD *mupd); > need consistent spacing around '*' (ctx:WxV) Done https://review.coreboot.org/c/coreboot/+/39774/2/src/soc/intel/jasperlake/i… File src/soc/intel/jasperlake/include/soc/romstage.h: https://review.coreboot.org/c/coreboot/+/39774/2/src/soc/intel/jasperlake/i… PS2, Line 20: void mainboard_memory_init_params(FSPM_UPD *mupd); > need consistent spacing around '*' (ctx:WxV) Done https://review.coreboot.org/c/coreboot/+/39774/6/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/pci_irqs.asl: PS6: > This should have shown as a rename of pci_irqs_tgl.asl. Shows it when I commit the changes locally: […] Done https://review.coreboot.org/c/coreboot/+/39774/7/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/pch.h: https://review.coreboot.org/c/coreboot/+/39774/7/src/soc/intel/tigerlake/in… PS7, Line 20: #define PCH_H 1 : #define PCH_LP 2 : #define PCH_UNKNOWN_SERIES 0xFF > Not required Furquan, removed it. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727 Gerrit-Change-Number: 39774 Gerrit-PatchSet: 13 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Justin TerAvest <teravest(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 01 Apr 2020 19:10:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Michael Niewöhner (Code Review) 01 Apr '20

01 Apr '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG@13 PS3, Line 13: > Mention that in 2015 there were problems in FSP? ACK https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG@18 PS3, Line 18: Boards that have a domain_vr_config and set their specific settings are I'd like to have a way to dump the vendor information from the vendor image and/or read it by inteltool. Nico tried to read the VR mailbox without success. I tried to check the MSR 0x601 but that is 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 18:12:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
by Aamir Bohra (Code Review) 01 Apr '20

01 Apr '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39825 ) Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ...................................................................... soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build. BUG=b:150217037 TEST=build dedede, jasperlake_rvp and volteer board Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/romstage.c M src/mainboard/google/dedede/variants/baseboard/memory.c M src/mainboard/intel/jasperlake_rvp/dsdt.asl M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc 8 files changed, 13 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39825/1 diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 53423b8..98ef6e4 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -18,7 +18,7 @@ 0x20110725 /* OEM revision */ ) { - #include <soc/intel/tigerlake/acpi/platform.asl> + #include <soc/intel/jasperlake/acpi/platform.asl> /* global NVS and variables */ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> @@ -30,7 +30,7 @@ Device (PCI0) { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/jasperlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 9c220d4..f95e7aa 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -6,7 +6,7 @@ */ #include <baseboard/variants.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <soc/romstage.h> void mainboard_memory_init_params(FSPM_UPD *memupd) diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c index ff8a4ec..08c3bde 100644 --- a/src/mainboard/google/dedede/variants/baseboard/memory.c +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -8,7 +8,7 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> #include <gpio.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <soc/romstage.h> static const struct mb_cfg baseboard_memcfg_cfg = { diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index c996717..ed59af6 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -25,7 +25,7 @@ 0x20110725 /* OEM revision */ ) { - #include <soc/intel/tigerlake/acpi/platform.asl> + #include <soc/intel/jasperlake/acpi/platform.asl> /* global NVS and variables */ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> @@ -37,7 +37,7 @@ Device (PCI0) { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/jasperlake/acpi/southbridge.asl> } } diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 01d7294..844a954 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -1,9 +1,9 @@ -config SOC_INTEL_JASPERLAKE_COPY +config SOC_INTEL_JASPERLAKE bool help Intel Jasperlake support -if SOC_INTEL_JASPERLAKE_COPY +if SOC_INTEL_JASPERLAKE config CPU_SPECIFIC_OPTIONS def_bool y @@ -192,7 +192,7 @@ depends on FSP_USE_REPO default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" -config SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT +config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT int "Debug Consent for JSL" # USB DBC is more common for developers so make this default to 3 if # SOC_INTEL_DEBUG_CONSENT=y diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 29db4f3..4a65adc 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE_COPY),y) +ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 63bd881..e71586d 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -1,22 +1,9 @@ -config SOC_INTEL_TIGERLAKE_BASE - bool - config SOC_INTEL_TIGERLAKE bool - select SOC_INTEL_TIGERLAKE_BASE - #TODO - Enable INTEL_CAR_NEM_ENHANCED - select INTEL_CAR_NEM help Intel Tigerlake support -config SOC_INTEL_JASPERLAKE - bool - select SOC_INTEL_TIGERLAKE_BASE - select INTEL_CAR_NEM - help - Intel Jasperlake support - -if SOC_INTEL_TIGERLAKE_BASE +if SOC_INTEL_TIGERLAKE config CPU_SPECIFIC_OPTIONS def_bool y @@ -36,6 +23,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index e7169cf..12d59b1 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE),y) +ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode -- To view, visit https://review.coreboot.org/c/coreboot/+/39825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Gerrit-Change-Number: 39825 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Remove Jasper Lake SoC references
by Furquan Shaikh (Code Review) 01 Apr '20

01 Apr '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39774 ) Change subject: soc/intel/tigerlake: Remove Jasper Lake SoC references ...................................................................... Patch Set 13: Aamir -- can you please mark all comments as resolved? -- To view, visit https://review.coreboot.org/c/coreboot/+/39774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727 Gerrit-Change-Number: 39774 Gerrit-PatchSet: 13 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Justin TerAvest <teravest(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 01 Apr 2020 16:39:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs
by Aaron Durbin (Code Review) 01 Apr '20

01 Apr '20

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/24989 ) Change subject: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/24989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Gerrit-Change-Number: 24989 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 15:20:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs
by Matt DeVillier (Code Review) 01 Apr '20

01 Apr '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/24989 ) Change subject: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs ...................................................................... Patch Set 5: (2 comments) > Patch Set 4: > > Nice analysis. Can you add that to the commit message too? I've updated it with a summarized version: as usual, Linux doesn't care and Windows is very picky for no good reason https://review.coreboot.org/c/coreboot/+/24989/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/24989/4//COMMIT_MSG@16 PS4, Line 16: Cherrytrail > Cherry Trail Done https://review.coreboot.org/c/coreboot/+/24989/4//COMMIT_MSG@21 PS4, Line 21: Linux > What version? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/24989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Gerrit-Change-Number: 24989 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 15:11:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs
by Matt DeVillier (Code Review) 01 Apr '20

01 Apr '20

Hello build bot (Jenkins), Paul Menzel, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/24989 to look at the new patch set (#5). Change subject: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs ...................................................................... mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs The jack detect GPIOs are initialized as dual edge-triggered GPIs, and Linux doesn't care if they are set to ActiveLow, ActiveHigh, or ActiveBoth -- a single interrupt is detected on jack insertion or removal. The Windows drivers on the other hand, will not function unless the codec and LPE ACPI interrupts entries are set as in the Intel Cherry Trail Tianocore platform reference code. So adjust the ACPI interrupt triggers to make Windows happy, since Linux doesn't care either way. Test: boot Linux (GalliumOS 3.1) and Windows 10 on google/edgar, observe functional audio output for both built-in speakers and headphones. Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/24989/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/24989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Gerrit-Change-Number: 24989 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/pc80/rtc: Always load cmos.default to satisfy measured boot
by Bill XIE (Code Review) 01 Apr '20

01 Apr '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39906 ) Change subject: drivers/pc80/rtc: Always load cmos.default to satisfy measured boot ...................................................................... drivers/pc80/rtc: Always load cmos.default to satisfy measured boot cmos.default used to be loaded only when cmos is needed to be reset, but conditional loading of CBFS files may break measured boot if measurement is hooked on each loading. In order to resolve this, loadings should be made unconditional, but the use of loaded data remains conditional, so cmos.default should always be loaded (with cbfs_boot_map_with_leak() which is further hooked with measurement), but cmos resetting remains conditional. Change-Id: If6ea0d1cbaa7d96f7dea7e77b7548ca2b30efe9e Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/drivers/pc80/rtc/option.c 1 file changed, 7 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39906/1 diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index bb697df..5bf2fc9 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -239,7 +239,7 @@ return cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC); } -static void cmos_load_defaults(void) +void sanitize_cmos(void) { size_t length = 128; size_t i; @@ -250,14 +250,10 @@ if (!cmos_default) return; - u8 control_state = cmos_disable_rtc(); - for (i = 14; i < MIN(128, length); i++) - cmos_write_inner(cmos_default[i], i); - cmos_restore_rtc(control_state); -} - -void sanitize_cmos(void) -{ - if (cmos_error() || !cmos_lb_cks_valid() || CONFIG(STATIC_OPTION_TABLE)) - cmos_load_defaults(); + if (cmos_error() || !cmos_lb_cks_valid() || CONFIG(STATIC_OPTION_TABLE)) { + u8 control_state = cmos_disable_rtc(); + for (i = 14; i < MIN(128, length); i++) + cmos_write_inner(cmos_default[i], i); + cmos_restore_rtc(control_state); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6ea0d1cbaa7d96f7dea7e77b7548ca2b30efe9e Gerrit-Change-Number: 39906 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Remove myself from MAINTAINERS file
by Philipp Deppenwiese (Code Review) 01 Apr '20

01 Apr '20

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39897 ) Change subject: Remove myself from MAINTAINERS file ...................................................................... Remove myself from MAINTAINERS file I will pass my responsibilities to Christian Walter. I have hardly any time left for the coreboot project. Change-Id: Ia60e71c5cbd361486dbc924ad954db203e285a5a Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M MAINTAINERS 1 file changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/39897/1 diff --git a/MAINTAINERS b/MAINTAINERS index 3a31847..7ea4aa3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -223,7 +223,7 @@ F: src/mainboard/google/stout/ OPENCELLULAR MAINBOARDS -M: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> +M: Christian Walter <christian.walter(a)9elements.com> M: Patrick Rudolph <patrick.rudolph(a)9elements.com> S: Supported F: src/mainboard/opencellular/elgon/ @@ -455,7 +455,7 @@ F: util/inteltool/ INTELMETOOL -M: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> +M: Christian Walter <christian.walter(a)9elements.com> F: util/intelmetool/ ME_CLEANER @@ -535,7 +535,7 @@ F: payloads/external LINUXBOOT PAYLOAD INTEGRATION -M: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> +M: Christian Walter <christian.walter(a)9elements.com> M: Marcello Sylvester Bauer <info(a)marcellobauer.com> S: Supported F: payloads/external/LinuxBoot @@ -545,10 +545,9 @@ F: src/security/vboot/ TPM SUPPORT -M: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> +M: Christian Walter <christian.walter(a)9elements.com> S: Supported F: src/drivers/*/tpm/ -F: src/security/vboot/vboot_crtm.* F: src/security/tpm DOCKER @@ -608,11 +607,11 @@ # Backups: # Website -# Owners: Martin, Philipp +# Owners: Martin # Backups: Patrick, Stefan # Documentation Website -# Owners: Patrick, Philipp +# Owners: Patrick # Backups: CODE OF CONDUCT -- To view, visit https://review.coreboot.org/c/coreboot/+/39897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia60e71c5cbd361486dbc924ad954db203e285a5a Gerrit-Change-Number: 39897 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2020