Change in coreboot[master]: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build.
BUG=b:150217037 TEST=build dedede, jasperlake_rvp and volteer board
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/romstage.c M src/mainboard/google/dedede/variants/baseboard/memory.c M src/mainboard/intel/jasperlake_rvp/dsdt.asl M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc 8 files changed, 13 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39825/1
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 53423b8..98ef6e4 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -18,7 +18,7 @@ 0x20110725 /* OEM revision */ ) { - #include <soc/intel/tigerlake/acpi/platform.asl> + #include <soc/intel/jasperlake/acpi/platform.asl>
/* global NVS and variables */ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> @@ -30,7 +30,7 @@ Device (PCI0) { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/jasperlake/acpi/southbridge.asl> } }
diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 9c220d4..f95e7aa 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -6,7 +6,7 @@ */
#include <baseboard/variants.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *memupd) diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c index ff8a4ec..08c3bde 100644 --- a/src/mainboard/google/dedede/variants/baseboard/memory.c +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -8,7 +8,7 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> #include <gpio.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <soc/romstage.h>
static const struct mb_cfg baseboard_memcfg_cfg = { diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index c996717..ed59af6 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -25,7 +25,7 @@ 0x20110725 /* OEM revision */ ) { - #include <soc/intel/tigerlake/acpi/platform.asl> + #include <soc/intel/jasperlake/acpi/platform.asl>
/* global NVS and variables */ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> @@ -37,7 +37,7 @@ Device (PCI0) { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/jasperlake/acpi/southbridge.asl> } }
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 01d7294..844a954 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -1,9 +1,9 @@ -config SOC_INTEL_JASPERLAKE_COPY +config SOC_INTEL_JASPERLAKE bool help Intel Jasperlake support
-if SOC_INTEL_JASPERLAKE_COPY +if SOC_INTEL_JASPERLAKE
config CPU_SPECIFIC_OPTIONS def_bool y @@ -192,7 +192,7 @@ depends on FSP_USE_REPO default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd"
-config SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT +config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT int "Debug Consent for JSL" # USB DBC is more common for developers so make this default to 3 if # SOC_INTEL_DEBUG_CONSENT=y diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 29db4f3..4a65adc 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE_COPY),y) +ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE),y)
subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 63bd881..e71586d 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -1,22 +1,9 @@ -config SOC_INTEL_TIGERLAKE_BASE - bool - config SOC_INTEL_TIGERLAKE bool - select SOC_INTEL_TIGERLAKE_BASE - #TODO - Enable INTEL_CAR_NEM_ENHANCED - select INTEL_CAR_NEM help Intel Tigerlake support
-config SOC_INTEL_JASPERLAKE - bool - select SOC_INTEL_TIGERLAKE_BASE - select INTEL_CAR_NEM - help - Intel Jasperlake support - -if SOC_INTEL_TIGERLAKE_BASE +if SOC_INTEL_TIGERLAKE
config CPU_SPECIFIC_OPTIONS def_bool y @@ -36,6 +23,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index e7169cf..12d59b1 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE),y) +ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y)
subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39825/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39825/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC One could change the mainboards to select SOC_INTEL_JASPERLAKE_COPY, do the necessary removals, then drop the _COPY suffix
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Rizwan Qureshi, Justin TerAvest, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39825
to look at the new patch set (#2).
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build.
BUG=b:150217037 TEST=build dedede, jasperlake_rvp and volteer board
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/romstage.c M src/mainboard/google/dedede/variants/baseboard/memory.c M src/mainboard/intel/jasperlake_rvp/dsdt.asl M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc 8 files changed, 13 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39825/2
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39825/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39825/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
One could change the mainboards to select SOC_INTEL_JASPERLAKE_COPY, do the necessary removals, then […]
Isn't this simple. Just switch to SOC_INTEL_JASPERLAKE once done with the clean up, without changing mainboard SoC subscription.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 2: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39825/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39825/2//COMMIT_MSG@14 PS2, Line 14: build dedede, jasper no boot test?
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Rizwan Qureshi, Justin TerAvest, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39825
to look at the new patch set (#3).
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build.
BUG=b:150217037 TEST=build dedede, jasperlake_rvp and volteer board
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/romstage.c M src/mainboard/google/dedede/variants/baseboard/memory.c M src/mainboard/intel/jasperlake_rvp/dsdt.asl M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/jasperlake/romstage/fsp_params.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc 9 files changed, 14 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39825/3
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 3: Code-Review+2
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39825/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39825/2//COMMIT_MSG@14 PS2, Line 14: build dedede, jasper
no boot test?
No, I have dedede on remote setup, I can check and update.
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39825/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39825/2//COMMIT_MSG@14 PS2, Line 14: build dedede, jasper
No, I have dedede on remote setup, I can check and update.
Furquan, I am Seeing a hang in ramstage: PCI: 00:1e.0 PCI: 00:1e.1 PCI: 00:1e.2 child on link 0 SPI: 00 SPI: 00 PCI: 00:1e.3 PCI: 00:1f.0 child on link 0 PNP: 0c09.0 PNP: 0c09.0 PCI: 00:1f.1 PCI: 00:1f.2 PCI: 00:1f.3 child on link 0 GENERIC: 0.0 GENERIC: 0.0 PCI: 00:1f.4 PCI: 00:1f.5 PCI: 00:1f.7 Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 1 / 333 ms
If I reboot, I see hang in bootblock. @Karthik, can you please help check, if issue is seen on your device too. I'll update the observation is crosbug.
I do not have the volteer device to test.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39825/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39825/2//COMMIT_MSG@14 PS2, Line 14: build dedede, jasper
Furquan, I am Seeing a hang in ramstage: […]
I am seeing that you haven't updated the devicetree & overridetree to use jasperlake. Is that in a different CL in this stack?
Furquan Shaikh has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Removed Code-Review+2 by Furquan Shaikh furquan@google.com
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Rizwan Qureshi, Justin TerAvest, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39825
to look at the new patch set (#4).
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build.
BUG=b:150217037 TEST=build dedede, jasperlake_rvp and volteer board
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/romstage.c M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/memory.c M src/mainboard/google/dedede/variants/waddledee/overridetree.cb M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb M src/mainboard/intel/jasperlake_rvp/dsdt.asl M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/jasperlake/romstage/fsp_params.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc 13 files changed, 18 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39825/4
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Rizwan Qureshi, Justin TerAvest, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39825
to look at the new patch set (#5).
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build.
BUG=b:150217037 TEST=build dedede, jasperlake_rvp and volteer board
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/romstage.c M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/memory.c M src/mainboard/google/dedede/variants/waddledee/overridetree.cb M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb M src/mainboard/intel/jasperlake_rvp/dsdt.asl M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/jasperlake/romstage/fsp_params.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc 13 files changed, 18 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39825/5
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39825/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39825/2//COMMIT_MSG@14 PS2, Line 14: build dedede, jasper
I am seeing that you haven't updated the devicetree & overridetree to use jasperlake. […]
Thanks!!. I think it has to be in this CL , when we switch to using soc/intel/jasperlake. Updated now.
My board connection is lost, I'll check for boot and update.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 5: Code-Review+1
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Rizwan Qureshi, Justin TerAvest, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39825
to look at the new patch set (#6).
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build.
BUG=b:150217037 TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board.
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/romstage.c M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/memory.c M src/mainboard/google/dedede/variants/waddledee/overridetree.cb M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb M src/mainboard/intel/jasperlake_rvp/dsdt.asl M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/jasperlake/romstage/fsp_params.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc 13 files changed, 18 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39825/6
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39825/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39825/2//COMMIT_MSG@14 PS2, Line 14: build dedede, jasper
Thanks!!. I think it has to be in this CL , when we switch to using soc/intel/jasperlake. […]
I could test the board for boot.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 6: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 7: -Code-Review
There seem to be some more changes that are required:
src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h:20:10: fatal error: soc/meminit_jsl.h: No such file or directory #include <soc/meminit_jsl.h>
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Rizwan Qureshi, Justin TerAvest, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39825
to look at the new patch set (#8).
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build.
BUG=b:150217037 TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board.
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/romstage.c M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/memory.c M src/mainboard/google/dedede/variants/waddledee/overridetree.cb M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb M src/mainboard/intel/jasperlake_rvp/dsdt.asl M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/jasperlake/romstage/fsp_params.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc 16 files changed, 21 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39825/8
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 8:
Patch Set 7: -Code-Review
There seem to be some more changes that are required:
src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h:20:10: fatal error: soc/meminit_jsl.h: No such file or directory #include <soc/meminit_jsl.h>
Yes, Updated now.
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39825/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39825/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Isn't this simple. […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 8: Code-Review+1
Looks okay to me. Karthik - any concerns?
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 8: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build.
BUG=b:150217037 TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board.
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra aamir.bohra@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Karthik Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/romstage.c M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/memory.c M src/mainboard/google/dedede/variants/waddledee/overridetree.cb M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb M src/mainboard/intel/jasperlake_rvp/dsdt.asl M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/jasperlake/romstage/fsp_params.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc 16 files changed, 21 insertions(+), 33 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 53423b8..98ef6e4 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -18,7 +18,7 @@ 0x20110725 /* OEM revision */ ) { - #include <soc/intel/tigerlake/acpi/platform.asl> + #include <soc/intel/jasperlake/acpi/platform.asl>
/* global NVS and variables */ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> @@ -30,7 +30,7 @@ Device (PCI0) { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/jasperlake/acpi/southbridge.asl> } }
diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 9c220d4..f95e7aa 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -6,7 +6,7 @@ */
#include <baseboard/variants.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *memupd) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 865d4ea..f030b20 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c index ff8a4ec..08c3bde 100644 --- a/src/mainboard/google/dedede/variants/baseboard/memory.c +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -8,7 +8,7 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> #include <gpio.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <soc/romstage.h>
static const struct mb_cfg baseboard_memcfg_cfg = { diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb index 23db34e..388051a 100644 --- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake
# Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 884199c..cb21c63 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake
# Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index c996717..ed59af6 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -25,7 +25,7 @@ 0x20110725 /* OEM revision */ ) { - #include <soc/intel/tigerlake/acpi/platform.asl> + #include <soc/intel/jasperlake/acpi/platform.asl>
/* global NVS and variables */ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> @@ -37,7 +37,7 @@ Device (PCI0) { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/jasperlake/acpi/southbridge.asl> } }
diff --git a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c index 8858e44..f185628 100644 --- a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c @@ -14,7 +14,7 @@ */ #include <baseboard/variants.h> #include <console/console.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <soc/romstage.h> #include "board_id.h"
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h index 27c645b..2fe7631 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -17,7 +17,7 @@ #define __BASEBOARD_VARIANTS_H__
#include <soc/gpio.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 386936e..41921dd 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake
device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c index 1915a1e..4de66b3 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c @@ -16,7 +16,7 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> #include <gpio.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <soc/romstage.h>
static const struct mb_cfg jslrvp_ddr4_memcfg_cfg = { diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 01d7294..844a954 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -1,9 +1,9 @@ -config SOC_INTEL_JASPERLAKE_COPY +config SOC_INTEL_JASPERLAKE bool help Intel Jasperlake support
-if SOC_INTEL_JASPERLAKE_COPY +if SOC_INTEL_JASPERLAKE
config CPU_SPECIFIC_OPTIONS def_bool y @@ -192,7 +192,7 @@ depends on FSP_USE_REPO default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd"
-config SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT +config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT int "Debug Consent for JSL" # USB DBC is more common for developers so make this default to 3 if # SOC_INTEL_DEBUG_CONSENT=y diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 29db4f3..4a65adc 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE_COPY),y) +ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE),y)
subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index ca7ff26..d263834 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -89,7 +89,7 @@ m_cfg->SmbusEnable = config->SmbusEnable;
/* Set debug probe type */ - m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_JASPERLAKE_DEBUG_CONSENT;
/* VT-d config */ m_cfg->VtdDisable = 0; diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 63bd881..e71586d 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -1,22 +1,9 @@ -config SOC_INTEL_TIGERLAKE_BASE - bool - config SOC_INTEL_TIGERLAKE bool - select SOC_INTEL_TIGERLAKE_BASE - #TODO - Enable INTEL_CAR_NEM_ENHANCED - select INTEL_CAR_NEM help Intel Tigerlake support
-config SOC_INTEL_JASPERLAKE - bool - select SOC_INTEL_TIGERLAKE_BASE - select INTEL_CAR_NEM - help - Intel Jasperlake support - -if SOC_INTEL_TIGERLAKE_BASE +if SOC_INTEL_TIGERLAKE
config CPU_SPECIFIC_OPTIONS def_bool y @@ -36,6 +23,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index e7169cf..12d59b1 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE),y) +ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y)
subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39825 )
Change subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC ......................................................................
Patch Set 9:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1978 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1977 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1976
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Aamir Bohra (Code Review)
-
Angel Pons (Code Review)
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Furquan Shaikh (Code Review)
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Karthik Ramasubramanian (Code Review)