coreboot-gerrit April 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs
by Paul Menzel (Code Review) 01 Apr '20

01 Apr '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/24989 ) Change subject: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs ...................................................................... Patch Set 4: (2 comments) > Patch Set 2: > > > Patch Set 2: > > > > Yes, the question is why it is fixed. Is this because there's an inversion being done somewhere where it shouldn't? > > > > We should dump the the gpio config for the one in question and compare w/ the coreboot settings vs what the kerne's pinmux might be doing. > > every cyan variant has the jack detect GPIO defined as 95, PCIE_CLKREQ3B/AUDIO_CODEC_IRQ, > and every one sets it as a GPI, edge triggered both. The kernel cherrytrail pinmux driver actually skips over 95 since it's only listed as having a single/primary function (PCIE_CLKREQ3B) > > Given that, 'ActiveBoth' would seem to be the correct setting for both the codec and LPE device. I'll test and adjust the patch if that works here Nice analysis. Can you add that to the commit message too? https://review.coreboot.org/c/coreboot/+/24989/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/24989/4//COMMIT_MSG@16 PS4, Line 16: Cherrytrail Cherry Trail https://review.coreboot.org/c/coreboot/+/24989/4//COMMIT_MSG@21 PS4, Line 21: Linux What version? -- To view, visit https://review.coreboot.org/c/coreboot/+/24989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Gerrit-Change-Number: 24989 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 09:39:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
by Maxim Polyakov (Code Review) 01 Apr '20

01 Apr '20

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Change in coreboot[master]: cros_ec: add chrome EC headers to include path
by Patrick Georgi (Code Review) 01 Apr '20

01 Apr '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39947 ) Change subject: cros_ec: add chrome EC headers to include path ...................................................................... cros_ec: add chrome EC headers to include path This adds the path to chrome EC headers to the depthcharge build. Depthcharge currently includes a manually maintained copy of the EC headers which are perpetually out of sync with the real interface definitions. By adding the include path, we can build depthcharge with the actual EC interface definitions and eliminate the manual maintenance of copies of EC headers. Once the include path is in place, we can remove the copies of the EC headers from depthcharge. BUG=b:152373049 Change-Id: I1ce0ad9dc99ea52f177d4fb034fd23efd95a7864 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39947 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- M payloads/external/depthcharge/Makefile 1 file changed, 4 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index c1993e4..c4dd1bf 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -10,6 +10,7 @@ libpayload_install_dir=$(output_dir)/lp_$(BOARD) VBOOT_SOURCE ?= $(abspath $(CURDIR)/../../../3rdparty/vboot) +EC_HEADERS ?= $(abspath $(CURDIR)/../../../3rdparty/chromeec/include) TAG-$(DEPTHCHARGE_MASTER)=origin/master TAG-$(DEPTHCHARGE_STABLE)=$(STABLE_COMMIT_ID) @@ -79,13 +80,15 @@ cd $(project_dir) && \ $(MAKE) BOARD=$(BOARD) \ LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \ - VB_SOURCE=$(VBOOT_SOURCE) defconfig + VB_SOURCE=$(VBOOT_SOURCE) \ + EC_HEADERS=$(EC_HEADERS) defconfig build: config echo " MAKE $(project_name) $(TAG-y)" $(MAKE) -C $(project_dir) depthcharge BOARD=$(BOARD) \ LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \ VB_SOURCE=$(VBOOT_SOURCE) \ + EC_HEADERS=$(EC_HEADERS) \ PATH="$(abspath ../../../build/util/cbfstool):$$PATH" clean: -- To view, visit https://review.coreboot.org/c/coreboot/+/39947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ce0ad9dc99ea52f177d4fb034fd23efd95a7864 Gerrit-Change-Number: 39947 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
by Maxim Polyakov (Code Review) 01 Apr '20

01 Apr '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39425 ) Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver ...................................................................... Patch Set 15: (5 comments) Thanks so much to everyone for review and testing :) https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/acp… File src/soc/intel/xeon_sp/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/acp… PS11, Line 5: define > This file was removed from the change. Marking as resolved. These macros are used only here, but I would like to put this in any of the *.h files to make apci code more clean. https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/acp… PS11, Line 27: /* GPIO Community 0 */ : CreateDWordField (^RBUF, ^COM0._BAS, BAS0) : CreateDWordField (^RBUF, ^COM0._LEN, LEN0) : > This file was removed from the change. Marking as resolved. At the moment, acpi still needs a lot of changes, so I moved this to the commit commit: https://review.coreboot.org/c/coreboot/+/39979 https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/acp… PS11, Line 37: GPIO_BASE_SIZE > This file was removed from the change. Marking as resolved. At the moment, acpi still needs a lot of changes, so I moved this to the commit commit: https://review.coreboot.org/c/coreboot/+/39979 https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/acp… PS11, Line 88: Subtract > Please use the new asl syntax where possible Done in https://review.coreboot.org/c/coreboot/+/39979/1..2 https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/inc… File src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h: https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/inc… PS11, Line 340: ALIGN_UP > *poke* In my case, that's not possible, because the macro DIV_ROUND_UP contains {} #define DIV_ROUND_UP(x, y) ({ \ typeof(x) _div_local_x = (x); \ typeof(y) _div_local_y = (y); \ (_div_local_x + _div_local_y - 1) / _div_local_y; \ }) -- To view, visit https://review.coreboot.org/c/coreboot/+/39425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Gerrit-Change-Number: 39425 Gerrit-PatchSet: 15 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Apr 2020 09:13:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Andrey Petrov <andrey.petrov(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
by Angel Pons (Code Review) 01 Apr '20

01 Apr '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39425 ) Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver ...................................................................... Patch Set 15: Code-Review+2 (5 comments) https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/acp… File src/soc/intel/xeon_sp/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/acp… PS11, Line 5: define > Don't you need to include this file from somewhere else? Like in the main PCH asl file? This file was removed from the change. Marking as resolved. https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/acp… PS11, Line 27: /* GPIO Community 0 */ : CreateDWordField (^RBUF, ^COM0._BAS, BAS0) : CreateDWordField (^RBUF, ^COM0._LEN, LEN0) : > actually it compiles fine, I was just stuffing this in wrong acpi namespace. […] This file was removed from the change. Marking as resolved. https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/acp… PS11, Line 37: GPIO_BASE_SIZE > we do not have this defined, we need to find out this value for C620 This file was removed from the change. Marking as resolved. https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/acp… PS11, Line 88: Subtract > Please use the new asl syntax where possible This file was removed from the change. Marking as resolved. https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/inc… File src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h: https://review.coreboot.org/c/coreboot/+/39425/11/src/soc/intel/xeon_sp/inc… PS11, Line 340: ALIGN_UP > Use DIV_ROUND_UP instead? *poke* -- To view, visit https://review.coreboot.org/c/coreboot/+/39425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Gerrit-Change-Number: 39425 Gerrit-PatchSet: 15 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Apr 2020 08:46:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Andrey Petrov <andrey.petrov(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Stitches CSE blobs into FW_MAIN_X partitions
by Angel Pons (Code Review) 01 Apr '20

01 Apr '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35406 ) Change subject: soc/intel/common/basecode: Stitches CSE blobs into FW_MAIN_X partitions ...................................................................... Patch Set 42: (2 comments) https://review.coreboot.org/c/coreboot/+/35406/42//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35406/42//COMMIT_MSG@7 PS42, Line 7: Stitches Stitch https://review.coreboot.org/c/coreboot/+/35406/42/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/Makefile.inc: https://review.coreboot.org/c/coreboot/+/35406/42/src/soc/intel/common/bloc… PS42, Line 14: sleep 1 Why the sleep? -- To view, visit https://review.coreboot.org/c/coreboot/+/35406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d2908e9e16858c5f333e1b10b19d18b7ca27765 Gerrit-Change-Number: 35406 Gerrit-PatchSet: 42 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 01 Apr 2020 08:43:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Paul Menzel (Code Review) 01 Apr '20

01 Apr '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Patch Set 3: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG@13 PS3, Line 13: Mention that in 2015 there were problems in FSP? -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 08:20:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 01 Apr '20

01 Apr '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 73: (2 comments) https://review.coreboot.org/c/coreboot/+/35402/71/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35402/71/src/soc/intel/common/bloc… PS71, Line 237: boot_partition_id > Agreed. Done https://review.coreboot.org/c/coreboot/+/35402/71/src/soc/intel/common/bloc… PS71, Line 270: : /* : * Configuration data error occurred, it needs to be : * handled with MKHI DATA_CLEAR command. : */ : BP_STATUS_DATA_FAILURE = 3, > Relevant only during CSE FW downgrade support. I remove it now. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 73 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Apr 2020 07:34:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/cannonlake: Enables CSE update flow for CML
by Sridhar Siricilla (Code Review) 01 Apr '20

01 Apr '20

Sridhar Siricilla has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35404 ) Change subject: src/soc/intel/cannonlake: Enables CSE update flow for CML ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/35404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87887870cdd4c492f7d228f482c8037023ac16fa Gerrit-Change-Number: 35404 Gerrit-PatchSet: 43 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: sc7180: Add QUPv3 FW load & config
by Roja Rani Yarubandi (Code Review) 01 Apr '20

01 Apr '20

Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35499 ) Change subject: sc7180: Add QUPv3 FW load & config ...................................................................... Patch Set 44: (1 comment) https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/q… File src/soc/qualcomm/sc7180/qupv3_config.c: https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/q… PS40, Line 75: /* To maintain Div=4 for QcLib, configure clock to 7372800Hz for sc7180 */ > Checking with QcLib team UART driver can derive 115200 baud from any of the frequencies maintained by QUP clock table, usually from low to high. Here, as we are able to achieve 115200 baud from 7372800Hz frequency, so hope this is fine and no need of any fix from QcLib. -- To view, visit https://review.coreboot.org/c/coreboot/+/35499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Gerrit-Change-Number: 35499 Gerrit-PatchSet: 44 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-CC: Stephen Boyd <swboyd(a)chromium.org> Gerrit-CC: Taniya Das <tdas(a)codeaurora.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 07:30:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2020