coreboot-gerrit April 2020

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Change in coreboot[master]: soc/amd/common/psp: Move early init to soc
by Felix Held (Code Review) 02 Apr '20

02 Apr '20

Hello Marshall Dawson, Eric Peers, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40000 to review the following change. Change subject: soc/amd/common/psp: Move early init to soc ...................................................................... soc/amd/common/psp: Move early init to soc The initialization code in common//psp is very specific to Family 15h. Move this to the stoneyridge directory. TEST: Verify PSP functionality on google/grunt Change-Id: Ice3d06d6437f59a529c26fc2359565c940d39482 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020365 Reviewed-by: Eric Peers <epeers(a)google.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/Makefile.inc M src/soc/amd/common/block/psp/psp.c M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/include/soc/southbridge.h A src/soc/amd/stoneyridge/psp.c M src/soc/amd/stoneyridge/romstage.c 7 files changed, 75 insertions(+), 126 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/40000/1 diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 494f174..42c802d 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -15,24 +15,8 @@ #ifndef __AMD_PSP_H__ #define __AMD_PSP_H__ -#include <amdblocks/agesawrapper.h> -#include <soc/pci_devs.h> -#include <types.h> - -/* Extra, Special Purpose Registers in the PSP PCI Config Space */ - -/* PSP Mirror Features Capabilities and Control Register */ -#define PSP_PCI_MIRRORCTRL1_REG 0x44 /* PSP Mirror Ctrl Reg */ -#define PMNXTPTRW_MASK 0xff /* PCI AFCR pointer mask */ -#define PMNXTPTRW_EXPOSE 0xa4 /* Pointer to expose the AFCR */ - -#define PSP_PCI_EXT_HDR_CTRL 0x48 /* Extra PCI Header Ctrl */ -#define MAGIC_ENABLES 0x34 /* Extra PCI HDR Ctl Enables */ - -#define PSP_MAILBOX_BASE 0x70 /* Mailbox offset from PCIe BAR */ - -#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */ -#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ +/* Get the mailbox base address - specific to family of device. */ +struct psp_mbox *soc_get_mbox_address(void); /* x86 to PSP commands */ #define MBOX_BIOS_CMD_DRAM_INFO 0x01 diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index d5f9386..2f5de1d 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -1,3 +1,4 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index a32c9b7..d53a746 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -33,73 +33,6 @@ static const char *psp_status_cmd_timeout = "error: PSP command timeout"; static const char *psp_status_noerror = ""; -static void psp_bar_init_early(void) -{ - u32 psp_mmio_size; - u32 value32; - u32 base, limit; - - /* Check for presence of the PSP */ - if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { - printk(BIOS_WARNING, "PSP: SOC_PSP_DEV device not found at D%xF%x\n", - PSP_DEV, PSP_FUNC); - return; - } - - /* Check if PSP BAR has been assigned, and if so, just return */ - if (pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) & - ~PCI_BASE_ADDRESS_MEM_ATTR_MASK) - return; - - /* Otherwise, do an early init of the BAR */ - pci_write_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4, 0xffffffff); - psp_mmio_size = ~pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) + 1; - printk(BIOS_SPEW, "PSP: BAR size is 0x%x\n", psp_mmio_size); - /* Assign BAR to an initial temporarily defined region */ - pci_write_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4, - PSP_MAILBOX_BAR3_BASE); - - /* Route MMIO through the northbridge */ - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, - (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); - limit = ((PSP_MAILBOX_BAR3_BASE + psp_mmio_size - 1) >> 8) & ~0xff; - pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(7), limit); - base = (PSP_MAILBOX_BAR3_BASE >> 8) | MMIO_WE | MMIO_RE; - pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(7), base); - pci_write_config32(SOC_PSP_DEV, PSP_PCI_EXT_HDR_CTRL, MAGIC_ENABLES); - - /* Update the capability chain */ - value32 = pci_read_config32(SOC_PSP_DEV, PSP_PCI_MIRRORCTRL1_REG); - value32 &= ~PMNXTPTRW_MASK; - value32 |= PMNXTPTRW_EXPOSE; - pci_write_config32(SOC_PSP_DEV, PSP_PCI_MIRRORCTRL1_REG, value32); -} - -static uintptr_t get_psp_bar3_addr(void) -{ - uintptr_t psp_mmio; - - /* Check for presence of the PSP */ - if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { - printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n", - PSP_DEV, PSP_FUNC); - return 0; - } - - /* D8F0x48[12] is the Bar3Hide flag, check it */ - if (pci_read_config32(SOC_PSP_DEV, PSP_PCI_EXT_HDR_CTRL) & BAR3HIDE) { - psp_mmio = rdmsr(MSR_CU_CBBCFG).lo; - if (psp_mmio == 0xffffffff) { - printk(BIOS_WARNING, "PSP: BAR hidden, MSR val uninitialized\n"); - return 0; - } - return psp_mmio; - } else { - return pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) & - ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - } -} - static const char *status_to_string(int err) { switch (err) { @@ -120,23 +53,6 @@ } } -static struct psp_mbox *get_mbox_address(void) -{ - uintptr_t baseptr; - - baseptr = get_psp_bar3_addr(); - if (baseptr == 0) { - psp_bar_init_early(); - baseptr = get_psp_bar3_addr(); - if (baseptr == 0) { - printk(BIOS_WARNING, "PSP: %s(), psp_bar_init_early() failed...\n", - __func__); - return NULL; - } - } - return (struct psp_mbox *)(baseptr + PSP_MAILBOX_BASE); -} - static u32 rd_mbox_sts(struct psp_mbox *mbox) { return read32(&mbox->mbox_status); @@ -192,7 +108,7 @@ static int send_psp_command(u32 command, void *buffer) { - struct psp_mbox *mbox = get_mbox_address(); + struct psp_mbox *mbox = soc_get_mbox_address(); if (!mbox) return -PSPSTS_NOBASE; diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 96b8303..50e53c4 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -59,6 +59,7 @@ romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +romstage-y += psp.c verstage-y += gpio.c verstage-y += i2c.c @@ -93,6 +94,7 @@ ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c +ramstage-y += psp.c all-y += reset.c @@ -102,6 +104,7 @@ smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-y += gpio.c +smm-y += psp.c CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 45bad1f..7384951 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -290,10 +290,17 @@ #define SPI_RD4DW_EN_HOST BIT(15) /* Platform Security Processor D8F0 */ +void soc_enable_psp_early(void); + #define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */ +#define PSP_MAILBOX_OFFSET 0x70 /* offset from BAR3 value */ + #define PSP_BAR_ENABLES 0x48 #define PSP_MAILBOX_BAR_EN 0x10 +#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */ +#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ + /* IO 0xcf9 - Reset control port*/ #define FULL_RST BIT(3) #define RST_CMD BIT(2) diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c new file mode 100644 index 0000000..bc2d725 --- /dev/null +++ b/src/soc/amd/stoneyridge/psp.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <console/console.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <cpu/x86/msr.h> +#include <soc/pci_devs.h> +#include <soc/northbridge.h> +#include <soc/southbridge.h> +#include <amdblocks/psp.h> + +void soc_enable_psp_early(void) +{ + u32 base, limit, cmd; + + /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ + base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; + limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); + pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); + pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); + + /* Preload a value into BAR and enable it */ + pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); + pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); + + /* Enable memory access and master */ + cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); + cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); +}; + +struct psp_mbox *soc_get_mbox_address(void) +{ + uintptr_t psp_mmio; + + /* Check for presence of the PSP */ + if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { + printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n", + PSP_DEV, PSP_FUNC); + return 0; + } + + /* Determine if Bar3Hide has been set, and if hidden get the base from + * the MSR instead. */ + if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { + psp_mmio = rdmsr(MSR_CU_CBBCFG).lo; + if (psp_mmio == 0xffffffff) { + printk(BIOS_WARNING, "PSP: BAR hidden, MSR val uninitialized\n"); + return 0; + } + } else { + psp_mmio = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + } + + return (struct psp_mbox *)(psp_mmio + PSP_MAILBOX_OFFSET); +} diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index efe75b7..fab9a83 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -31,6 +31,7 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> #include <soc/northbridge.h> +#include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> @@ -42,28 +43,6 @@ /* By default, don't do anything */ } -static void load_smu_fw1(void) -{ - u32 base, limit, cmd; - - /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ - base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; - limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); - - /* Preload a value into "BAR3" and enable it */ - pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); - pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); - - /* Enable memory access and master */ - cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); - cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); - - psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); -} - static void agesa_call(void) { post_code(0x37); @@ -92,8 +71,9 @@ console_init(); + soc_enable_psp_early(); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) - load_smu_fw1(); + psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); mainboard_romstage_entry_s3(s3_resume); elog_boot_notify(s3_resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/40000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice3d06d6437f59a529c26fc2359565c940d39482 Gerrit-Change-Number: 40000 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/psp: Make common function to print status
by Felix Held (Code Review) 02 Apr '20

02 Apr '20

Hello Raul Rangel, Marshall Dawson, Marshall Dawson, Eric Peers, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39998 to review the following change. Change subject: soc/amd/common/psp: Make common function to print status ...................................................................... soc/amd/common/psp: Make common function to print status Consolidate commands' printing of status into one static function. TEST: Verify PSP functionality on google/grunt Change-Id: Id8abe0d1d4ac87f6d4f625593f47bf484729906f Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020363 Reviewed-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-by: Eric Peers <epeers(a)google.com> Tested-by: Eric Peers <epeers(a)google.com> --- M src/soc/amd/common/block/psp/psp.c 1 file changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39998/1 diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index cf25fd1..0294422 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -226,6 +226,21 @@ } /* + * Print meaningful status to the console. Caller only passes a pointer to a + * buffer if it's expected to contain its own status. + */ +static void print_cmd_status(int cmd_status, struct mbox_default_buffer *buffer) +{ + if (buffer && rd_resp_sts(buffer)) + printk(BIOS_DEBUG, "buffer status=0x%x ", rd_resp_sts(buffer)); + + if (cmd_status) + printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status)); + else + printk(BIOS_DEBUG, "OK\n"); +} + +/* * Notify the PSP that DRAM is present. Upon receiving this command, the PSP * will load its OS into fenced DRAM that is not accessible to the x86 cores. */ @@ -243,13 +258,7 @@ cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); /* buffer's status shouldn't change but report it if it does */ - if (rd_resp_sts(&buffer)) - printk(BIOS_DEBUG, "buffer status=0x%x ", - rd_resp_sts(&buffer)); - if (cmd_status) - printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status)); - else - printk(BIOS_DEBUG, "OK\n"); + print_cmd_status(cmd_status, &buffer); return cmd_status; } @@ -273,13 +282,7 @@ cmd_status = send_psp_command(MBOX_BIOS_CMD_BOOT_DONE, &buffer); /* buffer's status shouldn't change but report it if it does */ - if (rd_resp_sts(&buffer)) - printk(BIOS_DEBUG, "buffer status=0x%x ", - rd_resp_sts(&buffer)); - if (cmd_status) - printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status)); - else - printk(BIOS_DEBUG, "OK\n"); + print_cmd_status(cmd_status, &buffer); } /* @@ -305,10 +308,7 @@ /* Blob commands use the buffer registers as data, not pointer to buf */ cmd_status = send_psp_command(type, addr); - if (cmd_status) - printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status)); - else - printk(BIOS_DEBUG, "OK\n"); + print_cmd_status(cmd_status, NULL); return cmd_status; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8abe0d1d4ac87f6d4f625593f47bf484729906f Gerrit-Change-Number: 39998 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Publish single GPIO ACPI device for Jasper Lake
by Aamir Bohra (Code Review) 02 Apr '20

02 Apr '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40037 ) Change subject: soc/intel/jasperlake: Publish single GPIO ACPI device for Jasper Lake ...................................................................... soc/intel/jasperlake: Publish single GPIO ACPI device for Jasper Lake Current pin-ctrl kernel(v5.4) driver expects the firmware to publish single GPIO ACPI device. Until kernel pin-ctrl driver implementation is updated to consume community based GPIO ACPI device, updating the current ACPI code to comply with pin-ctrl driver requirement. BUG=b:150154277 TEST=Verify intel pin-ctrl driver can successfully load in OS Change-Id: I5c88eb4f03fd59074c0bef336f389d6c0de97304 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/jasperlake/acpi/gpio.asl 1 file changed, 36 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/40037/1 diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl index 9bf0c60..47a1dac 100644 --- a/src/soc/intel/jasperlake/acpi/gpio.asl +++ b/src/soc/intel/jasperlake/acpi/gpio.asl @@ -11,108 +11,70 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#include <intelblocks/gpio.h> #include <soc/gpio_defs.h> #include <soc/irq.h> #include <soc/pcr_ids.h> -#include <intelblocks/gpio.h> #include "gpio_op.asl" -Device (GCM0) +Device (GPIO) { Name (_HID, CROS_GPIO_NAME) Name (_UID, 0) - Name (_DDN, "GPIO Controller Community 0") + Name (_DDN, "GPIO Controller") Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM2) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) { GPIO_IRQ14 } }) + Method (_CRS, 0, NotSerialized) { + /* GPIO Community 0 */ CreateDWordField (^RBUF, ^COM0._BAS, BAS0) - BAS0 = ^^PCRB (PID_GPIOCOM0) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + Store (^^PCRB (PID_GPIOCOM0), BAS0) + Store (GPIO_BASE_SIZE, LEN0) -Device (GCM1) -{ - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 1) - Name (_DDN, "GPIO Controller Community 1") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { + /* GPIO Community 1 */ CreateDWordField (^RBUF, ^COM1._BAS, BAS1) - BAS1 = ^^PCRB (PID_GPIOCOM1) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + Store (^^PCRB (PID_GPIOCOM1), BAS1) + Store (GPIO_BASE_SIZE, LEN1) -Device (GCM4) -{ - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 4) - Name (_DDN, "GPIO Controller Community 4") + /* GPIO Community 2 */ + CreateDWordField (^RBUF, ^COM2._BAS, BAS2) + CreateDWordField (^RBUF, ^COM2._LEN, LEN2) + Store (^^PCRB (PID_GPIOCOM2), BAS2) + Store (GPIO_BASE_SIZE, LEN2) - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { + /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) - BAS4 = ^^PCRB (PID_GPIOCOM4) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + Store (^^PCRB (PID_GPIOCOM4), BAS4) + Store (GPIO_BASE_SIZE, LEN4) -Device (GCM5) -{ - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 5) - Name (_DDN, "GPIO Controller Community 5") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { + /* GPIO Community 5 */ CreateDWordField (^RBUF, ^COM5._BAS, BAS5) - BAS5 = ^^PCRB (PID_GPIOCOM5) - Return (^RBUF) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + Store (^^PCRB (PID_GPIOCOM5), BAS5) + Store (GPIO_BASE_SIZE, LEN5) + + Return (RBUF) } - Method (_STA) + + Method (_STA, 0, NotSerialized) { Return (0xF) } } - /* * Get GPIO DW0 Address * Arg0 - GPIO Number @@ -153,3 +115,4 @@ Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) Return (Local2) } + -- To view, visit https://review.coreboot.org/c/coreboot/+/40037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c88eb4f03fd59074c0bef336f389d6c0de97304 Gerrit-Change-Number: 40037 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572
by Michael Niewöhner (Code Review) 02 Apr '20

02 Apr '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mainboard: Add Acer ES1-572 ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@31 PS5, Line 31: - Battery. I have it somewhere. > ACPI code needs to be added to communicate with the EC. […] wut? only ACPI? we don't have a driver for the EC -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Apr 2020 13:52:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
by Maxim Polyakov (Code Review) 02 Apr '20

02 Apr '20

Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39425 to look at the new patch set (#17). Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver ...................................................................... soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver Adds definitions that allow to use the common GPIO driver to configure the Lewisburg PCH pads. Using the GPIO configuration from common/gpio, unlike the FSP-style definitions from Intel RefCode [1] definitions, is more understandable and makes the motherboards code much cleaner. In addition, we can use utilities, such as intetool, to analyze the configuration of proprietary firmware to add support for new server motherboards with Skylake-SP processors. The pin layout in this patch corresponds to the driver in the Linux kernel for Lewisburg PCH GPIO hardware [2] [1] https://designintools.intel.com/product_p/stlgrn45.htm [2] drivers/pinctrl/intel/pinctrl-lewisburg.c These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/gpio.c A src/soc/intel/xeon_sp/include/soc/gpio.h A src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h M src/soc/intel/xeon_sp/include/soc/pcr_ids.h 5 files changed, 885 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39425/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/39425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Gerrit-Change-Number: 39425 Gerrit-PatchSet: 17 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/lenovo/*: Add vboot RO FMAPs on 12MiB devices
by Philipp Deppenwiese (Code Review) 02 Apr '20

02 Apr '20

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39450 ) Change subject: mb/lenovo/*: Add vboot RO FMAPs on 12MiB devices ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9be0c5e06fcb8287d32171cb72dabb5fcf047e7a Gerrit-Change-Number: 39450 Gerrit-PatchSet: 3 Gerrit-Owner: Marcello Sylvester Bauer <sylv(a)sylv.io> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 02 Apr 2020 11:21:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/field_pg_m6: Do various improvements
by Felix Singer (Code Review) 02 Apr '20

02 Apr '20

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39984 to review the following change. Change subject: mb/siemens/field_pg_m6: Do various improvements ...................................................................... mb/siemens/field_pg_m6: Do various improvements * Select INTEL_GMA_HAVE_VBT * Add cmos.layout * Add option to disable VT-d * Add option to disable HyperThreading * Move mainboard_init() (GPIO config) to romstage * Update devicetree wrt. SlotImplemented (WIP) * Configure EC device enablement Individual bits are based on observation of the original BIOS. For the Chili variant, add a Kconfig option to enable the debug USB port. * Lock flash early based on CMOS option If the CMOS option `inhibit_flashlock` is _not_ set, enable write- protection and lock the flash down early. This workaround is re- quired as current FSP always locks the SPI interface after PCI enumeration, so we can't enable write-protection when we actually decide to do it (i.e. in the payload). Change-Id: I8d22ff74a65ca4b1c63e751ee91af3b110aac0ed Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/mainboard/siemens/field_pg_m6/Kconfig M src/mainboard/siemens/field_pg_m6/Makefile.inc A src/mainboard/siemens/field_pg_m6/cmos.layout A src/mainboard/siemens/field_pg_m6/ec.c A src/mainboard/siemens/field_pg_m6/ec.h M src/mainboard/siemens/field_pg_m6/mainboard.c M src/mainboard/siemens/field_pg_m6/romstage.c M src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc M src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb 9 files changed, 261 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/39984/1 diff --git a/src/mainboard/siemens/field_pg_m6/Kconfig b/src/mainboard/siemens/field_pg_m6/Kconfig index aeee917..55e7fef 100644 --- a/src/mainboard/siemens/field_pg_m6/Kconfig +++ b/src/mainboard/siemens/field_pg_m6/Kconfig @@ -9,8 +9,11 @@ select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_UART_8250IO if BOARD_SIEMENS_FIELD_PG_M6_BASE + select EC_ACPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION select SOC_INTEL_CANNONLAKE_PCH_H diff --git a/src/mainboard/siemens/field_pg_m6/Makefile.inc b/src/mainboard/siemens/field_pg_m6/Makefile.inc index e957121..bb023f6 100644 --- a/src/mainboard/siemens/field_pg_m6/Makefile.inc +++ b/src/mainboard/siemens/field_pg_m6/Makefile.inc @@ -6,5 +6,8 @@ romstage-y += romstage.c ramstage-y += mainboard.c +ramstage-y += ec.c + +smm-y += ec.c subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/siemens/field_pg_m6/cmos.layout b/src/mainboard/siemens/field_pg_m6/cmos.layout new file mode 100644 index 0000000..4548540 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/cmos.layout @@ -0,0 +1,61 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +0 120 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: cpu +400 1 e 5 hyper_threading +401 1 e 5 vtd + +# coreboot config options: pch +408 2 e 4 power_on_after_fail + +# coreboot config options: mainboard +440 1 e 5 ethernet1 +441 1 e 1 inhibit_flashlock + +# payload config options +512 256 s 0 boot_devices +768 8 h 0 boot_default +784 1 e 1 cmos_defaults_loaded + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 No +1 1 Yes +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew +4 0 Disable +4 1 Enable +4 2 Keep +5 0 Disable +5 1 Enable +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/siemens/field_pg_m6/ec.c b/src/mainboard/siemens/field_pg_m6/ec.c new file mode 100644 index 0000000..511c0d4 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/ec.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <timer.h> + +#include "ec.h" + +#define EC_STATUS 0x50 +#define EC_RUNNING (1 << 1) +#define EC_DEVICE_CONTROL_1 0x80 +#define EC_DEVICE_CONTROL_1_PROGAS_ON (1 << 0) +#define EC_DEVICE_CONTROL_1_BOOMER_ON (1 << 1) +#define EC_DEVICE_CONTROL_1_BT_RF_ON (1 << 2) +#define EC_DEVICE_CONTROL_1_TP_ON (1 << 3) +#define EC_DEVICE_CONTROL_1_LAN2_RST (1 << 6) +#define EC_DEVICE_CONTROL_2 0x81 +#define EC_DEVICE_CONTROL_2_LAN_1_ON (1 << 0) +#define EC_DEVICE_CONTROL_2_LAN_2_ON (1 << 1) +#define EC_DEVICE_CONTROL_2_WLAN_ON (1 << 2) +#define EC_DEVICE_CONTROL_2_USB_ON (1 << 3) +#define EC_DEVICE_CONTROL_2_IDE1_ON (1 << 4) +#define EC_DEVICE_CONTROL_2_IDE2_ON (1 << 5) +#define EC_DEVICE_CONTROL_2_COM1_ON (1 << 6) +#define EC_DEVICE_CONTROL_2_MPI_ON (1 << 7) + +#define RUNNING_TIMEOUT_MS 3333 + +static bool ec_running(void) +{ + struct stopwatch sw; + uint8_t ec_status; + + stopwatch_init_msecs_expire(&sw, RUNNING_TIMEOUT_MS); + do + ec_status = ec_read(EC_STATUS); + while (!(ec_status & EC_RUNNING) && !stopwatch_expired(&sw)); + + if (!(ec_status & EC_RUNNING)) + printk(BIOS_WARNING, "EC not ready after %dms\n", RUNNING_TIMEOUT_MS); + + return !!(ec_status & EC_RUNNING); +} + +void ec_enable_devices(bool enable_usb) +{ + uint8_t control_1, control_2; + + if (!ec_running()) + return; + + control_1 = ec_read(EC_DEVICE_CONTROL_1); + control_2 = ec_read(EC_DEVICE_CONTROL_2); + + printk(BIOS_INFO, "EC previous EDC1: 0x%02x\n", control_1); + printk(BIOS_INFO, "EC previous EDC2: 0x%02x\n", control_2); + + control_1 &= ~(EC_DEVICE_CONTROL_1_BT_RF_ON); + control_1 |= EC_DEVICE_CONTROL_1_BOOMER_ON; + + control_2 &= ~(EC_DEVICE_CONTROL_2_WLAN_ON | EC_DEVICE_CONTROL_2_USB_ON); + control_2 |= EC_DEVICE_CONTROL_2_MPI_ON; + if (enable_usb) + control_2 |= EC_DEVICE_CONTROL_2_USB_ON; + + ec_write(EC_DEVICE_CONTROL_1, control_1); + ec_write(EC_DEVICE_CONTROL_2, control_2); + + printk(BIOS_INFO, "EC current EDC1: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_1)); + printk(BIOS_INFO, "EC current EDC2: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_2)); +} + +void mainboard_smi_sleep(const uint8_t slp_typ) +{ + uint8_t control_1, control_2; + + if (slp_typ != ACPI_S5) + return; + + if (!ec_running()) + return; + + control_1 = ec_read(EC_DEVICE_CONTROL_1); + control_2 = ec_read(EC_DEVICE_CONTROL_2); + + printk(BIOS_INFO, "EC previous EDC1: 0x%02x\n", control_1); + printk(BIOS_INFO, "EC previous EDC2: 0x%02x\n", control_2); + + control_1 &= ~(EC_DEVICE_CONTROL_1_BOOMER_ON); + control_2 &= ~(EC_DEVICE_CONTROL_2_USB_ON | EC_DEVICE_CONTROL_2_MPI_ON); + + ec_write(EC_DEVICE_CONTROL_1, control_1); + ec_write(EC_DEVICE_CONTROL_2, control_2); + + printk(BIOS_INFO, "EC current EDC1: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_1)); + printk(BIOS_INFO, "EC current EDC2: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_2)); +} diff --git a/src/mainboard/siemens/field_pg_m6/ec.h b/src/mainboard/siemens/field_pg_m6/ec.h new file mode 100644 index 0000000..ca69a42 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/ec.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SIEMENS_FIELD_PG_M6_EC_H +#define _SIEMENS_FIELD_PG_M6_EC_H + +void ec_enable_devices(bool enable_usb); + +#endif /* _SIEMENS_FIELD_PG_M6_EC_H */ diff --git a/src/mainboard/siemens/field_pg_m6/mainboard.c b/src/mainboard/siemens/field_pg_m6/mainboard.c index 508ba22..a61ca2e 100644 --- a/src/mainboard/siemens/field_pg_m6/mainboard.c +++ b/src/mainboard/siemens/field_pg_m6/mainboard.c @@ -3,19 +3,50 @@ * This file is part of the coreboot project. */ +#include <stdint.h> + +#include <arch/acpi.h> +#include <bootstate.h> +#include <console/console.h> #include <device/device.h> -#include <soc/gpio.h> -#include "variant.h" +#include <intelblocks/fast_spi.h> +#include <pc80/mc146818rtc.h> -static void mainboard_init(void *chip_info) +#include "ec.h" + +static void mainboard_dev_init(struct device *dev) { - const struct pad_config *pads; - size_t num; + const bool enable_usb = CONFIG(BOARD_SIEMENS_FIELD_PG_M6_BASE); + ec_enable_devices(enable_usb); +} - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_dev_init; } struct chip_operations mainboard_ops = { - .init = mainboard_init, + .enable_dev = mainboard_enable, }; + +static void mainboard_lockdown(void *unused) +{ + u8 inhibit_flashlock = 0; + unsigned int pr; + + get_option(&inhibit_flashlock, "inhibit_flashlock"); + + if (acpi_is_wakeup_s3() || !inhibit_flashlock) { + for (pr = 0; pr < 5; ++pr) { + if (!fast_spi_pr_set_and_lock(pr, 0xffff0000)) + break; + } + if (pr == 5) + die("Failed to find and lock a PR register.\n"); + } else { + inhibit_flashlock = 0; + set_option("inhibit_flashlock", &inhibit_flashlock); + } +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, mainboard_lockdown, NULL); diff --git a/src/mainboard/siemens/field_pg_m6/romstage.c b/src/mainboard/siemens/field_pg_m6/romstage.c index 9c2af94..ee31a1b 100644 --- a/src/mainboard/siemens/field_pg_m6/romstage.c +++ b/src/mainboard/siemens/field_pg_m6/romstage.c @@ -3,12 +3,29 @@ * This file is part of the coreboot project. */ +#include <stdint.h> + +#include <option.h> +#include <pc80/mc146818rtc.h> #include <soc/cnl_memcfg_init.h> +#include <soc/gpio.h> #include <soc/romstage.h> #include <spd_bin.h> +#include "variant.h" + +static void mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { + uint8_t vtd = 1; const struct cnl_mb_cfg cfg = { .spd = { [0] = { READ_SMBUS, { 0x50 << 1 } }, @@ -23,4 +40,10 @@ cannonlake_memcfg_init(&memupd->FspmConfig, &cfg); memupd->FspmConfig.EccSupport = 1; memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE; + + get_option(&vtd, "vtd"); + memupd->FspmTestConfig.VtdDisable = !vtd; + get_option(&memupd->FspmConfig.HyperThreading, "hyper_threading"); + + mainboard_init(); } diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc b/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc index d55796c..c24fb5e 100644 --- a/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc +++ b/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. -ramstage-y += gpio.c +romstage-y += gpio.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb b/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb index 8fd83dd..5ebaae2 100644 --- a/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb +++ b/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb @@ -33,6 +33,7 @@ register "PcieRpEnable[0]" = "1" register "PcieRpEnable[5]" = "1" register "PcieRpEnable[16]" = "1" +# register "PcieRpSlotImplemented[16]" = "1" register "PcieClkSrcUsage[2]" = "0" register "PcieClkSrcUsage[5]" = "5" -- To view, visit https://review.coreboot.org/c/coreboot/+/39984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d22ff74a65ca4b1c63e751ee91af3b110aac0ed Gerrit-Change-Number: 39984 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Michael Niewöhner (Code Review) 02 Apr '20

02 Apr '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG@23 PS3, Line 23: Tested successfully with PSI3/4 enabled. > S-Series CPUs with 1151 socket do not have C9/C10 but only C8. […] Updated commit msg accordingly -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Apr 2020 10:53:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Michael Niewöhner (Code Review) 02 Apr '20

02 Apr '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Uploaded patch set 5: Commit message was updated. (2 comments) https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG@18 PS3, Line 18: Boards that have a domain_vr_config and set their specific settings are > Those settings are not in the bios/uefi on any of the firmwares I have checked. […] Done https://review.coreboot.org/c/coreboot/+/39980/3//COMMIT_MSG@23 PS3, Line 23: Tested successfully with PSI3/4 enabled. > I'm still trying to find out; the board has the MP2955 but there is no ds. […] S-Series CPUs with 1151 socket do not have C9/C10 but only C8. Since only C10 makes use of S4 those CPUs won't ever request PS4. That means we do not need to disable it explicitly for these boards. -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Apr 2020 10:53:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Michael Niewöhner (Code Review) 02 Apr '20

02 Apr '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Patrick Rudolph, Matt DeVillier, Benjamin Doron, Christian Walter, Paul Menzel, Matthew Garrett, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39980 to look at the new patch set (#5). Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default There are boards that do not need a specific domain_vr_config because the defaults provided by the soc code are sufficient. Currently, this means that these boards can't benefit from lower power states (PSI 3 and 4) because the settings default to being disabled since at the time the defaults have been defined (2015) there were bugs in FSP in this regard. Set the default values of psiXenable to 1 for boards that do not have a domain_vr_config setting in their devicetree, just like Cannon Lake does. Boards that have a domain_vr_config and set their specific settings are not affected at all. Currently, there are only three boards that have no domain_vr_config: - supermicro/x11-lga1151-series These boards have a MPS MP2955 which we can assume support for PS3 (the MP2965 and MP2935 support it, too). S-series CPUs with a 1151 socket do not have C9/C10 but only C8 and since only C10 makes use of PS4, those CPUs won't ever request PS4. That means we do not need to disable it explicitly for these boards. - 51nb/x210: Needs testing and/or VR datasheet check for PS3/PS4 support Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/vr_config.c 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39980/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2020