coreboot-gerrit April 2020

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Benjamin Doron (Code Review) 02 Apr '20

02 Apr '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Patch Set 6: Code-Review-1 (1 comment) https://review.coreboot.org/c/coreboot/+/39980/6/src/soc/intel/skylake/vr_c… File src/soc/intel/skylake/vr_config.c: https://review.coreboot.org/c/coreboot/+/39980/6/src/soc/intel/skylake/vr_c… PS6, Line 24: PSI3 and PSI4 are disabled. This is untrue. -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Apr 2020 21:35:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Matt DeVillier (Code Review) 02 Apr '20

02 Apr '20

Matt DeVillier has uploaded a new patch set (#6) to the change originally created by Michael Niewöhner. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default There are boards that do not need a specific domain_vr_config because the defaults provided by the soc code are sufficient. Currently, this means that these boards can't benefit from lower power states (PSI 3 and 4) because the settings default to being disabled. Set the default values of psiXenable to 1 for boards that do not have a domain_vr_config setting in their devicetree, just like Cannon Lake does. Boards that have a domain_vr_config and set their specific settings are not affected at all. Currently, there are only three boards that have no domain_vr_config: - supermicro/x11-lga1151-series/variants/x11ssm-f: Tested successfully with PSI3/4 enabled. - supermicro/x11-lga1151-series/variants/x11ssh-tf: Needs testing. This board is mostly identical to x11ssm-f and thus is expected to just work fine. - 51nb/x210: Needs testing. Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/vr_config.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39980/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/braswell: add ACPI backlight support
by Matt DeVillier (Code Review) 02 Apr '20

02 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39943 ) Change subject: soc/intel/braswell: add ACPI backlight support ...................................................................... soc/intel/braswell: add ACPI backlight support Add framework to generate ACPI methods in SSDT for screen backlight control. To make use of this, individual boards will need to include default_brightness_levels.asl in their dsdt, as well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to their devicetree. Change-Id: I0adccc6c8bee71d3c1b7840518308c8dc8ea2d81 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/chip.h M src/soc/intel/braswell/gfx.c 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/39943/1 diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 026e491..5f1aaee 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -21,6 +21,7 @@ #define _SOC_CHIP_H_ #include <stdint.h> +#include <drivers/intel/gma/i915.h> #include <fsp/util.h> #include <intelblocks/lpc_lib.h> #include <soc/pci_devs.h> @@ -169,6 +170,8 @@ uint8_t I2C4Frequency; uint8_t I2C5Frequency; uint8_t I2C6Frequency; + + struct i915_gpu_controller_info gfx; }; #endif /* _SOC_CHIP_H_ */ diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index ff73955..faef4c7 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -18,6 +18,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <drivers/intel/gma/opregion.h> +#include <drivers/intel/gma/i915.h> #include <reg_script.h> #include <soc/gfx.h> #include <soc/nvs.h> @@ -87,10 +88,29 @@ gnvs_ptr->aslb = aslb; } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + struct device *dev = pcidev_on_root(GFX_DEV, GFX_FUNC); + if (!dev || !dev->enabled) + return NULL; + + struct soc_intel_braswell_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(struct device *dev) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (gfx) + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct device_operations gfx_device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = gma_ssdt, .init = gfx_init, .ops_pci = &soc_pci_ops, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/39943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0adccc6c8bee71d3c1b7840518308c8dc8ea2d81 Gerrit-Change-Number: 39943 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Simplify GMA SSDT generator
by Matt DeVillier (Code Review) 02 Apr '20

02 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39948 ) Change subject: nb/intel/haswell: Simplify GMA SSDT generator ...................................................................... nb/intel/haswell: Simplify GMA SSDT generator Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt_generator is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. Only check we need is if a given board has supplied the i915 controller info to populate the SSDT. Change-Id: Icd9caf622dd4c46b13589ebb772138b25888752f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/northbridge/intel/haswell/gma.c 1 file changed, 6 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39948/1 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 65c5cf3..afb495d 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -524,24 +524,13 @@ intel_gma_restore_opregion(); } -const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) +static void gma_generate_ssdt(struct device *device) { - struct device *dev = pcidev_on_root(2, 0); - if (!dev) { - return NULL; - } - struct northbridge_intel_haswell_config *chip = dev->chip_info; - return &chip->gfx; -} + const struct northbridge_intel_haswell_config *chip = device->chip_info; + const struct i915_gpu_controller_info *gfx = &chip->gfx; -static void gma_ssdt(struct device *device) -{ - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - if (!gfx) { - return; - } - - drivers_intel_gma_displays_ssdt_generate(gfx); + if (gfx) + drivers_intel_gma_displays_ssdt_generate(gfx); } static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, @@ -577,7 +566,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, - .acpi_fill_ssdt_generator = gma_ssdt, + .acpi_fill_ssdt_generator = gma_generate_ssdt, .scan_bus = NULL, .enable = NULL, .ops_pci = &gma_pci_ops, -- To view, visit https://review.coreboot.org/c/coreboot/+/39948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd9caf622dd4c46b13589ebb772138b25888752f Gerrit-Change-Number: 39948 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/baytrail: add ACPI backlight support
by Matt DeVillier (Code Review) 02 Apr '20

02 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39942 ) Change subject: soc/intel/baytrail: add ACPI backlight support ...................................................................... soc/intel/baytrail: add ACPI backlight support Add framework to generate ACPI methods in SSDT for screen backlight control. To make use of this, individual boards will need to include default_brightness_levels.asl in their dsdt, as well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to their devicetree. Change-Id: I0b7fc45bda3aaf89306bedb579fb1e9f8ce07926 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/baytrail/chip.h M src/soc/intel/baytrail/gfx.c 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/39942/1 diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 0fa7eaf..52b1e33 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -18,6 +18,7 @@ #ifndef _BAYTRAIL_CHIP_H_ #define _BAYTRAIL_CHIP_H_ +#include <drivers/intel/gma/i915.h> #include <stdint.h> struct soc_intel_baytrail_config { @@ -84,6 +85,8 @@ uint16_t gpu_pipeb_power_cycle_delay; int gpu_pipeb_pwm_freq_hz; int disable_ddr_2x_refresh_rate; + + struct i915_gpu_controller_info gfx; }; #endif /* _BAYTRAIL_CHIP_H_ */ diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 417f36e..197c085 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -397,6 +397,25 @@ intel_gma_restore_opregion(); } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + struct device *dev = pcidev_on_root(GFX_DEV, GFX_FUNC); + if (!dev || !dev->enabled) + return NULL; + + struct soc_intel_baytrail_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(struct device *device) +{ + const struct i915_gpu_controller_info *gfx = + intel_gma_get_controller_info(); + if (gfx) + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, @@ -428,6 +447,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gfx_init, + .acpi_fill_ssdt_generator = gma_ssdt, .ops_pci = &soc_pci_ops, .write_acpi_tables = gma_write_acpi_tables, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/39942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b7fc45bda3aaf89306bedb579fb1e9f8ce07926 Gerrit-Change-Number: 39942 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/beltino: drop ACPI brightness control stub
by Matt DeVillier (Code Review) 02 Apr '20

02 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39946 ) Change subject: mb/google/beltino: drop ACPI brightness control stub ...................................................................... mb/google/beltino: drop ACPI brightness control stub beltino variants are Chromeboxes without built-in displays, so now that default_brightness_levels.asl is no longer required for all boards in a platform, drop it. Change-Id: Ie8147763fc9fdf4f184d3d000bffd6794e134d9e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/beltino/dsdt.asl 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/39946/1 diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index f494d2f..da11fed 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -38,8 +38,6 @@ { #include <northbridge/intel/haswell/acpi/haswell.asl> #include <southbridge/intel/lynxpoint/acpi/pch.asl> - - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8147763fc9fdf4f184d3d000bffd6794e134d9e Gerrit-Change-Number: 39946 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/poppy: Add support for ACPI brightness controls
by Matt DeVillier (Code Review) 02 Apr '20

02 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39945 ) Change subject: mb/google/poppy: Add support for ACPI brightness controls ...................................................................... mb/google/poppy: Add support for ACPI brightness controls Change-Id: Ie7eb4c43178acff2dc5ff7c685e71990d8f353c9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/poppy/dsdt.asl M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb 8 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39945/1 diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index dceccc2..7a21384 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -41,6 +41,7 @@ #include <soc/intel/skylake/acpi/ipu.asl> #include <soc/intel/skylake/acpi/systemagent.asl> #include <soc/intel/skylake/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 52a2dc7..b7ab523 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_pp_up_delay_ms" = "200" register "gpu_pp_down_delay_ms" = "50" register "gpu_pp_cycle_delay_ms" = "600" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index d960474..7772534 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 1b3fdcc..e4d148c 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 66ceb2d..c3404bf 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 75fcf9c..96fcc39 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index f44f9ce..6557870 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_pp_up_delay_ms" = "200" register "gpu_pp_down_delay_ms" = "500" register "gpu_pp_cycle_delay_ms" = "600" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 4711b1f..146d8d2 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/39945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7eb4c43178acff2dc5ff7c685e71990d8f353c9 Gerrit-Change-Number: 39945 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/gma: drop intel_gma_get_controller_info()
by Matt DeVillier (Code Review) 02 Apr '20

02 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39962 ) Change subject: drivers/intel/gma: drop intel_gma_get_controller_info() ...................................................................... drivers/intel/gma: drop intel_gma_get_controller_info() Drop function prototype, since all implementations have been removed. Change-Id: I2e7b5ac7352a1434652b5e6d37bb3744c68b2328 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/drivers/intel/gma/i915.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/39962/1 diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index fc7b35a..ff44ac1 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -99,8 +99,6 @@ void drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf); -const struct i915_gpu_controller_info * -intel_gma_get_controller_info(void); /* vbt.c */ struct device; -- To view, visit https://review.coreboot.org/c/coreboot/+/39962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e7b5ac7352a1434652b5e6d37bb3744c68b2328 Gerrit-Change-Number: 39962 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulation/qemu-q35: drop unused intel_gma_get_controller_info()
by Matt DeVillier (Code Review) 02 Apr '20

02 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39961 ) Change subject: mb/emulation/qemu-q35: drop unused intel_gma_get_controller_info() ...................................................................... mb/emulation/qemu-q35: drop unused intel_gma_get_controller_info() No longer needed anywhere Change-Id: Ifeea76af44377d917ec46cac0d9d7375d1a68204 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/emulation/qemu-q35/mainboard.c 1 file changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/39961/1 diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index aea6d41..4ccbcd0 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -16,7 +16,6 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <pc80/keyboard.h> -#include <drivers/intel/gma/i915.h> #define Q35_PAM0 0x90 @@ -25,14 +24,6 @@ 10, 10, 11, 11, }; -struct i915_gpu_controller_info gfx_controller_info = GMA_STATIC_DISPLAYS(0); - -const struct i915_gpu_controller_info * -intel_gma_get_controller_info(void) -{ - return &gfx_controller_info; -} - static void qemu_nb_init(struct device *dev) { /* Map memory at 0xc0000 - 0xfffff */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeea76af44377d917ec46cac0d9d7375d1a68204 Gerrit-Change-Number: 39961 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/pineview: drop unused intel_gma_get_controller_info()
by Matt DeVillier (Code Review) 02 Apr '20

02 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39960 ) Change subject: nb/intel/pineview: drop unused intel_gma_get_controller_info() ...................................................................... nb/intel/pineview: drop unused intel_gma_get_controller_info() No longer used by southbridge, no longer needed since pineview doesn't utilize drivers_intel_gma_displays_ssdt_generate() Change-Id: Ia386f8fcd208e201fb8bc2a37cdbecd6f45a044b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/northbridge/intel/pineview/gma.c 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/39960/1 diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 0b04ade..bb259d5 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -289,17 +289,6 @@ intel_gma_restore_opregion(); } -const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) -{ - struct device *dev = pcidev_on_root(2, 0); - if (!dev) { - printk(BIOS_WARNING, "WARNING: Can't find IGD (0,2,0)\n"); - return NULL; - } - struct northbridge_intel_pineview_config *chip = dev->chip_info; - return &chip->gfx; -} - static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { -- To view, visit https://review.coreboot.org/c/coreboot/+/39960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia386f8fcd208e201fb8bc2a37cdbecd6f45a044b Gerrit-Change-Number: 39960 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit April 2020