Change in coreboot[master]: mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39970 )
Change subject: mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA ......................................................................
mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA
Certain PCIe endpoints cause an exception inside AmdInitMid when PCIe ClockPM is enabled in AGESA PCIe initialization structures. Disable it to allow platform to boot with such devices. coreboot driver enables the ClockPM correctly on such devices anyway.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I7fb13f915861c26cf773960abb12a3a1c0211cdc --- M src/mainboard/pcengines/apu2/OemCustomize.c 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/39970/1
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index e47a2c8..8b6cd03 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -35,7 +35,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_PORT3_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { @@ -47,7 +47,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -59,7 +59,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -71,7 +71,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { @@ -83,7 +83,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_GFX_RESET_ID, - ClkPmSupportEnabled) + 0) } };
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39970 )
Change subject: mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA ......................................................................
Patch Set 1: Code-Review+2
Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39970 )
Change subject: mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA ......................................................................
mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA
Certain PCIe endpoints cause an exception inside AmdInitMid when PCIe ClockPM is enabled in AGESA PCIe initialization structures. Disable it to allow platform to boot with such devices. coreboot driver enables the ClockPM correctly on such devices anyway.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I7fb13f915861c26cf773960abb12a3a1c0211cdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/39970 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/pcengines/apu2/OemCustomize.c 1 file changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index e47a2c8..8b6cd03 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -35,7 +35,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_PORT3_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { @@ -47,7 +47,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -59,7 +59,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -71,7 +71,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { @@ -83,7 +83,7 @@ PcieGenMaxSupported, AspmL0sL1, PCIE_GFX_RESET_ID, - ClkPmSupportEnabled) + 0) } };
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39970 )
Change subject: mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1957 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1956 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1955
Please note: This test is under development and might not be accurate at all!
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39970 )
Change subject: mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39970/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39970/2//COMMIT_MSG@8 PS2, Line 8: : Certain PCIe endpoints cause an exception inside AmdInitMid when PCIe : ClockPM is enabled in AGESA PCIe initialization structures. Disable it : to allow platform to boot with such devices. How can this be reproduced exactly?
How does the exception look like?
https://review.coreboot.org/c/coreboot/+/39970/2/src/mainboard/pcengines/apu... File src/mainboard/pcengines/apu2/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/39970/2/src/mainboard/pcengines/apu... PS2, Line 38: 0) A comment would help, that coreboot takes care of this?
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Michał Żygowski (Code Review)
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Paul Menzel (Code Review)