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Change in coreboot[master]: Revert "i82371eb: Drop support for older PIIX chips"
by Patrick Georgi (Code Review) 06 Mar '20

06 Mar '20

Hello build bot (Jenkins), Paul Menzel, Angel Pons, Keith Hui, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39238 to review the following change. Change subject: Revert "i82371eb: Drop support for older PIIX chips" ...................................................................... Revert "i82371eb: Drop support for older PIIX chips" This reverts commit 2b9004de602f98a404b17584ab3e1451f165c1f4. Reason for revert: QEMU emulates that chipset and with that commit a Linux guest kernel can't find IDE devices anymore. Change-Id: Iad75af4ea9993d6a2ec5433ad30d39900dab874e --- M src/southbridge/intel/i82371eb/i82371eb.c M src/southbridge/intel/i82371eb/ide.c M src/southbridge/intel/i82371eb/isa.c M src/southbridge/intel/i82371eb/usb.c 4 files changed, 83 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39238/1 diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c index 02812ce..898cdff 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.c +++ b/src/southbridge/intel/i82371eb/i82371eb.c @@ -14,9 +14,22 @@ * GNU General Public License for more details. */ -/* Note: This code supports the 82371AB/EB/MB. */ +/* Note: This code supports the 82371FB/SB/MX/AB/EB/MB and 82437MX. */ /* Datasheets: + * - Name: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR + * - URL: http://www.intel.com/design/intarch/datashts/290550.htm + * - PDF: http://download.intel.com/design/intarch/datashts/29055002.pdf + * - Date: April 1997 + * - Order Number: 290550-002 + * + * - Name: 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerator + * Specification Update + * - URL: http://www.intel.com/design/chipsets/specupdt/297658.htm + * - PDF: http://download.intel.com/design/chipsets/specupdt/29765801.pdf + * - Date: March 1998 + * - Order Number: 297658-004 + * * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) * (applies to 82371AB/EB/MB, a.k.a. PIIX4/PIIX4E/PIIX4M) * - URL: http://www.intel.com/design/intarch/datashts/290562.htm @@ -31,8 +44,10 @@ * - Order Number: 297738-017 */ +/* TODO: List the other datasheets. */ + #include <device/device.h> const struct chip_operations southbridge_intel_i82371eb_ops = { - CHIP_NAME("Intel 82371AB/EB/MB Southbridge") + CHIP_NAME("Intel 82371FB/SB/MX/AB/EB/MB Southbridge") }; diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c index 1b8136a..7a72a65 100644 --- a/src/southbridge/intel/i82371eb/ide.c +++ b/src/southbridge/intel/i82371eb/ide.c @@ -119,6 +119,18 @@ } /** + * IDE init for the Intel 82371FB/SB IDE controller. + * + * These devices do not support UDMA/33, so don't attempt to enable it. + * + * @param dev The device to use. + */ +static void ide_init_i82371fb_sb(struct device *dev) +{ + ide_init_enable(dev); +} + +/** * IDE init for the Intel 82371AB/EB/MB IDE controller. * * @param dev The device to use. @@ -129,6 +141,17 @@ ide_init_udma33(dev); } +/* Intel 82371FB/SB */ +static const struct device_operations ide_ops_fb_sb = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init_i82371fb_sb, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, /* No subsystem IDs on 82371XX! */ +}; + /* Intel 82371AB/EB/MB */ static const struct device_operations ide_ops_ab_eb_mb = { .read_resources = pci_dev_read_resources, @@ -140,6 +163,34 @@ .ops_pci = 0, /* No subsystem IDs on 82371XX! */ }; +/* Intel 82371FB (PIIX) */ +static const struct pci_driver ide_driver_fb __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371FB_IDE, +}; + +/* Intel 82371SB (PIIX3) */ +static const struct pci_driver ide_driver_sb __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_IDE, +}; + +/* Intel 82371MX (MPIIX) */ +static const struct pci_driver ide_driver_mx __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371MX_ISA_IDE, +}; + +/* Intel 82437MX (part of the 430MX chipset) */ +static const struct pci_driver ide_driver_82437mx __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82437MX_ISA_IDE, +}; + /* Intel 82371AB/EB/MB */ static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = { .ops = &ide_ops_ab_eb_mb, diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index fefead0..a57d61a 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -157,3 +157,9 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82371AB_ISA, }; + +static const struct pci_driver isa_SB_driver __pci_driver = { + .ops = &isa_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_ISA, +}; diff --git a/src/southbridge/intel/i82371eb/usb.c b/src/southbridge/intel/i82371eb/usb.c index 38ab167..80b19a1 100644 --- a/src/southbridge/intel/i82371eb/usb.c +++ b/src/southbridge/intel/i82371eb/usb.c @@ -43,6 +43,15 @@ .ops_pci = 0, /* No subsystem IDs on 82371EB! */ }; +/* Note: No USB on 82371FB/MX (PIIX/MPIIX) and 82437MX. */ + +/* Intel 82371SB (PIIX3) */ +static const struct pci_driver usb_driver_sb __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_USB, +}; + /* Intel 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) */ /* The 440MX (82443MX) consists of 82443BX + 82371EB (uses same PCI IDs). */ static const struct pci_driver usb_driver_ab_eb_mb __pci_driver = { -- To view, visit https://review.coreboot.org/c/coreboot/+/39238 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad75af4ea9993d6a2ec5433ad30d39900dab874e Gerrit-Change-Number: 39238 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

7 12

Change in coreboot[master]: soc/intel/common/block/tco: clear TCO1_STS register, too
by Patrick Georgi (Code Review) 06 Mar '20

06 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39259 ) Change subject: soc/intel/common/block/tco: clear TCO1_STS register, too ...................................................................... soc/intel/common/block/tco: clear TCO1_STS register, too The register TCO1_STS is never cleared, which will cause SMIs to either retrigger over and over again (e.g. TIMEOUT) or prevent concurrent interrupt events, depending on which event triggered. Clear both TCO2_STS and TCO1_STS. This also fixes the issue where SECOND_TO_STS will always end up set in the SMI handler by unconditionally (re)setting it. Tested on X11SSM-F, where enabling TCO caused the terminal to get flooded with SMI debug messages. With this patch, a message gets written every ~1 second. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Ia57c203a672fdd0095355a7e2a0e01aaa6657968 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39259 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Andrey Petrov <anpetrov(a)fb.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/smbus/tco.c 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Aaron Durbin: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve Andrey Petrov: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1a215eb..bd8790a 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -74,13 +74,13 @@ uint16_t tco1_sts; uint16_t tco2_sts; - /* TCO Status 2 register */ - tco2_sts = tco_read_reg(TCO2_STS); - tco2_sts |= TCO_STS_SECOND_TO; - tco_write_reg(TCO2_STS, tco2_sts); - /* TCO Status 1 register */ tco1_sts = tco_read_reg(TCO1_STS); + tco_write_reg(TCO1_STS, tco1_sts); + + /* TCO Status 2 register */ + tco2_sts = tco_read_reg(TCO2_STS); + tco_write_reg(TCO2_STS, tco2_sts | TCO_STS_SECOND_TO); return (tco2_sts << 16) | tco1_sts; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia57c203a672fdd0095355a7e2a0e01aaa6657968 Gerrit-Change-Number: 39259 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/lenovo/x230: Add Lenovo X230 Tablet to the list of X230 variants
by Peter Lemenkov (Code Review) 06 Mar '20

06 Mar '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38482 ) Change subject: mb/lenovo/x230: Add Lenovo X230 Tablet to the list of X230 variants ...................................................................... mb/lenovo/x230: Add Lenovo X230 Tablet to the list of X230 variants Lenovo ThinkPad X230t Convertible Laptop works well with X230 default image (see CB:34361). Change-Id: Ib0a73fd551f0d26c789d3fd13541b2d1571742cb Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x230/Kconfig.name 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38482/1 diff --git a/src/mainboard/lenovo/x230/Kconfig.name b/src/mainboard/lenovo/x230/Kconfig.name index d207653..4f02d55 100644 --- a/src/mainboard/lenovo/x230/Kconfig.name +++ b/src/mainboard/lenovo/x230/Kconfig.name @@ -1,2 +1,2 @@ config BOARD_LENOVO_X230 - bool "ThinkPad X230" + bool "ThinkPad X230 / X230t" -- To view, visit https://review.coreboot.org/c/coreboot/+/38482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0a73fd551f0d26c789d3fd13541b2d1571742cb Gerrit-Change-Number: 38482 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: mb/lenovo: Remove thermal.h header
by Peter Lemenkov (Code Review) 06 Mar '20

06 Mar '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38781 ) Change subject: mb/lenovo: Remove thermal.h header ...................................................................... mb/lenovo: Remove thermal.h header We include it only in one file. So let's simplify everything and do like autoport does. Change-Id: I71f092ed7582b4931122d72f41d0b42a7569b96e Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/l520/acpi_tables.c D src/mainboard/lenovo/l520/thermal.h M src/mainboard/lenovo/s230u/acpi_tables.c D src/mainboard/lenovo/s230u/thermal.h M src/mainboard/lenovo/t400/acpi_tables.c D src/mainboard/lenovo/t400/thermal.h M src/mainboard/lenovo/t410/acpi_tables.c D src/mainboard/lenovo/t410/thermal.h M src/mainboard/lenovo/t420/acpi_tables.c D src/mainboard/lenovo/t420/thermal.h M src/mainboard/lenovo/t420s/acpi_tables.c D src/mainboard/lenovo/t420s/thermal.h M src/mainboard/lenovo/t430/acpi_tables.c D src/mainboard/lenovo/t430/thermal.h M src/mainboard/lenovo/t430s/acpi_tables.c D src/mainboard/lenovo/t430s/thermal.h M src/mainboard/lenovo/t520/acpi_tables.c D src/mainboard/lenovo/t520/thermal.h M src/mainboard/lenovo/t530/acpi_tables.c D src/mainboard/lenovo/t530/thermal.h M src/mainboard/lenovo/t60/acpi_tables.c D src/mainboard/lenovo/t60/thermal.h M src/mainboard/lenovo/x131e/acpi_tables.c D src/mainboard/lenovo/x131e/thermal.h M src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c D src/mainboard/lenovo/x1_carbon_gen1/thermal.h M src/mainboard/lenovo/x200/acpi_tables.c D src/mainboard/lenovo/x200/thermal.h M src/mainboard/lenovo/x201/acpi_tables.c D src/mainboard/lenovo/x201/thermal.h M src/mainboard/lenovo/x220/acpi_tables.c D src/mainboard/lenovo/x220/thermal.h M src/mainboard/lenovo/x230/acpi_tables.c D src/mainboard/lenovo/x230/thermal.h M src/mainboard/lenovo/x60/acpi_tables.c D src/mainboard/lenovo/x60/thermal.h 36 files changed, 40 insertions(+), 608 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/38781/1 diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c index d6452af..d8535b4 100644 --- a/src/mainboard/lenovo/l520/acpi_tables.c +++ b/src/mainboard/lenovo/l520/acpi_tables.c @@ -17,13 +17,12 @@ #include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { // the lid is open by default. gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/l520/thermal.h b/src/mainboard/lenovo/l520/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/l520/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/s230u/acpi_tables.c b/src/mainboard/lenovo/s230u/acpi_tables.c index e7ddf82..45b5568 100644 --- a/src/mainboard/lenovo/s230u/acpi_tables.c +++ b/src/mainboard/lenovo/s230u/acpi_tables.c @@ -14,13 +14,12 @@ */ #include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { /* The LID is open by default */ gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/s230u/thermal.h b/src/mainboard/lenovo/s230u/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/s230u/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 6fed293..3a48170 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/smp/mpspec.h> #include <device/device.h> #include <southbridge/intel/i82801ix/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -31,8 +30,8 @@ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/t400/thermal.h b/src/mainboard/lenovo/t400/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/t400/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t410/acpi_tables.c b/src/mainboard/lenovo/t410/acpi_tables.c index 2a8d935..9513143 100644 --- a/src/mainboard/lenovo/t410/acpi_tables.c +++ b/src/mainboard/lenovo/t410/acpi_tables.c @@ -16,13 +16,12 @@ */ #include <southbridge/intel/ibexpeak/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - /* the lid is open by default. */ gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t410/thermal.h b/src/mainboard/lenovo/t410/thermal.h deleted file mode 100644 index d8c9480..0000000 --- a/src/mainboard/lenovo/t410/thermal.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t420/acpi_tables.c b/src/mainboard/lenovo/t420/acpi_tables.c index e2d9814..b278512 100644 --- a/src/mainboard/lenovo/t420/acpi_tables.c +++ b/src/mainboard/lenovo/t420/acpi_tables.c @@ -14,13 +14,12 @@ */ #include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { // the lid is open by default. gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t420/thermal.h b/src/mainboard/lenovo/t420/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/t420/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c index e2d9814..b278512 100644 --- a/src/mainboard/lenovo/t420s/acpi_tables.c +++ b/src/mainboard/lenovo/t420s/acpi_tables.c @@ -14,13 +14,12 @@ */ #include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { // the lid is open by default. gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t420s/thermal.h b/src/mainboard/lenovo/t420s/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/t420s/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c index ea7e52f..155989d 100644 --- a/src/mainboard/lenovo/t430/acpi_tables.c +++ b/src/mainboard/lenovo/t430/acpi_tables.c @@ -14,17 +14,16 @@ */ #include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { // the lid is open by default. gnvs->lids = 1; - gnvs->f0of = CTDP_DOWN_THRESHOLD_OFF; - gnvs->f0on = CTDP_DOWN_THRESHOLD_ON; + gnvs->f0of = 80; + gnvs->f0on = 90; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; + gnvs->tmax = 105; } diff --git a/src/mainboard/lenovo/t430/thermal.h b/src/mainboard/lenovo/t430/thermal.h deleted file mode 100644 index edfe3bc..0000000 --- a/src/mainboard/lenovo/t430/thermal.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Config TDP Sensor ID */ -#define CTDP_SENSOR_ID 0 /* PECI */ - -/* Config TDP Nominal */ -#define CTDP_NOMINAL_THRESHOLD_OFF 0 -#define CTDP_NOMINAL_THRESHOLD_ON 0 - -/* Config TDP Down */ -#define CTDP_DOWN_THRESHOLD_OFF 80 -#define CTDP_DOWN_THRESHOLD_ON 90 - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 105 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t430s/acpi_tables.c b/src/mainboard/lenovo/t430s/acpi_tables.c index e2d9814..b278512 100644 --- a/src/mainboard/lenovo/t430s/acpi_tables.c +++ b/src/mainboard/lenovo/t430s/acpi_tables.c @@ -14,13 +14,12 @@ */ #include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { // the lid is open by default. gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t430s/thermal.h b/src/mainboard/lenovo/t430s/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/t430s/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index e2d9814..b278512 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -14,13 +14,12 @@ */ #include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { // the lid is open by default. gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t520/thermal.h b/src/mainboard/lenovo/t520/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/t520/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index e2d9814..b278512 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -14,13 +14,12 @@ */ #include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { // the lid is open by default. gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t530/thermal.h b/src/mainboard/lenovo/t530/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/t530/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 46bb0d9..8f1d6d4 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -15,7 +15,6 @@ */ #include <southbridge/intel/i82801gx/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -23,6 +22,6 @@ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t60/thermal.h b/src/mainboard/lenovo/t60/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/t60/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x131e/acpi_tables.c b/src/mainboard/lenovo/x131e/acpi_tables.c index e2d9814..b278512 100644 --- a/src/mainboard/lenovo/x131e/acpi_tables.c +++ b/src/mainboard/lenovo/x131e/acpi_tables.c @@ -14,13 +14,12 @@ */ #include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { // the lid is open by default. gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/x131e/thermal.h b/src/mainboard/lenovo/x131e/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/x131e/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c index e2d9814..b278512 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c @@ -14,13 +14,12 @@ */ #include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { // the lid is open by default. gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/x1_carbon_gen1/thermal.h b/src/mainboard/lenovo/x1_carbon_gen1/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/x1_carbon_gen1/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 6fed293..3a48170 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/smp/mpspec.h> #include <device/device.h> #include <southbridge/intel/i82801ix/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -31,8 +30,8 @@ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/x200/thermal.h b/src/mainboard/lenovo/x200/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/x200/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index 6a29ba0..dc59b26 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -16,10 +16,9 @@ */ #include <southbridge/intel/ibexpeak/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/x201/thermal.h b/src/mainboard/lenovo/x201/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/x201/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c index e2d9814..b278512 100644 --- a/src/mainboard/lenovo/x220/acpi_tables.c +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -14,13 +14,12 @@ */ #include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { // the lid is open by default. gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/x220/thermal.h b/src/mainboard/lenovo/x220/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/x220/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c index e2d9814..b278512 100644 --- a/src/mainboard/lenovo/x230/acpi_tables.c +++ b/src/mainboard/lenovo/x230/acpi_tables.c @@ -14,13 +14,12 @@ */ #include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { // the lid is open by default. gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/x230/thermal.h b/src/mainboard/lenovo/x230/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/x230/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index 46bb0d9..8f1d6d4 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -15,7 +15,6 @@ */ #include <southbridge/intel/i82801gx/nvs.h> -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -23,6 +22,6 @@ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/x60/thermal.h b/src/mainboard/lenovo/x60/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/x60/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71f092ed7582b4931122d72f41d0b42a7569b96e Gerrit-Change-Number: 38781 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: mb/intel/tglrvp: Enable Audio AIC with Max98373 & ALC5682 on TGL
by Srinidhi N Kaushik (Code Review) 06 Mar '20

06 Mar '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38561 ) Change subject: mb/intel/tglrvp: Enable Audio AIC with Max98373 & ALC5682 on TGL ...................................................................... mb/intel/tglrvp: Enable Audio AIC with Max98373 & ALC5682 on TGL Add support for Max98373 speaker amp & ALC5682 headset codec BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I013dbc6246b07a501f9bff80c2bca3594e6cc146 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 44 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/38561/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index fbd1c39..80bd47a 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -81,6 +81,20 @@ [PchSerialIoIndexUART2] = PchSerialIoPci, }" + #HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[0]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y @@ -112,7 +126,36 @@ device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 - device pci 15.0 on end # I2C0 0xA0E8 + device pci 15.0 on # I2C0 0xA0E8 + chip drivers/i2c/max98373 + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""RIGHT SPEAKER AMP"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "6" + register "imon_slot_no" = "7" + register "uid" = "1" + register "desc" = ""LEFT SPEAKER AMP"" + register "name" = ""MAXL"" + device i2c 32 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_C12_IRQ)" + register "probed" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C0 device pci 15.1 on end # I2C1 0xA0E9 device pci 15.2 on end # I2C2 0xA0EA device pci 15.3 on end # I2C3 0xA0EB -- To view, visit https://review.coreboot.org/c/coreboot/+/38561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I013dbc6246b07a501f9bff80c2bca3594e6cc146 Gerrit-Change-Number: 38561 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/mediatek/mt8183: improve the DRAMC runtime config flow
by huayang duan (Code Review) 06 Mar '20

06 Mar '20

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38490 ) Change subject: soc/mediatek/mt8183: improve the DRAMC runtime config flow ...................................................................... soc/mediatek/mt8183: improve the DRAMC runtime config flow move channel loop at the top level to reduce the redundancy logic. Change-Id: Iea623d1bd1f7d736e81f66f191a1bf8476d30404 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 4 files changed, 126 insertions(+), 132 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/38490/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index c7d6c74..e9b1bd6 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -285,13 +285,12 @@ (0x1 << 29) | (0xf << 4) | (0x1 << 0), (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); - for (u8 b = 0; b < 2; b++) { + for (u8 b = 0; b < 2; b++) clrsetbits32(&ch[chn].phy.b[b].dq[9], - (0x7 << 28) | (0x7 << 24), - (0x1 << 28) | (0x0 << 24)); - setbits32(&ch[chn].phy.b[b].dq[5], 0x1 << 31); - } + (0x7 << 28) | (0x7 << 24), (0x1 << 28) | (0x0 << 24)); clrbits32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); + for (u8 b = 0; b < 2; b++) + setbits32(&ch[chn].phy.b[b].dq[5], 0x1 << 31); setbits32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31)); setbits32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31)); @@ -321,16 +320,14 @@ clrbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 31); } -static void dramc_hw_gating_init(void) +static void dramc_hw_gating_init(size_t chn) { - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - clrbits32(&ch[chn].ao.stbcal, - (0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21)); - setbits32(&ch[chn].ao.stbcal, (0x1 << 20) | (0x3 << 28)); - setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 24); + clrbits32(&ch[chn].ao.stbcal, + (0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21)); + setbits32(&ch[chn].ao.stbcal, (0x1 << 20) | (0x3 << 28)); + setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 24); - dramc_hw_dqs_gating_tracking(chn); - } + dramc_hw_dqs_gating_tracking(chn); } static void dramc_impedance_tracking_enable(void) @@ -348,24 +345,25 @@ setbits32(&ch[chn].ao.refctrl0, (0x1 << 2) | (0x1 << 3)); } -static void dramc_phy_low_power_enable(void) +static void dramc_phy_low_power_enable(size_t chn) { - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - for (size_t b = 0; b < 2; b++) { - clrbits32(&ch[chn].phy.b[b].dll_fine_tune[2], - 0x3fffff << 10); - write32(&ch[chn].phy.b[b].dll_fine_tune[3], 0x2e800); - } - clrsetbits32(&ch[chn].phy.ca_dll_fine_tune[2], - 0x3fffff << 10, 0x2 << 10); + for (size_t b = 0; b < 2; b++) { + clrbits32(&ch[chn].phy.b[b].dll_fine_tune[2], + 0x3fffff << 10); + write32(&ch[chn].phy.b[b].dll_fine_tune[3], 0x2e800); } - write32(&ch[0].phy.ca_dll_fine_tune[3], 0xba000); - write32(&ch[1].phy.ca_dll_fine_tune[3], 0x3a000); + clrsetbits32(&ch[chn].phy.ca_dll_fine_tune[2], + 0x3fffff << 10, 0x2 << 10); + + if (chn == CHANNEL_A) + write32(&ch[chn].phy.ca_dll_fine_tune[3], 0xba000); + else + write32(&ch[chn].phy.ca_dll_fine_tune[3], 0x3a000); } static void dramc_dummy_read_for_tracking_enable(u8 chn) { - setbits32(&ch[chn].ao.dummy_rd, 0x3 << 16); + clrsetbits32(&ch[chn].ao.dummy_rd, 0x3 << 16, 0x2 << 16); for (size_t r = 0; r < 2; r++) for (size_t i = 0; i < 4; i++) @@ -380,7 +378,7 @@ clrbits32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0); } - clrbits32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20); + setbits32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20); } static void dramc_set_CKE_2_rank_independent(u8 chn) @@ -421,46 +419,41 @@ void dramc_runtime_config(void) { - clrbits32(&ch[0].ao.refctrl0, 0x1 << 29); - clrbits32(&ch[1].ao.refctrl0, 0x1 << 29); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + clrbits32(&ch[chn].ao.refctrl0, 0x1 << 29); transfer_pll_to_spm_control(); setbits32(&mtk_spm->spm_power_on_val0, 0x1 << 25); - for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { dramc_hw_dqsosc(chn); /* RX_TRACKING: ON */ - for (u8 chn = 0; chn < CHANNEL_MAX; chn++) dramc_rx_input_delay_tracking(chn); /* HW_GATING: ON */ - dramc_hw_gating_init(); - dramc_hw_gating_onoff(CHANNEL_A, true); - dramc_hw_gating_onoff(CHANNEL_B, true); + dramc_hw_gating_init(chn); + dramc_hw_gating_onoff(chn, true); /* HW_GATING DBG: OFF */ - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) clrbits32(&ch[chn].ao.stbcal2, (0x3 << 4) | (0x3 << 8) | (0x1 << 28)); /* DUMMY_READ_FOR_TRACKING: ON */ - for (u8 chn = 0; chn < CHANNEL_MAX; chn++) dramc_dummy_read_for_tracking_enable(chn); /* ZQCS_ENABLE_LP4: ON */ - clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 30); - clrbits32(&ch[1].ao.spcmdctrl, 0x1 << 30); + clrbits32(&ch[chn].ao.spcmdctrl, 0x1 << 30); /* LOWPOWER_GOLDEN_SETTINGS(DCM): ON */ - dramc_phy_low_power_enable(); - dramc_enable_phy_dcm(true); + dramc_phy_low_power_enable(chn); + dramc_enable_phy_dcm(chn, true); /* DUMMY_READ_FOR_DQS_GATING_RETRY: OFF */ - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) clrbits32(&ch[chn].ao.shu[shu].dqsg_retry, (0x1 << 1) | (0x3 << 13)); + } /* SPM_CONTROL_AFTERK: ON */ write32(&ch[0].phy.misc_spm_ctrl0, 0xfbffefff); @@ -496,9 +489,10 @@ /* DRAM DRS DISABLE */ clrsetbits32(&ch[chn].ao.drsctrl, - (0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6), + (0x1 << 21) | (0x7f << 12) | (0xf << 8) | + (0x1 << 6) | (0x1 << 4)| (0x1 << 2), (0x1 << 19) | (0x3 << 12) | (0x8 << 8) | - (0x3 << 4) | (0x1 << 2) | (0x1 << 0)); + (0x1 << 5) | (0x1 << 2) | (0x1 << 0)); setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26); } dramc_dqs_precalculation_preset(); diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index f93214e..bdb14ee 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -286,18 +286,16 @@ dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref); } -static void dramc_read_dbi_onoff(bool on) +static void dramc_read_dbi_onoff(size_t chn, bool on) { - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - for (size_t b = 0; b < 2; b++) - SET32_BITFIELDS(&ch[chn].phy.shu[0].b[b].dq[7], - SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0, on); + for (size_t b = 0; b < 2; b++) + SET32_BITFIELDS(&ch[chn].phy.shu[0].b[b].dq[7], + SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0, on); } -static void dramc_write_dbi_onoff(bool onoff) +static void dramc_write_dbi_onoff(size_t chn, bool onoff) { - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - SET32_BITFIELDS(&ch[chn].ao.shu[0].wodt, SHU1_WODT_DBIWR, onoff); + SET32_BITFIELDS(&ch[chn].ao.shu[0].wodt, SHU1_WODT_DBIWR, onoff); } static void dramc_phy_dcm_2_channel(u8 chn, bool en) @@ -317,64 +315,61 @@ ((en ? 0x7 : 0) << 16) | ((en ? 0x7 : 0) << 20)); } -void dramc_enable_phy_dcm(bool en) +void dramc_enable_phy_dcm(u8 chn, bool en) { - for (size_t chn = 0; chn < CHANNEL_MAX ; chn++) { - clrbits32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20); - clrbits32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20); - clrbits32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20); - for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { - struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; - setbits32(&shu->b[0].dll[0], 0x1); - setbits32(&shu->b[1].dll[0], 0x1); - setbits32(&shu->ca_dll[0], 0x1); - } - - clrsetbits32(&ch[chn].ao.dramc_pd_ctrl, - (0x1 << 0) | (0x1 << 1) | (0x1 << 2) | - (0x1 << 5) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31), - ((en ? 0x1 : 0) << 0) | ((en ? 0x1 : 0) << 1) | - ((en ? 0x1 : 0) << 2) | ((en ? 0 : 0x1) << 5) | - ((en ? 0 : 0x1) << 26) | ((en ? 0x1 : 0) << 30) | - ((en ? 0x1 : 0) << 31)); - - /* DCM on: CHANNEL_EMI free run; DCM off: mem_dcm */ - write32(&ch[chn].phy.misc_cg_ctrl2, - 0x8060033e | (0x40 << (en ? 0x1 : 0))); - write32(&ch[chn].phy.misc_cg_ctrl2, - 0x8060033f | (0x40 << (en ? 0x1 : 0))); - write32(&ch[chn].phy.misc_cg_ctrl2, - 0x8060033e | (0x40 << (en ? 0x1 : 0))); - - clrsetbits32(&ch[chn].phy.misc_ctrl3, 0x3 << 26, - (en ? 0 : 0x3) << 26); - for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { - u32 mask = 0x7 << 17; - u32 value = (en ? 0x7 : 0) << 17; - struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; - - clrsetbits32(&shu->b[0].dq[7], mask, value); - clrsetbits32(&shu->b[1].dq[7], mask, value); - clrsetbits32(&shu->ca_cmd[7], mask, value); - } - - dramc_phy_dcm_2_channel(chn, en); + for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { + struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; + setbits32(&shu->b[0].dll[0], 0x1); + setbits32(&shu->b[1].dll[0], 0x1); + setbits32(&shu->ca_dll[0], 0x1); } + + clrsetbits32(&ch[chn].ao.dramc_pd_ctrl, + (0x1 << 0) | (0x1 << 1) | (0x1 << 2) | + (0x1 << 5) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31), + ((en ? 0x1 : 0) << 0) | ((en ? 0x1 : 0) << 1) | + ((en ? 0x1 : 0) << 2) | ((en ? 0 : 0x1) << 5) | + ((en ? 0 : 0x1) << 26) | ((en ? 0x1 : 0) << 30) | + ((en ? 0x1 : 0) << 31)); + + /* DCM on: CHANNEL_EMI free run; DCM off: mem_dcm */ + write32(&ch[chn].phy.misc_cg_ctrl2, + 0x8060033e | (0x40 << (en ? 0x1 : 0))); + write32(&ch[chn].phy.misc_cg_ctrl2, + 0x8060033f | (0x40 << (en ? 0x1 : 0))); + write32(&ch[chn].phy.misc_cg_ctrl2, + 0x8060033e | (0x40 << (en ? 0x1 : 0))); + + clrsetbits32(&ch[chn].phy.misc_ctrl3, 0x3 << 26, + (en ? 0 : 0x3) << 26); + for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { + u32 mask = 0x7 << 17; + u32 value = (en ? 0x7 : 0) << 17; + struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; + + clrsetbits32(&shu->b[0].dq[7], mask, value); + clrsetbits32(&shu->b[1].dq[7], mask, value); + clrsetbits32(&shu->ca_cmd[7], mask, value); + } + + dramc_phy_dcm_2_channel(chn, en); } -static void dramc_reset_delay_chain_before_calibration(void) +static void dramc_reset_delay_chain_before_calibration(size_t chn) { - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - for (size_t rank = 0; rank < RANK_MAX; rank++) { - struct dramc_ddrphy_regs_shu_rk *rk; - rk = &ch[chn].phy.shu[0].rk[rank]; - clrbits32(&rk->ca_cmd[0], 0xffffff << 0); - clrbits32(&rk->b[0].dq[0], 0xfffffff << 0); - clrbits32(&rk->b[1].dq[0], 0xfffffff << 0); - clrbits32(&rk->b[0].dq[1], 0xf << 0); - clrbits32(&rk->b[1].dq[1], 0xf << 0); - } + for (size_t rank = 0; rank < RANK_MAX; rank++) { + struct dramc_ddrphy_regs_shu_rk *rk; + rk = &ch[chn].phy.shu[0].rk[rank]; + clrbits32(&rk->ca_cmd[0], 0xffffff << 0); + clrbits32(&rk->b[0].dq[0], 0xfffffff << 0); + clrbits32(&rk->b[1].dq[0], 0xfffffff << 0); + clrbits32(&rk->b[0].dq[1], 0xf << 0); + clrbits32(&rk->b[1].dq[1], 0xf << 0); + } } void dramc_hw_gating_onoff(u8 chn, bool on) @@ -398,26 +393,26 @@ void dramc_apply_config_before_calibration(u8 freq_group) { - dramc_enable_phy_dcm(false); - dramc_reset_delay_chain_before_calibration(); - - setbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16); - setbits32(&ch[0].ao.spcmdctrl, 0x1 << 24); - clrsetbits32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1); - - for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - setbits32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0); - - clrbits32(&ch[0].ao.dramctrl, 0x1 << 18); - clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 31); - clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 30); - clrbits32(&ch[0].ao.dqsoscr, 0x1 << 26); - clrbits32(&ch[0].ao.dqsoscr, 0x1 << 25); - - dramc_write_dbi_onoff(false); - dramc_read_dbi_onoff(false); - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + dramc_enable_phy_dcm(chn, false); + dramc_reset_delay_chain_before_calibration(chn); + + setbits32(&ch[chn].ao.shu[0].conf[3], 0x1ff << 16); + setbits32(&ch[chn].ao.spcmdctrl, 0x1 << 24); + clrsetbits32(&ch[chn].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1); + + for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + setbits32(&ch[chn].ao.shu[shu].conf[3], 0x1ff << 0); + + clrbits32(&ch[chn].ao.dramctrl, 0x1 << 18); + clrbits32(&ch[chn].ao.spcmdctrl, 0x1 << 31); + clrbits32(&ch[chn].ao.spcmdctrl, 0x1 << 30); + clrbits32(&ch[chn].ao.dqsoscr, 0x1 << 26); + clrbits32(&ch[chn].ao.dqsoscr, 0x1 << 25); + + dramc_write_dbi_onoff(chn, false); + dramc_read_dbi_onoff(chn, false); + setbits32(&ch[chn].ao.spcmdctrl, 0x1 << 29); setbits32(&ch[chn].ao.dqsoscr, 0x1 << 24); for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) @@ -791,7 +786,6 @@ SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 0); SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMSTBENCMP_RK, rank); - } static void set_selph_gating_value(uint32_t *addr, u8 dly, u8 dly_p1) diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 4680a0e..cf1369e 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -64,6 +64,8 @@ struct optimize_ac_time { u8 rfc; u8 rfc_05t; + u8 rfc_pb; + u8 rfrc_pb05t; u16 tx_ref_cnt; }; @@ -324,19 +326,23 @@ static void dramc_ac_timing_optimize(u8 freq_group) { struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = { - [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62}, - [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .tx_ref_cnt = 91}, - [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .tx_ref_cnt = 119}, - [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .tx_ref_cnt = 138}, + [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .rfc_pb = 16, .rfrc_pb05t = 0, .tx_ref_cnt = 62}, + [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .rfc_pb = 30, .rfrc_pb05t = 0, .tx_ref_cnt = 91}, + [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .rfc_pb = 44, .rfrc_pb05t = 0, .tx_ref_cnt = 119}, + [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .rfc_pb = 53, .rfrc_pb05t = 1, .tx_ref_cnt = 138}, }; for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits32(&ch[chn].ao.shu[0].actim[3], 0xff << 16, rf_cab_opt[freq_group].rfc << 16); - clrbits32(&ch[chn].ao.shu[0].ac_time_05t, - rf_cab_opt[freq_group].rfc_05t << 2); - clrsetbits32(&ch[chn].ao.shu[0].actim[4], + clrsetbits_le32(&ch[chn].ao.shu[0].ac_time_05t, + 0x1 << 2, rf_cab_opt[freq_group].rfc_05t << 2); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], 0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], + 0xff << 0, rf_cab_opt[freq_group].rfc_pb << 0); + clrsetbits_le32(&ch[chn].ao.shu[0].ac_time_05t, + 0x1 << 1, rf_cab_opt[freq_group].rfrc_pb05t << 1); } } @@ -509,11 +515,11 @@ dfs_init_for_calibration(params, freq_group, shared); *first_run = false; - dramc_dbg("Start K (current clock: %u\n", params->frequency); + dramc_dbg("Start K current clock: %u\n", params->frequency); if (dramc_calibrate_all_channels(params, freq_group, &shared->mr) != 0) return -1; dramc_ac_timing_optimize(freq_group); - dramc_dbg("K finished (current clock: %u\n", params->frequency); + dramc_dbg("K finished current clock: %u\n", params->frequency); dramc_save_result_to_shuffle(DRAM_DFS_SHUFFLE_1, shuffle); return 0; diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index ea4f138..32df9e5 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -112,7 +112,7 @@ int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, const struct mr_value *mr); void dramc_hw_gating_onoff(u8 chn, bool onoff); -void dramc_enable_phy_dcm(bool bEn); +void dramc_enable_phy_dcm(u8 chn, bool bEn); void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off); void dramc_hw_dqsosc(u8 chn); -- To view, visit https://review.coreboot.org/c/coreboot/+/38490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea623d1bd1f7d736e81f66f191a1bf8476d30404 Gerrit-Change-Number: 38490 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

8 18

Change in coreboot[master]: soc/mediatek/mt8183: add TX tracking for DRAM DVFS
by huayang duan (Code Review) 06 Mar '20

06 Mar '20

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37996 ) Change subject: soc/mediatek/mt8183: add TX tracking for DRAM DVFS ...................................................................... soc/mediatek/mt8183: add TX tracking for DRAM DVFS use dqs osc to tracking the TX window for DVFS BUG=b:none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Idcf9213a488e795df3faf64b03588cfe55cb2f81 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_register.h 4 files changed, 296 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/37996/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 1eb86f4..c609128 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -419,6 +419,51 @@ } } +extern const u8 freq_shuffle[DRAM_DFS_SHUFFLE_MAX]; +extern const u8 freq_shuffle_emcp[DRAM_DFS_SHUFFLE_MAX]; +extern const u32 frequency_table[LP4X_DDRFREQ_MAX]; + +static void dramc_hw_dqs_osc(u8 chn) +{ + u32 freq_shu0, freq_shu1, freq_shu2; + const u8 *freq_tbl; + + if (CONFIG_MT8183_DRAM_EMCP) + freq_tbl = freq_shuffle_emcp; + else + freq_tbl = freq_shuffle; + + dramc_dbg("%s %d called!\n", __func__, __LINE__); + + freq_shu0 = frequency_table[freq_tbl[0]]; + freq_shu1 = frequency_table[freq_tbl[1]]; + freq_shu2 = frequency_table[freq_tbl[2]]; + + SET32_BITFIELDS(&ch[chn].ao.rk[2].dqsosc, RK2_DQSOSC_FREQ_RATIO_TX_0, (freq_shu1*8/freq_shu0)); + SET32_BITFIELDS(&ch[chn].ao.rk[2].dqsosc, RK2_DQSOSC_FREQ_RATIO_TX_1, (freq_shu2*8/freq_shu0)); + SET32_BITFIELDS(&ch[chn].ao.rk[2].dqsosc, RK2_DQSOSC_FREQ_RATIO_TX_3, (freq_shu0*8/freq_shu1)); + SET32_BITFIELDS(&ch[chn].ao.rk[2].dqsosc, RK2_DQSOSC_FREQ_RATIO_TX_4, (freq_shu2*8/freq_shu1)); + SET32_BITFIELDS(&ch[chn].ao.rk[2].dummy_rd_bk, RK2_DUMMY_RD_BK_FREQ_RATIO_TX_6, (freq_shu0*8/freq_shu2)); + SET32_BITFIELDS(&ch[chn].ao.rk[2].dummy_rd_bk, RK2_DUMMY_RD_BK_FREQ_RATIO_TX_7, (freq_shu1*8/freq_shu2)); + + SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0], PRE_TDQSCK1_SHU_PRELOAD_TX_HW, 1); + SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0], PRE_TDQSCK1_SHU_PRELOAD_TX_START, 0); + SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0], PRE_TDQSCK1_SW_UP_TX_NOW_CASE, 0); + + + SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPC_BLOCKALE_OPT, 0); + SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMARPIDQ_SW, 1); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_ARUIDQ_SW, 1); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 1); + + SET32_BITFIELDS(&ch[chn].ao.rk[0].dqsosc, RK0_DQSOSC_DQSOSCR_RK0EN, 1); + SET32_BITFIELDS(&ch[chn].ao.rk[1].dqsosc, RK1_DQSOSC_DQSOSCR_RK1EN, 1); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSC_CALEN, 1); + + for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + SET32_BITFIELDS(&ch[chn].ao.shu[shu].scintv, SHU_SCINTV_DQSOSCENDIS, 1); +} + void dramc_runtime_config(void) { clrbits32(&ch[0].ao.refctrl0, 0x1 << 29); @@ -427,6 +472,9 @@ transfer_pll_to_spm_control(); setbits32(&mtk_spm->spm_power_on_val0, 0x1 << 25); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + dramc_hw_dqs_osc(chn); + /* RX_TRACKING: ON */ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) dramc_rx_input_delay_tracking(chn); diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 0ec0193..2e5228d 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -105,6 +105,37 @@ CKECTRL_CKEFIXOFF, cke_off); } +static u16 dramc_mode_reg_read(u8 chn, u8 mr_idx) +{ + u16 value; + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSMA, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRREN, 1); + + /* Wait MRW command fired */ + while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRR_RESPONSE) + == 0) + udelay(1); + + value = READ32_BITFIELD(&ch[chn].nao.mrr_status, MRR_STATUS_MRR_REG); + + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRREN, 0); + dramc_dbg("Read MR%d =0x%x\n", mr_idx, value); + + return value; +} + +static u16 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) +{ + u16 value; + u32 mrs_bak = READ32_BITFIELD(&ch[chn].ao.mrs, MRS_MRSRK); + + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); + value = dramc_mode_reg_read(chn, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, mrs_bak); + + return value; +} + void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) { u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl); @@ -117,7 +148,7 @@ /* Wait MRW command fired */ while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRW_RESPONSE) == 0) - ; + udelay(1); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRWEN, 0); write32(&ch[chn].ao.ckectrl, ckectrl_bak); @@ -1577,17 +1608,9 @@ } } -static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, - struct win_perbit_dly *vref_dly, enum CAL_TYPE type, u8 freq_group, - u16 *tx_dq_precal_result, u16 dly_cell_unit, const struct sdram_params *params, - const bool fast_calib) +static u32 get_freq_group_clock(u8 freq_group) { - int index, clock_rate; - u8 use_delay_cell; - u32 byte_dly_cell[DQS_NUMBER] = {0}; - struct per_byte_dly center_dly[DQS_NUMBER]; - u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH]; - + u32 clock_rate = 0; /* * The clock rate is usually (frequency / 2 - delta), where the delta @@ -1609,8 +1632,23 @@ break; default: die("Invalid DDR frequency group %u\n", freq_group); - return; + break; } + return clock_rate; +} + +static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, + struct win_perbit_dly *vref_dly, enum CAL_TYPE type, u8 freq_group, + u16 *tx_dq_precal_result, u16 dly_cell_unit, const struct sdram_params *params, + const bool fast_calib) +{ + int index, clock_rate; + u8 use_delay_cell; + u32 byte_dly_cell[DQS_NUMBER] = {0}; + struct per_byte_dly center_dly[DQS_NUMBER]; + u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH]; + + clock_rate = get_freq_group_clock(freq_group); if (type == TX_WIN_DQ_ONLY && get_freq_fsq(freq_group) == FSP_1) use_delay_cell = 1; @@ -2104,6 +2142,152 @@ (0xff << 8) | (0x9 << 2) | ROEN); } +static void start_dqs_osc(u8 chn) +{ + u32 loop = 0; + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSOSCENEN, 1); + while (!wait_us(10, read32(&ch[chn].nao.spcmdresp) & (0x1 << 10))) { + if (loop++ > 10) + dramc_err("start DQSOSC fail (time out)\n"); + return; + } + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSOSCENEN, 0); +} + +static void dqs_osc_set(u8 chn, u8 rank, u8 freq_group) +{ + u8 mr23 = 0x3F; + u16 mr18, mr19; + u16 dqs_osc_cnt[2]; + + struct reg_value regs_bak[] = { + {&ch[chn].ao.mrs}, + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].ao.ckectrl}, + }; + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + dramc_dbg("%s %d called!\n", __func__, __LINE__); + + SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_DQSOSC2RK, 0); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); + SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); + dramc_mode_reg_write(chn, 23, mr23); + + for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + SET32_BITFIELDS(&ch[chn].ao.shu[shu].scintv, SHU_SCINTV_DQSOSCENDIS, 1); + + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_MIOCKCTRLOFF, 1); + dramc_cke_fix_onoff(chn, true, false); + + start_dqs_osc(chn); + udelay(1); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rank); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + + mr18 = dramc_mode_reg_read(chn, 18); + mr19 = dramc_mode_reg_read(chn, 19); + dqs_osc_cnt[0] = (mr18 & 0xFF) | ((mr19 & 0xFF) << 8); + dqs_osc_cnt[1] = (mr18 >> 8) | (mr19 & 0xFF00); + dramc_dbg("DQSOscCnt B0=0x%X, B1=0x%X\n", dqs_osc_cnt[0] , dqs_osc_cnt[1]); + + SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[rank].dqsosc, + SHU1RK0_DQSOSC_DQSOSC_BASE_RK0, dqs_osc_cnt[0]); + SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[rank].dqsosc, + SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1, dqs_osc_cnt[1]); +} + +static void dqs_osc_shu_settings(u8 chn, u8 freq_group) +{ + u8 filt_pithrd, w2r_sel, upd_sel; + u8 mr23 = 0x3F; + u16 mr18, mr19; + u16 dqs_cnt, dqs_osc, prd_cnt, thrd_inc, thrd_dec; + u32 clock_rate, tck; + + SET32_BITFIELDS(&ch[chn].ao.shu[0].scintv, SHU_SCINTV_DQS2DQ_SHU_PITHRD, 0); + SET32_BITFIELDS(&ch[chn].ao.rk[0].dqsosc, RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT, 0); + + switch (freq_group) { + case LP4X_DDR1600: + filt_pithrd = 0x5; + w2r_sel = 0x5; + upd_sel = 0x0; + break; + case LP4X_DDR2400: + filt_pithrd = 0x8; + w2r_sel = 0x2; + upd_sel = 0x0; + break; + case LP4X_DDR3200: + filt_pithrd = 0xA; + w2r_sel = 0x2; + upd_sel = 0x0; + break; + case LP4X_DDR3600: + filt_pithrd = 0xB; + w2r_sel = 0x2; + upd_sel = 0x0; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + dramc_dbg("%s %d called!\n", __func__, __LINE__); + + SET32_BITFIELDS(&ch[chn].ao.shu[0].scintv, SHU_SCINTV_DQS2DQ_FILT_PITHRD, filt_pithrd); + SET32_BITFIELDS(&ch[chn].ao.shu[0].wodt, SHU1_WODT_TXUPD_W2R_SEL, w2r_sel); + SET32_BITFIELDS(&ch[chn].ao.shu[0].wodt, SHU1_WODT_TXUPD_SEL, upd_sel); + + prd_cnt = mr23 / 4 + 3; + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsosc_prd, SHU1_DQSOSC_PRD_DQSOSC_PRDCNT, prd_cnt); + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscr, SHU_DQSOSCR_DQSOSCRCNT, 0x40); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + mr18 = dramc_mode_reg_read_by_rank(chn, rk, 18); + mr19 = dramc_mode_reg_read_by_rank(chn, rk, 19); + + clock_rate = get_freq_group_clock(freq_group); + tck = 1000000 /clock_rate; + + dqs_cnt = (mr18 & 0xFF) | ((mr19 & 0xFF) <<8); + if (dqs_cnt != 0) { + dqs_osc = mr23*16 *1000000 / (2 * dqs_cnt * clock_rate); + thrd_inc = (mr23 * tck * tck) / (dqs_osc * dqs_osc * 10); + thrd_dec = (3 * mr23 * tck * tck) / (dqs_osc * dqs_osc * 20); + } else { + dqs_osc = 0; + thrd_inc = 0x6; + thrd_dec = 0x4; + } + + dramc_dbg("CH%d_RK%d: MR19=0x%x, MR18=0x%x, DQSOSC=%d, MR23=0x%x, INC=%d, DEC=%d\n", + chn, rk, mr18, mr19, dqs_cnt, mr23, thrd_inc, thrd_dec); + + if (rk == RANK_0) { + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscthrd, + SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0, thrd_inc); + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscthrd, + SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0, thrd_dec); + } else { + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscthrd, + SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0, + thrd_inc & 0xFF); + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsosc_prd, + SHU1_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8, + (thrd_inc & 0xF00) >> 8); + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsosc_prd, + SHU1_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1, thrd_dec); + } + } + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscr2, SHU_DQSOSCR2_DQSOSCENCNT, 0x1FF); + dramc_dbg("%s %d called!\n", __func__, __LINE__); +} + int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, const struct mr_value *mr) { @@ -2146,8 +2330,11 @@ dramc_window_perbit_cal(chn, rk, freq_group, RX_WIN_TEST_ENG, pams, fast_calib); dramc_auto_refresh_switch(chn, false); + + dqs_osc_set(chn, rk, freq_group); } + dqs_osc_shu_settings(chn, freq_group); dramc_rx_dqs_gating_post_process(chn, freq_group); dramc_dual_rank_rx_datlat_cal(chn, freq_group, rx_datlat[0], rx_datlat[1]); } diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index cf104f8..3755d2b 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -22,19 +22,19 @@ #include <soc/mt6358.h> #include <soc/spm.h> -static const u8 freq_shuffle[DRAM_DFS_SHUFFLE_MAX] = { +const u8 freq_shuffle[DRAM_DFS_SHUFFLE_MAX] = { [DRAM_DFS_SHUFFLE_1] = LP4X_DDR3200, [DRAM_DFS_SHUFFLE_2] = LP4X_DDR2400, [DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600, }; -static const u8 freq_shuffle_emcp[DRAM_DFS_SHUFFLE_MAX] = { +const u8 freq_shuffle_emcp[DRAM_DFS_SHUFFLE_MAX] = { [DRAM_DFS_SHUFFLE_1] = LP4X_DDR3600, [DRAM_DFS_SHUFFLE_2] = LP4X_DDR3200, [DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600, }; -u32 frequency_table[LP4X_DDRFREQ_MAX] = { +const u32 frequency_table[LP4X_DDRFREQ_MAX] = { [LP4X_DDR1600] = 1600, [LP4X_DDR2400] = 2400, [LP4X_DDR3200] = 3200, diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index b3ee6af..38e1bb2 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -627,12 +627,17 @@ check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800); DEFINE_BITFIELD(MISC_STATUSA_REFRESH_QUEUE_CNT, 27, 24) +DEFINE_BIT(SPCMDRESP_MRR_RESPONSE, 0) DEFINE_BIT(SPCMDRESP_MRW_RESPONSE, 0) +DEFINE_BITFIELD(MRR_STATUS_MRR_REG, 15, 0) DEFINE_BIT(DDRCONF0_DM4TO1MODE, 22) DEFINE_BIT(DDRCONF0_RDATRST, 0) DEFINE_BIT(PERFCTL0_RWOFOEN, 4) +DEFINE_BIT(RKCFG_DQSOSC2RK, 11) +DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 26) + DEFINE_BIT(PADCTRL_DQIENLATEBEGIN, 3) DEFINE_BITFIELD(PADCTRL_DQIENQKEND, 1, 0) @@ -655,16 +660,21 @@ DEFINE_BITFIELD(MRS_MRSMA, 20, 8) DEFINE_BITFIELD(MRS_MRSOP, 7, 0) +DEFINE_BIT(SPCMD_DQSOSCENEN, 10) DEFINE_BIT(SPCMD_DQSGCNTRST, 9) DEFINE_BIT(SPCMD_DQSGCNTEN, 8) DEFINE_BIT(SPCMD_ZQLATEN, 6) DEFINE_BIT(SPCMD_RDDQCEN, 7) DEFINE_BIT(SPCMD_ZQCEN, 4) +DEFINE_BIT(SPCMD_MRREN, 0) DEFINE_BIT(SPCMD_MRWEN, 0) DEFINE_BIT(SPCMDCTRL_RDDQCDIS, 11) DEFINE_BIT(MPC_OPTION_MPCRKEN, 17) +DEFINE_BIT(MPC_OPTION_MPC_BLOCKALE_OPT, 0) + + DEFINE_BIT(DVFSDLL_R_BYPASS_1ST_DLL_SHU1, 1) @@ -727,7 +737,41 @@ DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL, 23, 20) DEFINE_BIT(SHU1_WODT_DBIWR, 29) +DEFINE_BIT(SHU_SCINTV_DQSOSCENDIS, 30) +DEFINE_BITFIELD(SHU_SCINTV_DQS2DQ_SHU_PITHRD, 23, 18) DEFINE_BITFIELD(SHURK_DQSCTL_DQSINCTL, 3, 0) +DEFINE_BIT(RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT, 29) +DEFINE_BIT(RK0_DQSOSC_DQSOSCR_RK0EN, 30) +DEFINE_BIT(RK1_DQSOSC_DQSOSCR_RK1EN, 30) + +DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_0, 4, 0) +DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_1, 9, 5) +DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_3, 19, 15) +DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_4, 24, 20) +DEFINE_BITFIELD(RK2_DUMMY_RD_BK_FREQ_RATIO_TX_6, 7, 3) +DEFINE_BITFIELD(RK2_DUMMY_RD_BK_FREQ_RATIO_TX_7, 12, 8) + +DEFINE_BIT(PRE_TDQSCK1_SW_UP_TX_NOW_CASE, 16) +DEFINE_BIT(PRE_TDQSCK1_SHU_PRELOAD_TX_START, 18) +DEFINE_BIT(PRE_TDQSCK1_SHU_PRELOAD_TX_HW, 19) + + +DEFINE_BITFIELD(SHU_SCINTV_DQS2DQ_FILT_PITHRD, 29, 24) +DEFINE_BITFIELD(SHU1_WODT_TXUPD_W2R_SEL, 16, 14) +DEFINE_BITFIELD(SHU1_WODT_TXUPD_SEL, 13, 12) +DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSC_PRDCNT, 9, 0) +DEFINE_BITFIELD(SHU_DQSOSCR_DQSOSCRCNT, 7, 0) +DEFINE_BIT(DQSOSCR_ARUIDQ_SW, 7) +DEFINE_BIT(DQSOSCR_DQSOSCRDIS, 24) +DEFINE_BIT(DQSOSCR_DQSOSC_CALEN, 31) + + +DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0, 11, 0) +DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0, 23, 12) +DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0, 31, 24) +DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8, 19, 16) +DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1, 31, 20) +DEFINE_BITFIELD(SHU_DQSOSCR2_DQSOSCENCNT, 8, 0) DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1, 14, 12) DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1, 6, 4) @@ -736,6 +780,8 @@ DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS1_GATED_P1, 14, 12) DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED_P1, 6, 4) DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED, 2, 0) +DEFINE_BITFIELD(SHU1RK0_DQSOSC_DQSOSC_BASE_RK0, 15, 0) +DEFINE_BITFIELD(SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1, 31, 16) DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16) DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16) -- To view, visit https://review.coreboot.org/c/coreboot/+/37996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcf9213a488e795df3faf64b03588cfe55cb2f81 Gerrit-Change-Number: 37996 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

9 38

Change in coreboot[master]: soc/mediatek/mt8183: Set correct threshold of EMI bandwidth for DVFS
by huayang duan (Code Review) 06 Mar '20

06 Mar '20

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39034 ) Change subject: soc/mediatek/mt8183: Set correct threshold of EMI bandwidth for DVFS ...................................................................... soc/mediatek/mt8183: Set correct threshold of EMI bandwidth for DVFS The threshold of EMI bandwidth should have difference setting for discrete and EMCP DDR, because the discrete DDR and EMCP DDR have different DVFS tables. BRANCH=kukui BUG=none TEST=bootup pass Change-Id: I82c3c70bcd90df3fdd613c0353aba0f176bc82bc Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/39034/1 diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index cf104f8..7e535dc 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -299,8 +299,10 @@ setbits32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4); setbits32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4); - - write32(&emi_regs->bwct0, 0x0a000705); + if (CONFIG_MT8183_DRAM_EMCP) + write32(&emi_regs->bwct0, 0x0d000705); + else + write32(&emi_regs->bwct0, 0x0a000705); write32(&emi_regs->bwct0_3rd, 0x0); /* EMI QoS 0.5 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82c3c70bcd90df3fdd613c0353aba0f176bc82bc Gerrit-Change-Number: 39034 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: mb/up/squared: move USB config to device tree
by Patrick Georgi (Code Review) 06 Mar '20

06 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39134 ) Change subject: mb/up/squared: move USB config to device tree ...................................................................... mb/up/squared: move USB config to device tree Change-Id: Ic4db37112e7b2329f9e4885139deca12557ffe3a Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39134 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/up/squared/devicetree.cb M src/mainboard/up/squared/ramstage.c 2 files changed, 14 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index 66be75c..d7281a6 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -1,5 +1,19 @@ chip soc/intel/apollolake + # Override USB port configuration + register "usb_config_override" = "1" + # USB 2.0 + register "usb2_port[0]" = "PORT_EN(OC0)" + register "usb2_port[1]" = "PORT_EN(OC1)" + register "usb2_port[2]" = "PORT_EN(OC1)" + register "usb2_port[3]" = "PORT_EN(OC1)" + register "usb2_port[4]" = "PORT_EN(OC1)" + register "usb2_port[5]" = "PORT_EN(OC1)" + register "usb2_port[6]" = "PORT_EN(OC_SKIP)" + register "usb2_port[7]" = "PORT_EN(OC_SKIP)" + # USB 3.0 + register "usb3_port[0]" = "PORT_EN(OC0)" + register "enable_vtd" = "1" device cpu_cluster 0 on diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c index 637b8d8..9ae30eb 100644 --- a/src/mainboard/up/squared/ramstage.c +++ b/src/mainboard/up/squared/ramstage.c @@ -80,14 +80,4 @@ silconfig->PcieRpTransmitterHalfSwing[5] = 0x0; // 0x1 silconfig->PcieRpLtrMaxNonSnoopLatency[5] = 0x1003; // 0x0 silconfig->PcieRpLtrMaxSnoopLatency[5] = 0x1003; // 0x0 - - silconfig->PortUs30bOverCurrentPin[0] = 0x0; // 0x1 - - silconfig->PortUs20bOverCurrentPin[1] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[2] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[3] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[4] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[5] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[6] = 0x2; // 0x0 - silconfig->PortUs20bOverCurrentPin[7] = 0x2; // 0x0 } -- To view, visit https://review.coreboot.org/c/coreboot/+/39134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4db37112e7b2329f9e4885139deca12557ffe3a Gerrit-Change-Number: 39134 Gerrit-PatchSet: 10 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/up/squared: remove NpkEn option from romstage
by Patrick Georgi (Code Review) 06 Mar '20

06 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39120 ) Change subject: mb/up/squared: remove NpkEn option from romstage ...................................................................... mb/up/squared: remove NpkEn option from romstage There is no need to set the NpkEn option to disable the NPK device, since it has already been done in the devicetree. Change-Id: I429f1129dc4149067503cd2ff9fb4c76cdc919f0 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39120 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/up/squared/romstage.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c index f9f0cfc..55235a8 100644 --- a/src/mainboard/up/squared/romstage.c +++ b/src/mainboard/up/squared/romstage.c @@ -169,7 +169,6 @@ config->RmtCheckRun = 0x3; // 0x0 config->RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 config->EnhancePort8xhDecoding = 0x0; // 0x1 - config->NpkEn = 0x0; // 0x3 config->PrimaryVideoAdaptor = 0x2; // 0x0 config->Ch0_DeviceWidth = 0x1; // 0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/39120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I429f1129dc4149067503cd2ff9fb4c76cdc919f0 Gerrit-Change-Number: 39120 Gerrit-PatchSet: 12 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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