coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake
by caveh jalali (Code Review) 06 Mar '20

06 Mar '20

caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39364 ) Change subject: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d Gerrit-Change-Number: 39364 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Sat, 07 Mar 2020 00:50:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake
by Wonkyu Kim (Code Review) 06 Mar '20

06 Mar '20

Wonkyu Kim has uploaded a new patch set (#2) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/39364 ) Change subject: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake ...................................................................... vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake Update FSPS header to include HybridStorageMode Upd for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 1 file changed, 16 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39364/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d Gerrit-Change-Number: 39364 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake
by Srinidhi N Kaushik (Code Review) 06 Mar '20

06 Mar '20

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39364 ) Change subject: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d Gerrit-Change-Number: 39364 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Fri, 06 Mar 2020 23:48:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: modify and add soe devicetree settings
by Nick Vaccaro (Code Review) 06 Mar '20

06 Mar '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39338 ) Change subject: mb/google/volteer: modify and add soe devicetree settings ...................................................................... mb/google/volteer: modify and add soe devicetree settings - add sdcard_cd_gpio - remove support for PCIE WLAN to allow WWAN to enumerate as USB - mark PcieClkSrcUsage[2] as unused - add HD Audio support - set TcssXhciEn to 1 for TCSS USB3 - add acpi info for cros-ec-spi BUG=b:148385924, b:144933687, b:148179954 TEST=emerge-volteer coreboot chromeos-bootimage, flash to ripto and verify ripto boots to kernel. Change-Id: I998a237a4a2587554a4f84d5625da2dfca2dc56e Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 31 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39338/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b9ed424..ab50458 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -50,18 +50,15 @@ register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" + register "sdcard_cd_gpio" = "GPP_E11" # Enable WLAN PCIE 7 using clk 1 register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" - # Enable WWAN PCIE 6 using clk 2 - register "PcieRpEnable[5]" = "1" - register "PcieClkSrcUsage[2]" = "5" - register "PcieClkSrcClkReq[2]" = "2" - # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality + register "PcieClkSrcUsage[2]" = "0xFF" register "PcieClkSrcUsage[4]" = "0xFF" register "PcieClkSrcUsage[5]" = "0xFF" register "PcieClkSrcUsage[6]" = "0xFF" @@ -110,6 +107,23 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[0]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + + # TCSS USB3 + register "TcssXhciEn" = "1" + # DP port register "DdiPortAConfig" = "1" # eDP register "DdiPortBConfig" = "0" @@ -153,7 +167,7 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | - #| GSPI1 | Fingerprint MCU + #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | #| I2C1 | Touchscreen | #| I2C2 | WLAN, SAR0 | @@ -303,7 +317,7 @@ device pci 1c.2 off end # RP3 0xA0BA device pci 1c.3 off end # RP4 0xA0BB device pci 1c.4 off end # RP5 0xA0BC - device pci 1c.5 on end # WWAN RP6 0xA0BD + device pci 1c.5 off end # WWAN RP6 0xA0BD device pci 1c.6 on end # RP7 0xA0BE device pci 1c.7 on end # SD Card RP8 0xA0BF @@ -326,7 +340,16 @@ device spi 0 on end end end # GSPI0 0xA0AA - device pci 1e.3 on end # GSPI1 0xA0AB + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" + device spi 0 on end + end # FPMCU + end # GSPI1 0xA0AB device pci 1f.0 on end # eSPI 0xA080 - A09F device pci 1f.1 off end # P2SB 0xA0A0 -- To view, visit https://review.coreboot.org/c/coreboot/+/39338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I998a237a4a2587554a4f84d5625da2dfca2dc56e Gerrit-Change-Number: 39338 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: add sdcard_cd_gpio export to devicetree
by Nick Vaccaro (Code Review) 06 Mar '20

06 Mar '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39355 ) Change subject: mb/google/volteer: add sdcard_cd_gpio export to devicetree ...................................................................... mb/google/volteer: add sdcard_cd_gpio export to devicetree BUG=b:148385924 TEST=none Change-Id: I76f4fbc6d6771bebf55c96a97fbafa1cdbcd2bbd Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/39355/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index f2196df..d44975f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -50,6 +50,7 @@ register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" + register "sdcard_cd_gpio" = "GPP_E11" # Enable WLAN PCIE 7 using clk 1 register "PcieRpEnable[6]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/39355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76f4fbc6d6771bebf55c96a97fbafa1cdbcd2bbd Gerrit-Change-Number: 39355 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/arch/x86:Add support for low power idle table
by Shaunak Saha (Code Review) 06 Mar '20

06 Mar '20

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 4: (14 comments) https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@7 PS4, Line 7: src/arch/x86:Add > 1. `src/` not needed. […] Ack https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@7 PS4, Line 7: low power idle table > Use LPIT here, and the full name in the commit message body. Ack https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@9 PS4, Line 9: residency.Residencies > Space after . Ack https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@13 PS4, Line 13: CPU PKG C10 (Read via FFH interface) : Platform Controller Hub (PCH) SLP_S0 (Read via memory mapped interface) > Please add blank lines around, and format it as a list. Ack https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@17 PS4, Line 17: /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us : /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us > Please indent with four spaces, and add blank lines around the block. Ack https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@21 PS4, Line 21: The “low_power_idle_system_residency_us” attribute shows SLP_S0 residency, or > Please add a blank line above to separate paragraphs visually. Ack https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@26 PS4, Line 26: Example: > Please add a blank line above. Ack https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@28 PS4, Line 28: thet > that Ack https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@31 PS4, Line 31: elected > selected Ack https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@31 PS4, Line 31: thet > that Ack https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c File src/arch/x86/acpi.c: https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1244 PS4, Line 1244: * implementation specific.e.e.g, scenerios: > no need for SoC comments in arch/x86. Ack https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1253 PS4, Line 1253: __weak void soc_residency_counter(struct acpi_lpit_native *lpit_native) > no need for weak, code will be removed if not CONFIG(ACPI_LPIT) Ack https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1275 PS4, Line 1275: header->asl_compiler_revision = 0; > header->asl_compiler_revision = asl_revision; Ack https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1278 PS4, Line 1278: lpit->lpit_native.header.type = 0; > already cleared by memset Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 4 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Mar 2020 19:25:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: util/autoport: Remove redundant comment
by Angel Pons (Code Review) 06 Mar '20

06 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39298 ) Change subject: util/autoport: Remove redundant comment ...................................................................... util/autoport: Remove redundant comment Nobody needs "LPC bridge PCI-LPC bridge". Change-Id: Iac833d4fa34b00d89bdfc9aeb06a96583840b900 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/bd82x6x.go 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39298/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 3ad212b..87e7584 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -277,7 +277,7 @@ } PutPCIChip(addr, cur) - PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + PutPCIDevParent(addr, "", "lpc") DSDTIncludes = append(DSDTIncludes, DSDTInclude{ File: "southbridge/intel/common/acpi/platform.asl", -- To view, visit https://review.coreboot.org/c/coreboot/+/39298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac833d4fa34b00d89bdfc9aeb06a96583840b900 Gerrit-Change-Number: 39298 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Configure unused GPIOs
by Karthik Ramasubramanian (Code Review) 06 Mar '20

06 Mar '20

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39323 to review the following change. Change subject: mb/google/dedede: Configure unused GPIOs ...................................................................... mb/google/dedede: Configure unused GPIOs Configure unused GPIOs as not connected. BUG=None TEST=Build and boot the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I49886aefc53818a48d0a20210b2739a4fec55e02 --- M src/mainboard/google/dedede/variants/baseboard/gpio.c 1 file changed, 37 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/39323/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 7b1a9e2..cfa7d54 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -22,11 +22,11 @@ /* A5 : ESPI_CLK */ /* A6 : ESPI_RESET_L */ /* A7 : SMB_CLK */ - PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_NC(GPP_A7, NONE), /* A8 : SMB_DATA */ - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_NC(GPP_A8, NONE), /* A9 : SMB_ALERT_N */ - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_NC(GPP_A9, NONE), /* A10 : WWAN_EN */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* A11 : TOUCH_RPT_EN */ @@ -46,7 +46,7 @@ /* A18 : USB_OC0_N */ PAD_NC(GPP_A18, NONE), /* A19 : PCHHOT_N */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_NC(GPP_A19, NONE), /* B0 : VCCIN_AUX_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), @@ -59,25 +59,25 @@ /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), /* B5 : PCIE_CLKREQ0_N */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_NC(GPP_B5, NONE), /* B6 : PCIE_CLKREQ1_N */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_NC(GPP_B6, NONE), /* B7 : PCIE_CLKREQ2_N */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* B8 : PCIE_CLKREQ3_N */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* B9 : PCIE_CLKREQ4_N */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_NC(GPP_B9, NONE), /* B10 : PCIE_CLKREQ5_N */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + PAD_NC(GPP_B10, NONE), /* B11 : PMCALERT_N */ - PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + PAD_NC(GPP_B11, NONE), /* B12 : AP_SLP_S0_L */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR/GSPI0_CS1_N */ - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + PAD_NC(GPP_B14, NONE), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -87,13 +87,13 @@ /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* B19 : GSPI1_CS0_N */ - PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK */ - PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO */ - PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI */ - PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + PAD_NC(GPP_B22, NONE), /* B23 : EC_AP_USB_C1_HDMI_HPD */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), @@ -110,9 +110,9 @@ /* C5 : RAM_STRAP_3 */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* C6 : PMC_SUSWARN_N */ - PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + PAD_NC(GPP_C6, NONE), /* C7 : PMC_SUSACK_N */ - PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + PAD_NC(GPP_C7, NONE), /* C8 : GPP_C8/UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* C9 : GPP_C9/UART0_TXD */ @@ -202,31 +202,31 @@ /* E2 : CLK_24M_WCAM */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* E3 : GPP_E3/SATA_0_DEVSLP */ - PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), + PAD_NC(GPP_E3, NONE), /* E4 : IMGCLKOUT_2 */ - PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), + PAD_NC(GPP_E4, NONE), /* E5 : AP_SUB_IO_2 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* E6 : GPP_E6/IMGCLKOUT_3 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* E7 : GPP_E7/SATA_1_DEVSLP */ - PAD_CFG_NF(GPP_E7, NONE, DEEP, NF1), + PAD_NC(GPP_E7, NONE), /* E8 : GPP_E8/SATA_0_GP */ - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_NC(GPP_E8, NONE), /* E9 : GPP_E9/SML_CLK0/SATA_1_GP */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_NC(GPP_E9, NONE), /* E10 : GPP_E10/SML_DATA0 */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_NC(GPP_E10, NONE), /* E11 : AP_I2C_SUB_INT_ODL */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* E12 : GPP_E12/IMGCLKOUT_4 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* E13 : GPP_E13/DDI0_DDC_SCL */ - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_NC(GPP_E13, NONE), /* E14 : GPP_E14/DDI0_DDC_SDA */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : GPP_E15/DDI1_DDC_SCL */ - PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + PAD_NC(GPP_E15, NONE), /* E16 : GPP_E16/DDI1_DDC_SDA */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), /* E17 : HDMI_DDC_SCL */ @@ -234,7 +234,7 @@ /* E18 : HDMI_DDC_SDA */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* E19 : GPP_E19/IMGCLKOUT_5/PCIE_LNK_DOWN */ - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + PAD_NC(GPP_E19, NONE), /* E20 : CNV_BRI_DT_R */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* E21 : CNV_BRI_RSP */ @@ -287,7 +287,7 @@ /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_SDIO_WP */ - PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), + PAD_NC(GPP_G7, NONE), /* H0 : WWAN_PERST */ PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), @@ -296,7 +296,7 @@ /* H2 : CNV_CLKREQ0 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* H3 : GPP_H03/SX_EXIT_HOLDOFF_N */ - PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_NC(GPP_H3, NONE), /* H4 : AP_I2C_TS_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : AP_I2C_TS_SCL */ @@ -312,13 +312,13 @@ /* H10 : CPU_C10_GATE_L */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), /* H11 : GPP_H11/AV_I2S2_SCLK */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_NC(GPP_H11, NONE), /* H12 : GPP_H12/AVS_I2S2_SFRM/CNF_RF_RESET_N */ - PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), + PAD_NC(GPP_H12, NONE), /* H13 : GPP_H13/AVS_I2S2_TXD/MODEM_CLKREQ */ - PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + PAD_NC(GPP_H13, NONE), /* H14 : GPP_H14/AVS_I2S2_RXD */ - PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_NC(GPP_H14, NONE), /* H15 : I2S_SPK_BCLK */ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* H16 : AP_SUB_IO_L */ @@ -339,9 +339,9 @@ /* R3 : I2S_HP_MIC */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1), /* R4 : GPP_R04/HDA_RST_N */ - PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + PAD_NC(GPP_R4, NONE), /* R5 : GPP_R05/HDA_SDI1/AVS_I2S1_RXD */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1), + PAD_NC(GPP_R5, NONE), /* R6 : I2S_SPK_LRCK */ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1), /* R7 : I2S_SPK_AUDIO */ @@ -356,9 +356,9 @@ /* S3 : DMIC1_DATA */ PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), /* S4 : GPP_S04/SNDW1_CLK */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + PAD_NC(GPP_S4, NONE), /* S5 : GPP_S05/SNDW1_DATA */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + PAD_NC(GPP_S5, NONE), /* S6 : DMIC0_CLK */ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), /* S7 : DMIC0_DATA */ @@ -383,9 +383,9 @@ /* GPD8 : WLAN_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9 : AP_SLP_WLAN_L */ - PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + PAD_NC(GPD9, NONE), /* GPD10 : AP_SLP_S5_L */ - PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + PAD_NC(GPD10, NONE), }; /* Early pad configuration in bootblock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49886aefc53818a48d0a20210b2739a4fec55e02 Gerrit-Change-Number: 39323 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/libretrend/lt1000: Add Libretrend LT1000 board support
by Angel Pons (Code Review) 06 Mar '20

06 Mar '20

1 0

Change in coreboot[master]: mb/libretrend/lt1000: Add Libretrend LT1000 board support
by Angel Pons (Code Review) 06 Mar '20

06 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: mb/libretrend/lt1000: Add Libretrend LT1000 board support ...................................................................... Patch Set 15: (8 comments) https://review.coreboot.org/c/coreboot/+/30360/15/Documentation/mainboard/l… File Documentation/mainboard/libretrend/lt1000.md: https://review.coreboot.org/c/coreboot/+/30360/15/Documentation/mainboard/l… PS15, Line 34: Strongly advised to *It is* strongly advised to ... https://review.coreboot.org/c/coreboot/+/30360/15/Documentation/mainboard/l… PS15, Line 35: possessing the having an https://review.coreboot.org/c/coreboot/+/30360/15/Documentation/mainboard/l… PS15, Line 41: between the DIMM slots and the M.2 disk Right, I think I see it. 😄 https://review.coreboot.org/c/coreboot/+/30360/15/src/mainboard/libretrend/… File src/mainboard/libretrend/lt1000/acpi/mainboard.asl: PS15: I don't think we need this file https://review.coreboot.org/c/coreboot/+/30360/15/src/mainboard/libretrend/… File src/mainboard/libretrend/lt1000/bootblock.c: https://review.coreboot.org/c/coreboot/+/30360/15/src/mainboard/libretrend/… PS15, Line 14: #define SERIAL1_DEV PNP_DEV(0x2e, IT8786E_SP1) Where is SERIAL2_DEV ? https://review.coreboot.org/c/coreboot/+/30360/15/src/mainboard/libretrend/… File src/mainboard/libretrend/lt1000/devicetree.cb: https://review.coreboot.org/c/coreboot/+/30360/15/src/mainboard/libretrend/… PS15, Line 241: "THERMAL_MODE_DISABLED" Should fit on the previous line https://review.coreboot.org/c/coreboot/+/30360/15/src/mainboard/libretrend/… PS15, Line 254: LVDS backlight control? https://review.coreboot.org/c/coreboot/+/30360/15/src/mainboard/libretrend/… File src/mainboard/libretrend/lt1000/dsdt.asl: https://review.coreboot.org/c/coreboot/+/30360/15/src/mainboard/libretrend/… PS15, Line 31: #include "acpi/mainboard.asl" We don't need this -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Mar 2020 18:12:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2020