Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Angel Pons, Andrey Petrov, Patrick Rudolph, Aaron Durbin, Lance Zhao, Nico Huber, Martin Roth, Werner Zeh, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39133
to look at the new patch set (#12).
Change subject: mb/kontron/mal10: Add COMe-mAL10 minimal support
......................................................................
mb/kontron/mal10: Add COMe-mAL10 minimal support
This patch adds minimal support for the Kontron COMe-mAL10 module with
the Apollo Lake processor together with Kontron T10-TNI carrierboard.
Working:
- console (Kontron CPLD)
- USB2/3
- Ethernet network
- eMMC
- SATA
- PCIe ports
- Video/DP (*)
Not tested:
- Video/LVDS
TODO:
- HDA (codec IDT 92HD73C1X5, currently disabled)
- SDIO
- Documentation
As the payload was used:
- Tianocore (*)(**)
- SeaBIOS (*)
(*) Video works only in linux
(**) Works only with Tianocore "UEFIPayload" payload
edk2-stable201903-1569-g3e63a91
(**) Booting with the "CorebootPayload" crashes:
https://pastebin.com/cpCfrPCL
Tested on COMe module with Intel Atom x5-E3940 processor (4 Core,
1.6/1.8GHz, 9.5W TDP). xubuntu 18.04.2 was used as a bootable OS
(5.0.0-32-generic linux kernel)
Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
A src/mainboard/kontron/mal10/Kconfig
A src/mainboard/kontron/mal10/Kconfig.name
A src/mainboard/kontron/mal10/Makefile.inc
A src/mainboard/kontron/mal10/acpi/dptf.asl
A src/mainboard/kontron/mal10/board_info.txt
A src/mainboard/kontron/mal10/bootblock.c
A src/mainboard/kontron/mal10/cmos.default
A src/mainboard/kontron/mal10/cmos.layout
A src/mainboard/kontron/mal10/data.vbt
A src/mainboard/kontron/mal10/dsdt.asl
A src/mainboard/kontron/mal10/gma-mainboard.ads
A src/mainboard/kontron/mal10/gpio.h
A src/mainboard/kontron/mal10/mal10.fmd
A src/mainboard/kontron/mal10/ramstage.c
A src/mainboard/kontron/mal10/romstage.c
A src/mainboard/kontron/mal10/variants/baseboard/devicetree.cb
A src/mainboard/kontron/mal10/variants/t10-tni/overridetree.cb
17 files changed, 1,152 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39133/12
--
To view, visit https://review.coreboot.org/c/coreboot/+/39133
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea
Gerrit-Change-Number: 39133
Gerrit-PatchSet: 12
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: newpatchset
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard
......................................................................
mb/asus/p8z77-v_lx2: Add new mainboard
Done using autoport and then a bunch of manual edits.
Working:
- Two DIMMs
- Serial port to emit spam
- S3 suspend/resume
- Some USB ports
- Realtek GbE
- Integrated graphics (libgfxinit)
- HDMI and VGA
- Some SATA ports
- Native raminit
- Flashing with flashrom
Untested:
- Four DIMMs
- PS/2 ports
- Audio: Only rear output (green) has been tested
- EHCI debug
- PCIe ports (some need to be disabled)
- PCI ports on the ASM1083 PCI bridge
- The remaining ports
- Non-Linux OSes
Change-Id: Ia5d9176b6f435977ecdd4fc82fc4bc0974d8d6a4
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
A src/mainboard/asus/p8z77-v_lx2/Kconfig
A src/mainboard/asus/p8z77-v_lx2/Kconfig.name
A src/mainboard/asus/p8z77-v_lx2/Makefile.inc
A src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl
A src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl
A src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl
A src/mainboard/asus/p8z77-v_lx2/acpi_tables.c
A src/mainboard/asus/p8z77-v_lx2/board_info.txt
A src/mainboard/asus/p8z77-v_lx2/devicetree.cb
A src/mainboard/asus/p8z77-v_lx2/dsdt.asl
A src/mainboard/asus/p8z77-v_lx2/early_init.c
A src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads
A src/mainboard/asus/p8z77-v_lx2/gpio.c
A src/mainboard/asus/p8z77-v_lx2/hda_verb.c
14 files changed, 634 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39299/1
diff --git a/src/mainboard/asus/p8z77-v_lx2/Kconfig b/src/mainboard/asus/p8z77-v_lx2/Kconfig
new file mode 100644
index 0000000..82310ab
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/Kconfig
@@ -0,0 +1,42 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2020 Angel Pons <th3fanbus(a)gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if BOARD_ASUS_P8Z77_V_LX2
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select MAINBOARD_HAS_LIBGFXINIT
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SUPERIO_NUVOTON_NCT6779D
+ select USE_NATIVE_RAMINIT
+
+config MAINBOARD_DIR
+ string
+ default asus/p8z77-v_lx2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "P8Z77-V LX2"
+
+config MAX_CPUS
+ int
+ default 8
+
+endif
diff --git a/src/mainboard/asus/p8z77-v_lx2/Kconfig.name b/src/mainboard/asus/p8z77-v_lx2/Kconfig.name
new file mode 100644
index 0000000..0dec75f
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_P8Z77_V_LX2
+ bool "P8Z77-V LX2"
diff --git a/src/mainboard/asus/p8z77-v_lx2/Makefile.inc b/src/mainboard/asus/p8z77-v_lx2/Makefile.inc
new file mode 100644
index 0000000..7167e10
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/Makefile.inc
@@ -0,0 +1,7 @@
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+
+romstage-y += early_init.c
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl
diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl
new file mode 100644
index 0000000..d8d3320
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl
new file mode 100644
index 0000000..f2b35ba
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl
@@ -0,0 +1 @@
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c
new file mode 100644
index 0000000..7f69572
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/asus/p8z77-v_lx2/board_info.txt b/src/mainboard/asus/p8z77-v_lx2/board_info.txt
new file mode 100644
index 0000000..79c36d6
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/uk/Motherboards/P8Z77V_LX2/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2013
diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb
new file mode 100644
index 0000000..f564aee
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb
@@ -0,0 +1,113 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2020 Angel Pons <th3fanbus(a)gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge
+ device cpu_cluster 0 on
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0 on end
+ device lapic 0xacac off end
+ end
+ end
+ register "pci_mmio_size" = "2048"
+ device domain 0 on
+ subsystemid 0x1043 0x84ca inherit
+
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PEG
+ device pci 02.0 on end # iGPU
+
+ chip southbridge/intel/bd82x6x
+ register "c2_latency" = "0x0065"
+ register "gen1_dec" = "0x000c0291"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x3f"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device pci 14.0 on end # xHCI
+ device pci 16.0 on end # MEI #1
+ device pci 16.1 off end # MEI #2
+ device pci 16.2 off end # ME IDE-R
+ device pci 16.3 off end # ME KT
+ device pci 19.0 off end # Intel GbE
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # HD Audio
+
+ device pci 1c.0 on end # RP #1:
+ device pci 1c.1 on end # RP #2:
+ device pci 1c.2 on end # RP #3:
+ device pci 1c.3 on end # RP #4:
+ device pci 1c.4 on end # RP #5: RTL8111 GbE NIC
+ device pci 1c.5 on end # RP #6: ASM1083 PCI Bridge
+ device pci 1c.6 on end # RP #7:
+ device pci 1c.7 on end # RP #8:
+
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip superio/nuvoton/nct6779d
+ device pnp 2e.1 off end # Parallel
+ device pnp 2e.2 on # UART A
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # UART B, IR
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x0060
+ io 0x62 = 0x0064
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GPIO6-8
+ device pnp 2e.8 off end # WDT1, GPIO0, GPIO1
+ device pnp 2e.108 on end # GPIO0
+ device pnp 2e.9 off end # GPIO1-8
+ device pnp 2e.109 off end # GPIO1
+ device pnp 2e.209 off end # GPIO2
+ device pnp 2e.309 off end # GPIO3
+ device pnp 2e.409 off end # GPIO4
+ device pnp 2e.509 on end # GPIO5
+ device pnp 2e.609 off end # GPIO6
+ device pnp 2e.709 off end # GPIO7
+ device pnp 2e.a on end # ACPI
+ device pnp 2e.b on # H/W Monitor, FP LED
+ io 0x60 = 0x0290
+ io 0x62 = 0
+ irq 0x70 = 0
+ end
+ device pnp 2e.d off end # WDT1
+ device pnp 2e.e off end # CIR WAKE-UP
+ device pnp 2e.f off end # GPIO Push-pull/Open-drain
+ device pnp 2e.14 off end # PORT80 UART
+ device pnp 2e.16 off end # Deep Sleep
+ end
+ end
+ device pci 1f.2 on end # SATA (AHCI)
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA (Legacy)
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl
new file mode 100644
index 0000000..f164b33
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI v2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include "acpi/platform.asl"
+ #include "acpi/superio.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/asus/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8z77-v_lx2/early_init.c
new file mode 100644
index 0000000..a720c1f
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/early_init.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+
+#define GLOBAL_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 4 },
+ { 1, 0, 4 },
+ { 1, 0, 6 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+ /* Select SIO pin states. */
+ pnp_write_config(GLOBAL_DEV, 0x1a, 0x02);
+ pnp_write_config(GLOBAL_DEV, 0x1b, 0x70);
+ pnp_write_config(GLOBAL_DEV, 0x1c, 0x10);
+ pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e);
+ pnp_write_config(GLOBAL_DEV, 0x22, 0xd7);
+ pnp_write_config(GLOBAL_DEV, 0x2a, 0x48);
+ pnp_write_config(GLOBAL_DEV, 0x2c, 0x00);
+
+ /* Power RAM in S3. */
+ pnp_set_logical_device(ACPI_DEV);
+ pnp_write_config(ACPI_DEV, 0xe4, 0x10);
+
+ nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+ /* Enable UART */
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
diff --git a/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads b/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads
new file mode 100644
index 0000000..37135f9
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads
@@ -0,0 +1,28 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (HDMI3,
+ Analog,
+ Others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/p8z77-v_lx2/gpio.c b/src/mainboard/asus/p8z77-v_lx2/gpio.c
new file mode 100644
index 0000000..634fb2e
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/gpio.c
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio28 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_GPIO,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_GPIO,
+ .gpio62 = GPIO_MODE_GPIO,
+ .gpio63 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT,
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio58 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_INPUT,
+ .gpio61 = GPIO_DIR_INPUT,
+ .gpio62 = GPIO_DIR_INPUT,
+ .gpio63 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_GPIO,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT,
+ .gpio65 = GPIO_DIR_INPUT,
+ .gpio66 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+ .gpio75 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/asus/p8z77-v_lx2/hda_verb.c b/src/mainboard/asus/p8z77-v_lx2/hda_verb.c
new file mode 100644
index 0000000..a52ccfb
--- /dev/null
+++ b/src/mainboard/asus/p8z77-v_lx2/hda_verb.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0887, /* Codec Vendor / Device ID: Realtek */
+ 0x10438445, /* Subsystem ID */
+ 15, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10438445),
+ AZALIA_PIN_CFG(0, 0x11, 0x99430130),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c50),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x58560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia5d9176b6f435977ecdd4fc82fc4bc0974d8d6a4
Gerrit-Change-Number: 39299
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39361 )
Change subject: lib/spd_bin: Fix grammar mistake in a comment
......................................................................
lib/spd_bin: Fix grammar mistake in a comment
Change-Id: I0a9ec0f9605282cbf4fd0ac05070278a3331b6fa
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/lib/spd_bin.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/39361/1
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index 9e625b5..25eb552 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -55,7 +55,7 @@
static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 };
int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf;
switch (dram_type) {
- /* DDR3 and LPDDR3 has the same bank definition */
+ /* DDR3 and LPDDR3 have the same bank definition */
case SPD_DRAM_DDR3:
case SPD_DRAM_LPDDR3_INTEL:
case SPD_DRAM_LPDDR3_JEDEC:
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0a9ec0f9605282cbf4fd0ac05070278a3331b6fa
Gerrit-Change-Number: 39361
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange
Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39274 )
Change subject: util/scripts/gerrit-rebase: Improve error message
......................................................................
util/scripts/gerrit-rebase: Improve error message
I received feedback that people were confused by "Error: foo", so
replace it with something more user friendly that serves the same
purpose.
Change-Id: I17b902a62020109e079437c8d9ffd7ea5979a3a1
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M util/scripts/gerrit-rebase
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39274/1
diff --git a/util/scripts/gerrit-rebase b/util/scripts/gerrit-rebase
index 276142d..d051103 100755
--- a/util/scripts/gerrit-rebase
+++ b/util/scripts/gerrit-rebase
@@ -71,7 +71,7 @@
cut -d: -f2-)"
# start rebase process, but fail immediately by enforcing an invalid todo
-GIT_SEQUENCE_EDITOR="echo foo >" \
+GIT_SEQUENCE_EDITOR="echo Ignore this error, it's intentional>" \
git rebase -i --onto ${to} ${from} ${to} 2>/dev/null
# write new rebase todo
--
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Gerrit-Change-Number: 39274
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39368 )
Change subject: src/soc/tigerlake: Enabled D3HotEnable in fsp_params
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39368/2/src/soc/intel/tigerlake/fs…
File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39368/2/src/soc/intel/tigerlake/fs…
PS2, Line 162: params->D3HotEnable = 1;
> Why is this put under S0ix enable? This is related to TCSS. […]
Also, I believe the EDS exposes the registers for setting these bits. I don't think we need to make use of FSP to do that.
--
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Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
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Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com>
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