Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39368 )
Change subject: src/soc/tigerlake: Enabled D3HotEnable in fsp_params
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Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39368/2/src/soc/intel/tigerlake/fsp...
File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39368/2/src/soc/intel/tigerlake/fsp...
PS2, Line 162: params->D3HotEnable = 1;
Why is this put under S0ix enable? This is related to TCSS. […]
Also, I believe the EDS exposes the registers for setting these bits. I don't think we need to make use of FSP to do that.
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