coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/soc/tigerlake: Enabled D3HotEnable in fsp_params
by Furquan Shaikh (Code Review) 07 Mar '20

07 Mar '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39368 ) Change subject: src/soc/tigerlake: Enabled D3HotEnable in fsp_params ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/39368/2/src/soc/intel/tigerlake/fs… File src/soc/intel/tigerlake/fsp_params_tgl.c: https://review.coreboot.org/c/coreboot/+/39368/2/src/soc/intel/tigerlake/fs… PS2, Line 162: params->D3HotEnable = 1; Why is this put under S0ix enable? This is related to TCSS. It should be tied in with other configurations for it. https://review.coreboot.org/c/coreboot/+/39368/2/src/vendorcode/intel/fsp/f… File src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h: PS2: Same comment as before about FSP header update. -- To view, visit https://review.coreboot.org/c/coreboot/+/39368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba12339378b38ff850da812135f51a1d8d4130f Gerrit-Change-Number: 39368 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Sat, 07 Mar 2020 15:38:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/tigerlake: add S0ix support fsp_params
by Furquan Shaikh (Code Review) 07 Mar '20

07 Mar '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39367 ) Change subject: src/soc/tigerlake: add S0ix support fsp_params ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/c/coreboot/+/39367/2/src/soc/intel/tigerlake/fs… File src/soc/intel/tigerlake/fsp_params_tgl.c: https://review.coreboot.org/c/coreboot/+/39367/2/src/soc/intel/tigerlake/fs… PS2, Line 162: 0x09 Why 0x09? Shouldn't this be board specific? https://review.coreboot.org/c/coreboot/+/39367/2/src/soc/intel/tigerlake/fs… PS2, Line 163: params->PchFivrVccinAuxLowToHighCurModeVolTranTime = 0; : params->PchFivrVccinAuxRetToHighCurModeVolTranTime = 0; : params->PchFivrVccinAuxOffToHighCurModeVolTranTime = 0; Why are these set to 0? I believe these have to be design specific. https://review.coreboot.org/c/coreboot/+/39367/2/src/vendorcode/intel/fsp/f… File src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h: PS2: Please update Fsp headers as a separate CL. Also, Intel is using a script to generate these. Please ensure that this is done following the same procedure. -- To view, visit https://review.coreboot.org/c/coreboot/+/39367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf29865e80311d6ef52ea0ff2a722f8d4e845dd7 Gerrit-Change-Number: 39367 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 07 Mar 2020 15:35:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/tigerlake: Enabled D3ColdEnable in fsp_params
by Wonkyu Kim (Code Review) 07 Mar '20

07 Mar '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39369 ) Change subject: src/soc/tigerlake: Enabled D3ColdEnable in fsp_params ...................................................................... Patch Set 2: UPD header change should be reviewed Intel internally and open up. We'll follow up UPD change. -- To view, visit https://review.coreboot.org/c/coreboot/+/39369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2b1b0b3b50cd8a7b2f974579dc281bcd65c243a Gerrit-Change-Number: 39369 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Divya S Sasidharan <divya.s.sasidharan(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Sat, 07 Mar 2020 07:22:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/tigerlake: Enabled D3HotEnable in fsp_params
by Wonkyu Kim (Code Review) 07 Mar '20

07 Mar '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39368 ) Change subject: src/soc/tigerlake: Enabled D3HotEnable in fsp_params ...................................................................... Patch Set 2: UPD header change should be reviewed Intel internally and open up. We'll follow up UPD change. -- To view, visit https://review.coreboot.org/c/coreboot/+/39368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba12339378b38ff850da812135f51a1d8d4130f Gerrit-Change-Number: 39368 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Sat, 07 Mar 2020 07:21:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/tigerlake: add S0ix support fsp_params
by Wonkyu Kim (Code Review) 07 Mar '20

07 Mar '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39367 ) Change subject: src/soc/tigerlake: add S0ix support fsp_params ...................................................................... Patch Set 2: UPD header change should be reviewed Intel internally and opened up. We'll follow up UPD change. -- To view, visit https://review.coreboot.org/c/coreboot/+/39367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf29865e80311d6ef52ea0ff2a722f8d4e845dd7 Gerrit-Change-Number: 39367 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 07 Mar 2020 07:21:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/tigerlake: Enabled D3HotEnable in fsp_params
by Caveh Jalali (Code Review) 07 Mar '20

07 Mar '20

Hello build bot (Jenkins), Wonkyu Kim, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39368 to look at the new patch set (#2). Change subject: src/soc/tigerlake: Enabled D3HotEnable in fsp_params ...................................................................... src/soc/tigerlake: Enabled D3HotEnable in fsp_params This enables the D3HotEnable feature for TCSS when s0ix is enabled. BUG=b:146624360,b:150912117 BRANCH=none TEST="Build and Boot on Volteer" Change-Id: Iaba12339378b38ff850da812135f51a1d8d4130f Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda(a)intel.com> Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/core… Reviewed-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda(a)intel.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh(a)google.com> Tested-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda(a)intel.corp-partner.google.com> Commit-Queue: Caveh Jalali <caveh(a)google.com> --- M src/soc/intel/tigerlake/fsp_params_tgl.c M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/39368/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba12339378b38ff850da812135f51a1d8d4130f Gerrit-Change-Number: 39368 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/soc/tigerlake: add S0ix support fsp_params
by Caveh Jalali (Code Review) 07 Mar '20

07 Mar '20

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39367 to look at the new patch set (#2). Change subject: src/soc/tigerlake: add S0ix support fsp_params ...................................................................... src/soc/tigerlake: add S0ix support fsp_params This adds support for configuring S0ix parameters in the device tree. BUG=b:150912117 TEST="Build and Boot on Volteer" Change-Id: Idf29865e80311d6ef52ea0ff2a722f8d4e845dd7 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/soc/intel/tigerlake/fsp_params_tgl.c M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/39367/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf29865e80311d6ef52ea0ff2a722f8d4e845dd7 Gerrit-Change-Number: 39367 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/soc/tigerlake: add S0ix support fsp_params
by Caveh Jalali (Code Review) 07 Mar '20

07 Mar '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39367 ) Change subject: src/soc/tigerlake: add S0ix support fsp_params ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/39367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf29865e80311d6ef52ea0ff2a722f8d4e845dd7 Gerrit-Change-Number: 39367 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 07 Mar 2020 07:06:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/tigerlake: Enabled D3ColdEnable in fsp_params
by Caveh Jalali (Code Review) 07 Mar '20

07 Mar '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39369 ) Change subject: src/soc/tigerlake: Enabled D3ColdEnable in fsp_params ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/39369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2b1b0b3b50cd8a7b2f974579dc281bcd65c243a Gerrit-Change-Number: 39369 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Divya S Sasidharan <divya.s.sasidharan(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Sat, 07 Mar 2020 07:04:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/tigerlake: Enabled D3HotEnable in fsp_params
by Caveh Jalali (Code Review) 07 Mar '20

07 Mar '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39368 ) Change subject: src/soc/tigerlake: Enabled D3HotEnable in fsp_params ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/39368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba12339378b38ff850da812135f51a1d8d4130f Gerrit-Change-Number: 39368 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Sat, 07 Mar 2020 07:03:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2020