coreboot-gerrit March 2020

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Change in coreboot[master]: mb/libretrend/lt1000: Add Libretrend LT1000 board support
by Angel Pons (Code Review) 06 Mar '20

06 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: mb/libretrend/lt1000: Add Libretrend LT1000 board support ...................................................................... Patch Set 15: (2 comments) https://review.coreboot.org/c/coreboot/+/30360/15//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/30360/15//COMMIT_MSG@7 PS15, Line 7: board support I would just say `mainboard` https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… File Documentation/mainboard/libretrend/lt1000.jpg: PS13: > Added some better quality image Sorry, I think I prefer the previous one. Do you happen to have the original file for it? -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Mar 2020 18:02:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/broadcom: Add ASPM blacklist
by Angel Pons (Code Review) 06 Mar '20

06 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39193 ) Change subject: drivers/broadcom: Add ASPM blacklist ...................................................................... drivers/broadcom: Add ASPM blacklist The Broadcom BCM5751 NIC on a PCIe card will make the computer hang if ASPM gets enabled. Blacklist it. Change-Id: I2cf8d56e9139928a6acfd1d09e47a96b9554fb06 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/drivers/broadcom/Makefile.inc A src/drivers/broadcom/bcm57xx_aspm_disable.c 2 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/39193/1 diff --git a/src/drivers/broadcom/Makefile.inc b/src/drivers/broadcom/Makefile.inc new file mode 100644 index 0000000..863ee56 --- /dev/null +++ b/src/drivers/broadcom/Makefile.inc @@ -0,0 +1,14 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += bcm57xx_aspm_disable.c diff --git a/src/drivers/broadcom/bcm57xx_aspm_disable.c b/src/drivers/broadcom/bcm57xx_aspm_disable.c new file mode 100644 index 0000000..427ba62 --- /dev/null +++ b/src/drivers/broadcom/bcm57xx_aspm_disable.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void bcm57xx_disable_aspm(struct device *const dev) +{ + printk(BIOS_INFO, "bcm57xx: Disabling ASPM for %s [%04x/%04x]\n", + dev_path(dev), dev->vendor, dev->device); + + dev->disable_pcie_aspm = 1; +} + +static struct device_operations bcm57xx_aspm_fixup_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = bcm57xx_disable_aspm, +}; + +static const unsigned short pci_device_ids[] = { + 0x1677, /* BCM5751 */ + 0, +}; + +static const struct pci_driver bcm57xx_aspm_fixup __pci_driver = { + .ops = &bcm57xx_aspm_fixup_ops, + .vendor = PCI_VENDOR_ID_BROADCOM, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/39193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cf8d56e9139928a6acfd1d09e47a96b9554fb06 Gerrit-Change-Number: 39193 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: northbridge: Remove unused '#include <device/pci.h>'
by HAOUAS Elyes (Code Review) 06 Mar '20

06 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37520 ) Change subject: northbridge: Remove unused '#include <device/pci.h>' ...................................................................... northbridge: Remove unused '#include <device/pci.h>' Change-Id: I942457a820a59428f7ae302262c4891a4c5ef1a6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/nehalem/acpi.c M src/northbridge/intel/nehalem/smi.c M src/northbridge/intel/pineview/acpi.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/acpi.c M src/northbridge/intel/sandybridge/common.c M src/northbridge/intel/x4x/acpi.c M src/northbridge/intel/x4x/northbridge.c 13 files changed, 0 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/37520/1 diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index ef152db..8d4f7b1 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -19,7 +19,6 @@ #include <arch/acpi.h> #include <arch/acpigen.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "gm45.h" diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 2625447..b297f67 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -18,7 +18,6 @@ #include <device/pci_ops.h> #include <stdint.h> #include <device/device.h> -#include <device/pci.h> #include <boot/tables.h> #include <arch/acpi.h> #include <cpu/intel/smm_reloc.h> diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index d92e858..a9b687b 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <arch/acpi.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "haswell.h" #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 3a9f6a2..66f26dd 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -18,7 +18,6 @@ #include <arch/acpi.h> #include <arch/acpigen.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "i945.h" diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 462cdc0..43b13c2 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -20,7 +20,6 @@ #include <types.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "nehalem.h" diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c index 8c19852..c3433a3 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/nehalem/smi.c @@ -15,7 +15,6 @@ #include <types.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "nehalem.h" diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c index 9dd8e31..2e12305 100644 --- a/src/northbridge/intel/pineview/acpi.c +++ b/src/northbridge/intel/pineview/acpi.c @@ -18,7 +18,6 @@ #include <arch/acpigen.h> #include <arch/acpi.h> #include <device/device.h> -#include <device/pci.h> #include <northbridge/intel/pineview/pineview.h> #include <types.h> diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index aec910c..1f7e36d 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -18,7 +18,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <device/pci.h> #include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/chip.h> #include <pc80/mc146818rtc.h> diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index c082586..d939511 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <stdint.h> #include <device/device.h> -#include <device/pci.h> #include <boot/tables.h> #include <arch/acpi.h> #include <northbridge/intel/pineview/pineview.h> diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 4afb546..9665972 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -20,7 +20,6 @@ #include <commonlib/helpers.h> #include <arch/acpi.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "sandybridge.h" #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c index 8bfd476..d141c99 100644 --- a/src/northbridge/intel/sandybridge/common.c +++ b/src/northbridge/intel/sandybridge/common.c @@ -18,7 +18,6 @@ #include <types.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include "sandybridge.h" enum platform_type get_platform_type(void) diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index a91d227..d25eb2b 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -20,7 +20,6 @@ #include <arch/acpi.h> #include <arch/acpigen.h> #include <device/device.h> -#include <device/pci.h> #include "x4x.h" unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index b7f9aaa..f2ff504 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <stdint.h> #include <device/device.h> -#include <device/pci.h> #include <boot/tables.h> #include <arch/acpi.h> #include <northbridge/intel/x4x/iomap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I942457a820a59428f7ae302262c4891a4c5ef1a6 Gerrit-Change-Number: 37520 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 6

Change in libhwbase[master]: Makefile: Adapt $(space) definition
by Angel Pons (Code Review) 06 Mar '20

06 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libhwbase/+/39163 ) Change subject: Makefile: Adapt $(space) definition ...................................................................... Makefile: Adapt $(space) definition GNU Make 4.3 is more picky about the $(space) definition. It seems that the variable ends up being empty. Change-Id: If07db29fc63e8a45e9b0869df894ce3420fa9b95 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/libhwbase refs/changes/63/39163/1 diff --git a/Makefile b/Makefile index a25deb6..14a7d4f 100644 --- a/Makefile +++ b/Makefile @@ -22,7 +22,7 @@ $(binary): space := -space += +space := $(space) $(space) comma := , strip_quotes = $(strip $(subst ",,$(1))) -- To view, visit https://review.coreboot.org/c/libhwbase/+/39163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: If07db29fc63e8a45e9b0869df894ce3420fa9b95 Gerrit-Change-Number: 39163 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/google/kahlee/nuwani: Create Nuwani variant
by Peichao Li (Code Review) 06 Mar '20

06 Mar '20

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39316 ) Change subject: mb/google/kahlee/nuwani: Create Nuwani variant ...................................................................... mb/google/kahlee/nuwani: Create Nuwani variant This commit creates a nuwani variant for Grunt. The initial settings override the baseboard was copied from variant treeya. BUG=b:144890301 TEST=emerge-grunt coreboot Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: Id3a7fc890340e5a88ebc4b516dc2c0b085654999 --- M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/Kconfig.name A src/mainboard/google/kahlee/variants/nuwani/Makefile.inc A src/mainboard/google/kahlee/variants/nuwani/devicetree.cb A src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl A src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl A src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl A src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl A src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl A src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h A src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h A src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h A src/mainboard/google/kahlee/variants/nuwani/mainboard.c A src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc 14 files changed, 543 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/39316/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 7d98d89..b46c1f6 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -66,6 +66,7 @@ default "careena" if BOARD_GOOGLE_CAREENA default "grunt" if BOARD_GOOGLE_GRUNT default "liara" if BOARD_GOOGLE_LIARA + default "nuwani" if BOARD_GOOGLE_NUWANI default "treeya" if BOARD_GOOGLE_TREEYA config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/google/kahlee/Kconfig.name b/src/mainboard/google/kahlee/Kconfig.name index 03d7baa..e0d2290 100644 --- a/src/mainboard/google/kahlee/Kconfig.name +++ b/src/mainboard/google/kahlee/Kconfig.name @@ -12,6 +12,9 @@ config BOARD_GOOGLE_LIARA bool "-> Liara" select BOARD_GOOGLE_BASEBOARD_KAHLEE +config BOARD_GOOGLE_NUWANI + bool "-> Nuwani" + select BOARD_GOOGLE_BASEBOARD_KAHLEE config BOARD_GOOGLE_TREEYA bool "-> Treeya" select BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc new file mode 100644 index 0000000..3753268 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2020 Google, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +subdirs-y += ./spd + +romstage-y += ../baseboard/romstage.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb new file mode 100644 index 0000000..6c953b1 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb @@ -0,0 +1,196 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + register "spd_addr_lookup" = " + { + { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 + }" + register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" + register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" + register "uma_size" = "16 * MiB" + register "stapm_percent" = "80" + register "stapm_time_ms" = "2000000" + register "stapm_power_mw" = "7800" + register "lvds_poseq_varybl_to_blon" = "0x5" + register "lvds_poseq_blon_to_varybl" = "0x5" + + # Enable I2C0 for audio, USB3 hub at 400kHz + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 95, + .fall_time_ns = 3, + }" + + # Enable I2C1 for H1 at 400kHz + register "i2c[1]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 3, + .fall_time_ns = 2, + }" + + # Enable I2C2 for trackpad, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 3, + .fall_time_ns = 2, + .data_hold_time_ns = 400, + }" + + # Enable I2C3 for touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 16, + .fall_time_ns = 8, + }" + + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + device cpu_cluster 0 on + device lapic 10 on end + end + device domain 0 on + device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU (Disabled for performance and battery) + device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # + device pci 2.2 on end # + device pci 2.3 on end # + device pci 2.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end + end # + device pci 2.5 on end # + device pci 8.0 on end # PSP + device pci 9.0 on end # PCIe Host Bridge + device pci 9.2 on end # HDA + device pci 10.0 on end # xHCI + device pci 11.0 off end # SATA + device pci 12.0 on end # EHCI + device pci 14.0 on # SMbus + end # SMbus + device pci 14.3 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #domain + device mmio 0xfedc2000 on + chip drivers/generic/adau7002 + device generic 0.0 on end + end + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + register "mclk_name" = ""oscout1"" + device i2c 1a on end + end + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + end + device mmio 0xfedc3000 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + device i2c 50 on end + end + end + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "wake" = "7" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_5)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end + device mmio 0xfedc5000 on + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "generic.reset_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end +end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl new file mode 100644 index 0000000..7a1e74b --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/gpe.asl> diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..acb906e --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/mainboard.asl> +#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl new file mode 100644 index 0000000..283e332 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/routing.asl> diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl new file mode 100644 index 0000000..b69f063 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/sleep.asl> diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..56a4da4 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h b/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h new file mode 100644 index 0000000..4a63722 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/ec.h> + +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + +/* + * Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in + * variant/gpio.h + */ +#define EC_ENABLE_SYNC_IRQ_GPIO diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h new file mode 100644 index 0000000..ebd7c5b --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> + +/* EC sync irq is AGPIO 10 */ +#define EC_SYNC_IRQ 10 diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h new file mode 100644 index 0000000..1bb78ef --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* + * Stoney Ridge Thermal Requirements 12 (6W) + * TDP (W) 6 + * T die,max (°C) 95 + * T ctl,max 85 + * T die,lmt (default) 90 + * T ctl,lmt (default) 80 + */ + +/* Control TDP Settings */ +#define CTL_TDP_SENSOR_ID 2 /* EC TIN2 */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 94 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 85 + +#endif diff --git a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c new file mode 100644 index 0000000..42dbe03 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/chromeec/ec.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <cbfs.h> +#include <gpio.h> +#include <smbios.h> +#include <variant/gpio.h> +#include <device/mmio.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <drivers/generic/bayhub/bh720.h> + +uint32_t sku_id(void) +{ + static int sku = -1; + + if (sku == -1) + sku = google_chromeec_get_sku_id(); + + return sku; +} + +uint8_t variant_board_sku(void) +{ + return sku_id(); +} + +void variant_mainboard_suspend_resume(void) +{ + /* Enable backlight - GPIO 133 active low */ + gpio_set(GPIO_133, 0); +} + +void board_bh720(struct device *dev) +{ + u32 sdbar; + u32 bh720_pcr_data; + + sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + + /* Enable Memory Access Function */ + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + + /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); + + /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + bh720_pcr_data &= 0x0000FFFF; + bh720_pcr_data |= 0x2510 << 16; + write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + + /* Use PLL Base clock PCR 0x3E4[22] = 1 */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_CSR); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_CSR); + + /* Disable Memory Access */ + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); + + /* Tune VIH */ + pci_write_config32(dev, BH720_PROTECT, + BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF); + bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL); + bh720_pcr_data &= 0xFFFFFF00; + /* CLK = 3 and DAT = 2 */ + bh720_pcr_data |= 0x35; + pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data); + pci_write_config32(dev, BH720_PROTECT, + BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON); +} + + +const char *smbios_mainboard_manufacturer(void) +{ + static char oem_bin_data[11]; + static const char *manuf; + + if (!CONFIG(USE_OEM_BIN)) + return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + + if (manuf) + return manuf; + + if (cbfs_boot_load_file("oem.bin", oem_bin_data, + sizeof(oem_bin_data) - 1, + CBFS_TYPE_RAW)) + manuf = &oem_bin_data[0]; + else + manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + + return manuf; +} diff --git a/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc new file mode 100644 index 0000000..a2d0d2f --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 +SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 +SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010 +SPD_SOURCES += micron-MT40A1G16KNR-075-E # 0b0011 +SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0100 +SPD_SOURCES += samsung-K4AAG165WB-MCRC # 0b0101 +SPD_SOURCES += micron-MT40A512M16LY-075-E # 0b0110 +SPD_SOURCES += hynix-H5ANAG6NCMR-VKC # 0b0111 +SPD_SOURCES += hynix-H5AN8G6NCJR-VKC # 0b1000 +SPD_SOURCES += samsung-K4A8G165WC-BCTD # 0b1001 +SPD_SOURCES += samsung-K4AAG165WB-MCTD # 0b1010 +SPD_SOURCES += micron-MT40A512M16TB-062E-J # 0b1011 +SPD_SOURCES += samsung-K4A8G165WC-BCWE # 0b1100 +SPD_SOURCES += hynix-H5AN8G6NCJR-XNC # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += empty # 0b1111 -- To view, visit https://review.coreboot.org/c/coreboot/+/39316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3a7fc890340e5a88ebc4b516dc2c0b085654999 Gerrit-Change-Number: 39316 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/common/block: tco: enable intruder SMI if selected
by Michael Niewöhner (Code Review) 06 Mar '20

06 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39264 ) Change subject: soc/intel/common/block: tco: enable intruder SMI if selected ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/39264/5/src/soc/intel/common/block… File src/soc/intel/common/block/smbus/tco.c: https://review.coreboot.org/c/coreboot/+/39264/5/src/soc/intel/common/block… PS5, Line 105: /* Make TCO issue an SMI on INTRD_DET assertion */ > We can start with one option, TCO SMI, but if there's ever a case where people would like more granu […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/39264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7 Gerrit-Change-Number: 39264 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Mar 2020 16:02:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block: tco: enable intruder SMI if selected
by Michael Niewöhner (Code Review) 06 Mar '20

06 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39264 ) Change subject: soc/intel/common/block: tco: enable intruder SMI if selected ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/39264/6/src/soc/intel/common/block… File src/soc/intel/common/block/smbus/tco.c: https://review.coreboot.org/c/coreboot/+/39264/6/src/soc/intel/common/block… PS6, Line 155: tco_intruder_smi_enable(); > Shouldn't this be based on the Kconfig option as well? If feels a little weird to enable it here, bu […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/39264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7 Gerrit-Change-Number: 39264 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Mar 2020 16:02:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/smm: add case intrusion to SMI handler
by Michael Niewöhner (Code Review) 06 Mar '20

06 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39265 ) Change subject: soc/intel/common/block/smm: add case intrusion to SMI handler ...................................................................... Uploaded patch set 8: Patch Set 7 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/39265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifad675bb09215ada760efebdcd915958febf5778 Gerrit-Change-Number: 39265 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Mar 2020 16:01:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: tco: enable intruder SMI if selected
by Michael Niewöhner (Code Review) 06 Mar '20

06 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39264 ) Change subject: soc/intel/common/block: tco: enable intruder SMI if selected ...................................................................... Uploaded patch set 8. -- To view, visit https://review.coreboot.org/c/coreboot/+/39264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7 Gerrit-Change-Number: 39264 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Mar 2020 16:01:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: tco: enable intruder SMI if selected
by Michael Niewöhner (Code Review) 06 Mar '20

06 Mar '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Paul Menzel, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, HAOUAS Elyes, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39264 to look at the new patch set (#8). Change subject: soc/intel/common/block: tco: enable intruder SMI if selected ...................................................................... soc/intel/common/block: tco: enable intruder SMI if selected Set TCO to issue an SMI when the case instrusion switch gets pressed. The SMI is controlled along with the general TCO SMI Kconfig. Tested on X11SSM-F. Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/smbus/tco.c 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39264/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/39264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7 Gerrit-Change-Number: 39264 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2020