coreboot-gerrit March 2020

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Change in coreboot[master]: mb/up/squared: remove NpkEn option from romstage
by Patrick Georgi (Code Review) 06 Mar '20

06 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39120 ) Change subject: mb/up/squared: remove NpkEn option from romstage ...................................................................... mb/up/squared: remove NpkEn option from romstage There is no need to set the NpkEn option to disable the NPK device, since it has already been done in the devicetree. Change-Id: I429f1129dc4149067503cd2ff9fb4c76cdc919f0 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39120 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/up/squared/romstage.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c index f9f0cfc..55235a8 100644 --- a/src/mainboard/up/squared/romstage.c +++ b/src/mainboard/up/squared/romstage.c @@ -169,7 +169,6 @@ config->RmtCheckRun = 0x3; // 0x0 config->RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 config->EnhancePort8xhDecoding = 0x0; // 0x1 - config->NpkEn = 0x0; // 0x3 config->PrimaryVideoAdaptor = 0x2; // 0x0 config->Ch0_DeviceWidth = 0x1; // 0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/39120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I429f1129dc4149067503cd2ff9fb4c76cdc919f0 Gerrit-Change-Number: 39120 Gerrit-PatchSet: 12 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/apl: add options to override USB port config
by Patrick Georgi (Code Review) 06 Mar '20

06 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38815 ) Change subject: soc/apl: add options to override USB port config ...................................................................... soc/apl: add options to override USB port config Allows to override the PortUsb20Enable and PortUsb30Enable FSP options (which are set to 1 by default) to enable/disable USB ports if the usb_config_override flag is set to "1". Therefore, these changes will not affect other boards with an Apollo Lake processor. Change-Id: Ia94a2be1647f7743ef0c918ae3b34437a179261c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38815 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/include/soc/usb.h 3 files changed, 47 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 37fdfff..4eabf8a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -558,11 +558,18 @@ static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) { -#if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these - fields in FspsUpd.h yet */ +#if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these fields in FspsUpd.h yet */ uint8_t port; for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { + if (cfg->usb_config_override) { + if (!cfg->usb2_port[port].enable) + continue; + + silconfig->PortUsb20Enable[port] = 1; + silconfig->PortUs20bOverCurrentPin[port] = cfg->usb2_port[port].oc_pin; + } + if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0) silconfig->PortUsb20PerPortTxPeHalf[port] = cfg->usb2eye[port].Usb20PerPortTxPeHalf; @@ -591,6 +598,16 @@ silconfig->PortUsb20HsNpreDrvSel[port] = cfg->usb2eye[port].Usb20HsNpreDrvSel; } + + if (cfg->usb_config_override) { + for (port = 0; port < APOLLOLAKE_USB3_PORT_MAX; port++) { + if (!cfg->usb3_port[port].enable) + continue; + + silconfig->PortUsb30Enable[port] = 1; + silconfig->PortUs30bOverCurrentPin[port] = cfg->usb3_port[port].oc_pin; + } + } #endif } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index e5045d0..40cd39b 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -136,6 +136,11 @@ /* USB2 eye diagram settings per port */ struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX]; + /* Override USB port configuration */ + uint8_t usb_config_override; + struct usb_port_config usb2_port[APOLLOLAKE_USB2_PORT_MAX]; + struct usb_port_config usb3_port[APOLLOLAKE_USB3_PORT_MAX]; + /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; diff --git a/src/soc/intel/apollolake/include/soc/usb.h b/src/soc/intel/apollolake/include/soc/usb.h index 28cad37..11dec48 100644 --- a/src/soc/intel/apollolake/include/soc/usb.h +++ b/src/soc/intel/apollolake/include/soc/usb.h @@ -21,6 +21,12 @@ #include <stdint.h> #define APOLLOLAKE_USB2_PORT_MAX 8 +#define APOLLOLAKE_USB3_PORT_MAX 6 + +struct usb_port_config { + uint8_t enable; + uint8_t oc_pin; +}; struct usb2_eye_per_port { uint8_t Usb20PerPortTxPeHalf; @@ -33,4 +39,21 @@ uint8_t Usb20OverrideEn; }; +/* USB overcurrent pins definition */ +enum { + OC0 = 0, + OC1 = 1, + OC_SKIP = 2, +}; + +#define PORT_EN(pin) { \ + .enable = 1, \ + .oc_pin = (pin), \ +} + +#define PORT_DIS { \ + .enable = 0, \ + .oc_pin = OC_SKIP, \ +} + #endif /* _SOC_APOLLOLAKE_USB_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia94a2be1647f7743ef0c918ae3b34437a179261c Gerrit-Change-Number: 38815 Gerrit-PatchSet: 19 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer: add new ripto variant
by Nick Vaccaro (Code Review) 06 Mar '20

06 Mar '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39301 ) Change subject: mb/google/volteer: add new ripto variant ...................................................................... mb/google/volteer: add new ripto variant Add a new ripto variant based off of the volteer baseboard design. BUG=b:148385924, b:150810535 TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto image and verify ripto boots to the kernel. Change-Id: If7606588147500a465f16c7846e2c8429ece93ec Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/ripto/Makefile.inc A src/mainboard/google/volteer/variants/ripto/gpio.c A src/mainboard/google/volteer/variants/ripto/include/variant/ec.h A src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h A src/mainboard/google/volteer/variants/ripto/overridetree.cb 7 files changed, 553 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39301/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 699cdea..28ea295 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -56,6 +56,7 @@ config MAINBOARD_PART_NUMBER string default "Volteer" if BOARD_GOOGLE_VOLTEER + default "Ripto" if BOARD_GOOGLE_RIPTO config MAX_CPUS int @@ -68,5 +69,6 @@ config VARIANT_DIR string default "volteer" if BOARD_GOOGLE_VOLTEER + default "ripto" if BOARD_GOOGLE_RIPTO endif # BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index a3fac9c..d60dfb4 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -3,3 +3,7 @@ config BOARD_GOOGLE_VOLTEER bool "-> Volteer" select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_RIPTO + bool "-> Ripto" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/ripto/Makefile.inc b/src/mainboard/google/volteer/variants/ripto/Makefile.inc new file mode 100644 index 0000000..9540149 --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2020 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = samsung-K4U6E3S4AA-MGCL # 0b0000 + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/ripto/gpio.c b/src/mainboard/google/volteer/variants/ripto/gpio.c new file mode 100644 index 0000000..244c45f --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/gpio.c @@ -0,0 +1,468 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A0 thru A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> NC(TP764) */ + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A9 : I2S2_TXD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_A9, NONE, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A11 : PMC_I2C_SDA ==> SSD_PERST_ODL */ + PAD_CFG_GPO(GPP_A11, 1, DEEP), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14 : USB_OC1# ==> USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B0 : CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : VRALERT# ==> VRALERT_L */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B4 : CPU_GP3 ==> NC */ + PAD_NC(GPP_B4, NONE), + /* B5 : ISH_I2C0_CVF_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : ISH_I2C0_CVF_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B12 : SLP_S0# ==> SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, DN_20K), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> EN_USB_CAM_PWR */ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C3 : SML0CLK ==> USB4_SMB_SCL */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : SML0DATA ==> USB4_SMB_SDA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, DN_20K), + /* C6 : SML1CLK ==> EC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C6, NONE, PLTRST, LEVEL, INVERT), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C8 : UART0_RXD ==> UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : UART0_CTS# ==> CVF_LPSS_INT_L */ + PAD_CFG_GPI(GPP_C11, NONE, DEEP), + /* C12 : UART1_RXD ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_C12, NONE, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C14 : UART1_RTS# ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_C14, NONE, DEEP), + /* C15 : UART1_CTS# ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_C15, NONE, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_NC(GPP_D0, UP_20K), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, UP_20K, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, UP_20K, DEEP), + /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ + PAD_CFG_GPI(GPP_D3, UP_20K, DEEP), + /* D4 : IMGCLKOUT0 ==> CAM_CVF_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> PCH_GSPI2_CVF_CS_L */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF7), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D11 : ISH_SPI_MISO ==> PCH_GSPI2_CVF_MISO */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_D15, NONE, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_CVF_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* D18 : ISH_GP5 ==> CVF_ACE_ISH_INT_L */ + PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1), + /* D19 : I2S_MCLK1 ==> I2S_MCLK1 */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ + PAD_NC(GPP_E6, NONE), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), + /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ + PAD_CFG_GPO(GPP_E13, 0, DEEP), + /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ + PAD_CFG_TERM_GPO(GPP_E17, 1, DN_20K, DEEP), + /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), + /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */ + PAD_NC(GPP_E23, NONE), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP ==> NCV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : I2S2_TXD ==> CNV_RGI_DT_STRAP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : I2S2_RXD ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_APIC(GPP_F8, UP_20K, DEEP, EDGE_BOTH, INVERT), + /* F9 : Reserved ==> NC */ + /* F10 : GPPF10_STRAP */ + PAD_NC(GPP_F10, DN_20K), + /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_ODL */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F14 : GSXDIN ==> SAR0_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + /* F15 : GSXSRESET# ==> SAR1_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F15, NONE, PLTRST, EDGE_SINGLE), + /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_F17, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + /* F20 : EXT_PWR_GATE# ==> EXT_PWR_GATE_L */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EXT_PWR_GATE2# ==> EXT_PWR_GATE2_L */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : V1P05_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : I2C2_SDA ==> PCH_I2C2_SAR0_WLAN_HDMI_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C2_SCL ==> PCH_I2C2_SAR0_WLAN_HDMI_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SAR1_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SAR1_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> WWAN_CONFIG2 */ + PAD_CFG_GPI(GPP_H14, NONE, DEEP), + /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_H15, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> PCH_CAM_VSYNC */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> EN_MIPI_CAM_PWR */ + PAD_CFG_GPO(GPP_H20, 0, PLTRST), + /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* H23 : IMGCLKOUT4 ==> WWAN_ESIM_SEL_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : HDA_RST# ==> HDA_RST_L */ + PAD_CFG_NF(GPP_R4, DN_20K, DEEP, NF1), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> DMIC_CLK1 */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* S5 : SNDW2_DATA ==> DMIC_DATA1 */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD0: BATLOW# ==> BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> SLP_A_L */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: GPD7_STRAP */ + PAD_CFG_GPI(GPD7, DN_20K, DEEP), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: SLP_S5# ==> SLP_S5_L */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: LANPHYC ==> NC */ +}; + +const struct pad_config *variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, RSMRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} + diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h b/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h new file mode 100644 index 0000000..3655f14 --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h b/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h new file mode 100644 index 0000000..3a3282e --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/ripto/overridetree.cb b/src/mainboard/google/volteer/variants/ripto/overridetree.cb new file mode 100644 index 0000000..67e7df9 --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/overridetree.cb @@ -0,0 +1,10 @@ +chip soc/intel/tigerlake + + # Limit L1.1(value:2) for RP9, RP11 + #register "PcieRpL1Substates[8]" = "2" + #register "PcieRpL1Substates[10]" = "2" + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/39301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7606588147500a465f16c7846e2c8429ece93ec Gerrit-Change-Number: 39301 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: mb/google/volteer: make variant_early_gpio_table weak
by Nick Vaccaro (Code Review) 06 Mar '20

06 Mar '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39300 ) Change subject: mb/google/volteer: make variant_early_gpio_table weak ...................................................................... mb/google/volteer: make variant_early_gpio_table weak Declare variant_early_gpio_table() weak to allow override by variants. BUG=b:148385924, b:150810535 TEST=none Change-Id: Ife5e3b75256f71ecd763c4000fd2c7d7c927bb64 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/39300/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 2dc340f..3f1f2b0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -452,7 +452,7 @@ return NULL; } -const struct pad_config *variant_early_gpio_table(size_t *num) +const struct pad_config *__weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; -- To view, visit https://review.coreboot.org/c/coreboot/+/39300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife5e3b75256f71ecd763c4000fd2c7d7c927bb64 Gerrit-Change-Number: 39300 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

5 4

Change in ...coreboot[master]: mb/lenovo/*: Add support for VBOOT on 12MiB devices
by Patrick Rudolph (Code Review) 06 Mar '20

06 Mar '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32617 Change subject: mb/lenovo/*: Add support for VBOOT on 12MiB devices ...................................................................... mb/lenovo/*: Add support for VBOOT on 12MiB devices Enable VBOOT support on all devices that have a 8 MiB flash, using a single RW_MAIN_A partition, allowing the use of tianocore payload in both RW_MAIN_A and WP_RO. * Add VBNV section to cmos.layout * Add FMAP for VBOOT and regular boot * Select Kconfigs for VBOOT * Enable VBOOT_SLOTS_RW_A by default Untested. Change-Id: I8a35a06ece1e9d57a2ef23970e61ae26fafce543 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/t430/Kconfig A src/mainboard/lenovo/t430/board.fmd M src/mainboard/lenovo/t430/cmos.layout A src/mainboard/lenovo/t430/vboot-rwa.fmd M src/mainboard/lenovo/t430s/Kconfig A src/mainboard/lenovo/t430s/board.fmd M src/mainboard/lenovo/t430s/cmos.layout A src/mainboard/lenovo/t430s/vboot-rwa.fmd M src/mainboard/lenovo/t530/Kconfig A src/mainboard/lenovo/t530/board.fmd M src/mainboard/lenovo/t530/cmos.layout A src/mainboard/lenovo/t530/vboot-rwa.fmd M src/mainboard/lenovo/x131e/Kconfig A src/mainboard/lenovo/x131e/board.fmd M src/mainboard/lenovo/x131e/cmos.layout A src/mainboard/lenovo/x131e/vboot-rwa.fmd M src/mainboard/lenovo/x1_carbon_gen1/Kconfig A src/mainboard/lenovo/x1_carbon_gen1/board.fmd M src/mainboard/lenovo/x1_carbon_gen1/cmos.layout A src/mainboard/lenovo/x1_carbon_gen1/vboot-rwa.fmd M src/mainboard/lenovo/x230/Kconfig A src/mainboard/lenovo/x230/board.fmd M src/mainboard/lenovo/x230/cmos.layout A src/mainboard/lenovo/x230/vboot-rwa.fmd 24 files changed, 408 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/32617/1 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index dbeaadb..fdccd66 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -26,6 +26,21 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/t430 diff --git a/src/mainboard/lenovo/t430/board.fmd b/src/mainboard/lenovo/t430/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/t430/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout index 1b50e7f..f9757f0 100644 --- a/src/mainboard/lenovo/t430/cmos.layout +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -80,6 +80,9 @@ #437 3 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t430/vboot-rwa.fmd b/src/mainboard/lenovo/t430/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/t430/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index bad1837..a56f577 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -26,6 +26,21 @@ # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/t430s diff --git a/src/mainboard/lenovo/t430s/board.fmd b/src/mainboard/lenovo/t430s/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/t430s/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 97d97ed..891a294 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -80,6 +80,9 @@ #436 4 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t430s/vboot-rwa.fmd b/src/mainboard/lenovo/t430s/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/t430s/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index b36460d..df011e4 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -27,6 +27,21 @@ if BOARD_LENOVO_BASEBOARD_T530 +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config VARIANT_DIR string default "t530" if BOARD_LENOVO_T530 diff --git a/src/mainboard/lenovo/t530/board.fmd b/src/mainboard/lenovo/t530/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/t530/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index 3400a4d..0c8c546 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -81,6 +81,9 @@ 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t530/vboot-rwa.fmd b/src/mainboard/lenovo/t530/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/t530/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index e7da8d0..3da7b3b 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -21,6 +21,21 @@ select SERIRQ_CONTINUOUS_MODE select INTEL_GMA_HAVE_VBT +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/x131e diff --git a/src/mainboard/lenovo/x131e/board.fmd b/src/mainboard/lenovo/x131e/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/x131e/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/x131e/cmos.layout b/src/mainboard/lenovo/x131e/cmos.layout index 93c74fb..41b8354 100644 --- a/src/mainboard/lenovo/x131e/cmos.layout +++ b/src/mainboard/lenovo/x131e/cmos.layout @@ -79,6 +79,9 @@ 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x131e/vboot-rwa.fmd b/src/mainboard/lenovo/x131e/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/x131e/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 520853c..29060d9 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -26,6 +26,21 @@ # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/x1_carbon_gen1 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/board.fmd b/src/mainboard/lenovo/x1_carbon_gen1/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/x1_carbon_gen1/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout index bb25261..55a8a58 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout +++ b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout @@ -80,6 +80,9 @@ 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwa.fmd b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 5b34b83..e7d7720 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -27,6 +27,21 @@ # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/x230 diff --git a/src/mainboard/lenovo/x230/board.fmd b/src/mainboard/lenovo/x230/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/x230/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 27197fb..9903400 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -80,6 +80,9 @@ 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x230/vboot-rwa.fmd b/src/mainboard/lenovo/x230/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/x230/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a35a06ece1e9d57a2ef23970e61ae26fafce543 Gerrit-Change-Number: 32617 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

10 32

Change in coreboot[master]: nb/intel/haswell/peg: Add PEG driver stub
by Name of user not set (Code Review) 06 Mar '20

06 Mar '20

Name of user not set #1002789 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38743 ) Change subject: nb/intel/haswell/peg: Add PEG driver stub ...................................................................... nb/intel/haswell/peg: Add PEG driver stub This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the haswell northbridge. This code is necessary to support the dGPU of the t440p. Code was cut and pasted from sandybridge with vendor IDs updated to the correct haswell values. Tested on t440p with dGPU on Ubuntu 18.04.4 with 5.3.0-29 kernel. Without patches dmesg reports noveau is unable to read the ROM of the dGPU as it has an invalid checksum (I checked that the ROM in CBFS is correct). With patches drm appears to be initalized and dmesg only reports an error I assume is related to the Optimus setup of "DRM: Pointer to TMDS table invalid". Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27 Signed-off-by: Chris Morgan <macromorgan(a)hotmail.com> --- M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl A src/northbridge/intel/haswell/acpi/peg.asl A src/northbridge/intel/haswell/pcie.c 5 files changed, 156 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38743/1 diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index b986336..73a20f2 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -19,6 +19,7 @@ ramstage-y += memmap.c ramstage-y += northbridge.c +ramstage-y += pcie.c ramstage-y += gma.c ramstage-y += acpi.c diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 45ebff2..2db72d7 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -16,6 +16,7 @@ #include "../haswell.h" #include "hostbridge.asl" +#include "peg.asl" #include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 19d788c..d567701 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -36,7 +36,8 @@ MHEN, 1, // Enable , 13, // MHBR, 22, // MCHBAR - + Offset (0x54), + DVEN, 32, Offset (0x60), // PCIe BAR PXEN, 1, // Enable PXSZ, 2, // BAR size diff --git a/src/northbridge/intel/haswell/acpi/peg.asl b/src/northbridge/intel/haswell/acpi/peg.asl new file mode 100644 index 0000000..07f7cdf --- /dev/null +++ b/src/northbridge/intel/haswell/acpi/peg.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PEGP) +{ + Name (_ADR, 0x00010000) + + Method (_STA) + { + ShiftRight (\_SB.PCI0.MCHC.DVEN, 3, Local0) + Return (And (Local0, 1)) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} + +Device (PEG1) +{ + Name (_ADR, 0x00010001) + + Method (_STA) + { + ShiftRight (\_SB.PCI0.MCHC.DVEN, 2, Local0) + Return (And (Local0, 1)) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} + +Device (PEG2) +{ + Name (_ADR, 0x00010002) + + Method (_STA) + { + ShiftRight (\_SB.PCI0.MCHC.DVEN, 1, Local0) + Return (And (Local0, 1)) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c new file mode 100644 index 0000000..ea9fa54 --- /dev/null +++ b/src/northbridge/intel/haswell/pcie.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ids.h> +#include <assert.h> + +static void pcie_disable(struct device *dev) +{ + printk(BIOS_INFO, "%s: Disabling device\n", dev_path(dev)); + dev->enabled = 0; +} + +#if CONFIG(HAVE_ACPI_TABLES) +static const char *pcie_acpi_name(const struct device *dev) +{ + assert(dev); + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + assert(dev->bus); + if (dev->bus->secondary == 0) + switch (dev->path.pci.devfn) { + case PCI_DEVFN(1, 0): + return "PEGP"; + case PCI_DEVFN(1, 1): + return "PEG1"; + case PCI_DEVFN(1, 2): + return "PEG2"; + }; + + struct device *const port = dev->bus->dev; + assert(port); + assert(port->bus); + + if (dev->path.pci.devfn == PCI_DEVFN(0, 0) && + port->bus->secondary == 0 && + (port->path.pci.devfn == PCI_DEVFN(1, 0) || + port->path.pci.devfn == PCI_DEVFN(1, 1) || + port->path.pci.devfn == PCI_DEVFN(1, 2))) + return "DEV0"; + + return NULL; +} +#endif + +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .disable = pcie_disable, + .init = pci_dev_init, + .ops_pci = &pci_ops, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = pcie_acpi_name, +#endif +}; + +static const unsigned short pci_device_ids[] = { 0x0c01, 0x0c05, 0x0c09, 0x0c0d, + 0 }; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/38743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27 Gerrit-Change-Number: 38743 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002789 Gerrit-MessageType: newchange

6 35

Change in coreboot[master]: sb/intel/common/firmware/Makefile.inc: use ifdtool --output flag
by Marcello Sylvester Bauer (Code Review) 06 Mar '20

06 Mar '20

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39275 ) Change subject: sb/intel/common/firmware/Makefile.inc: use ifdtool --output flag ...................................................................... sb/intel/common/firmware/Makefile.inc: use ifdtool --output flag Use the ifdtool --output flag to modify coreboot.pre inplace, instead of using the `mv` command to get the same result. In this way the stdout will make more sense in the build context. Change-Id: I6dacc8b39052801c770c02fa2aa1b526747ae496 Signed-off-by: Marcello Sylvester Bauer <sylv(a)sylv.io> --- M src/southbridge/intel/common/firmware/Makefile.inc 1 file changed, 12 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/39275/1 diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 5f3212f..2352636 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -55,8 +55,8 @@ $(objutil)/ifdtool/ifdtool \ $(IFDTOOL_USE_CHIPSET) \ -i ME:$(CONFIG_ME_BIN_PATH) \ + -O $(obj)/coreboot.pre \ $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_CHECK_ME),y) util/me_cleaner/me_cleaner.py -c $(obj)/coreboot.pre > /dev/null @@ -72,36 +72,39 @@ $(objutil)/ifdtool/ifdtool \ $(IFDTOOL_USE_CHIPSET) \ -i GbE:$(CONFIG_GBE_BIN_PATH) \ + -O $(obj)/coreboot.pre \ $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_HAVE_EC_BIN),y) printf " IFDTOOL ec.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ $(IFDTOOL_USE_CHIPSET) \ -i EC:$(CONFIG_EC_BIN_PATH) \ + -O $(obj)/coreboot.pre \ $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) printf " IFDTOOL Locking Management Engine\n" $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) -l $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre + $(IFDTOOL_USE_CHIPSET) -l \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre endif ifeq ($(CONFIG_UNLOCK_FLASH_REGIONS),y) printf " IFDTOOL Unlocking Management Engine\n" $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre + $(IFDTOOL_USE_CHIPSET) -u \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre endif ifeq ($(CONFIG_EM100),y) printf " IFDTOOL Setting EM100 mode\n" $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) --em100 $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre + $(IFDTOOL_USE_CHIPSET) --em100 \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre endif warn_intel_firmware: -- To view, visit https://review.coreboot.org/c/coreboot/+/39275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6dacc8b39052801c770c02fa2aa1b526747ae496 Gerrit-Change-Number: 39275 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylv(a)sylv.io> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/tigerlake: Avoid NULL pointer dereference
by John Zhao (Code Review) 06 Mar '20

06 Mar '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39260 ) Change subject: soc/intel/tigerlake: Avoid NULL pointer dereference ...................................................................... soc/intel/tigerlake: Avoid NULL pointer dereference Coverity detects pointer dev as FORWARD_NULL. Add sanity check for dev to prevent NULL pointer dereference. BUG=CID 1353148 TEST=Built and boot up to kernel. Change-Id: Ic0ad1ec79c950a3c17feccdde4f87f4a107fe8c0 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/tigerlake/fsp_params_jsl.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/39260/1 diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c index 8eb3fba..39ef66e 100644 --- a/src/soc/intel/tigerlake/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/fsp_params_jsl.c @@ -158,9 +158,12 @@ /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); - if (!dev || !xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; + if (!dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + + params->XdciEnable = dev->enabled; + } /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/39260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0ad1ec79c950a3c17feccdde4f87f4a107fe8c0 Gerrit-Change-Number: 39260 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: src/arch/x86: Convert to SPDX license header
by Patrick Georgi (Code Review) 06 Mar '20

06 Mar '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39284 ) Change subject: src/arch/x86: Convert to SPDX license header ...................................................................... src/arch/x86: Convert to SPDX license header This also drops individual copyright notices, all mentioned authors in that part of the tree are listed in AUTHORS. Change-Id: Ib5a92bb46ff2b9d2928aae3763daec71747044c2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc M src/arch/x86/acpi.c M src/arch/x86/acpi/debug.asl M src/arch/x86/acpi/globutil.asl M src/arch/x86/acpi/statdef.asl M src/arch/x86/acpi_bert_storage.c M src/arch/x86/acpi_device.c M src/arch/x86/acpi_pld.c M src/arch/x86/acpi_s3.c M src/arch/x86/acpigen.c M src/arch/x86/acpigen_dsm.c M src/arch/x86/assembly_entry.S M src/arch/x86/boot.c M src/arch/x86/bootblock_crt0.S M src/arch/x86/bootblock_normal.c M src/arch/x86/c_start.S M src/arch/x86/car.ld M src/arch/x86/cbmem.c M src/arch/x86/cf9_reset.c M src/arch/x86/cpu.c M src/arch/x86/cpu_common.c M src/arch/x86/ebda.c M src/arch/x86/exception.c M src/arch/x86/exit_car.S M src/arch/x86/gdt.c M src/arch/x86/gdt_init.S M src/arch/x86/id.S M src/arch/x86/id.ld M src/arch/x86/idt.S M src/arch/x86/include/arch/acpi.h M src/arch/x86/include/arch/acpi_device.h M src/arch/x86/include/arch/acpi_ivrs.h M src/arch/x86/include/arch/acpi_pld.h M src/arch/x86/include/arch/acpigen.h M src/arch/x86/include/arch/acpigen_dsm.h M src/arch/x86/include/arch/bert_storage.h M src/arch/x86/include/arch/boot/boot.h M src/arch/x86/include/arch/bootblock.h M src/arch/x86/include/arch/byteorder.h M src/arch/x86/include/arch/cache.h M src/arch/x86/include/arch/cbconfig.h M src/arch/x86/include/arch/cpu.h M src/arch/x86/include/arch/ebda.h M src/arch/x86/include/arch/exception.h M src/arch/x86/include/arch/header.ld M src/arch/x86/include/arch/hlt.h M src/arch/x86/include/arch/interrupt.h M src/arch/x86/include/arch/io.h M src/arch/x86/include/arch/ioapic.h M src/arch/x86/include/arch/memlayout.h M src/arch/x86/include/arch/memory_clear.h M src/arch/x86/include/arch/mmio.h M src/arch/x86/include/arch/pci_io_cfg.h M src/arch/x86/include/arch/pci_ops.h M src/arch/x86/include/arch/pirq_routing.h M src/arch/x86/include/arch/ram_segs.h M src/arch/x86/include/arch/registers.h M src/arch/x86/include/arch/rom_segs.h M src/arch/x86/include/arch/romstage.h M src/arch/x86/include/arch/smp/atomic.h M src/arch/x86/include/arch/smp/mpspec.h M src/arch/x86/include/arch/smp/spinlock.h M src/arch/x86/include/arch/stages.h M src/arch/x86/include/arch/symbols.h M src/arch/x86/include/cf9_reset.h M src/arch/x86/include/smm.h M src/arch/x86/ioapic.c M src/arch/x86/memcpy.c M src/arch/x86/memlayout.ld M src/arch/x86/memmove.c M src/arch/x86/memset.c M src/arch/x86/mmap_boot.c M src/arch/x86/mpspec.c M src/arch/x86/pirq_routing.c M src/arch/x86/post.c M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/arch/x86/prologue.inc M src/arch/x86/rdrand.c M src/arch/x86/smbios.c M src/arch/x86/tables.c M src/arch/x86/thread.c M src/arch/x86/thread_switch.S M src/arch/x86/timestamp.c M src/arch/x86/timestamp.inc M src/arch/x86/verstage.c M src/arch/x86/wakeup.S M src/arch/x86/walkcbfs.S M util/lint/lint-stable-000-license-headers 90 files changed, 182 insertions(+), 1,106 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/39284/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 1c55bdb..810a5bb 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -1,15 +1,7 @@ ## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## config ARCH_X86 bool diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 534f2ce..8731612 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,15 +1,7 @@ ## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ifeq ($(CONFIG_POSTCAR_STAGE),y) $(eval $(call init_standard_toolchain,postcar)) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index b9e896f..ae1967a 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1,15 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * coreboot ACPI Table support */ diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl index 36afac6..cde807c 100644 --- a/src/arch/x86/acpi/debug.asl +++ b/src/arch/x86/acpi/debug.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include <arch/acpi.h> diff --git a/src/arch/x86/acpi/globutil.asl b/src/arch/x86/acpi/globutil.asl index e9b428a..7667100 100644 --- a/src/arch/x86/acpi/globutil.asl +++ b/src/arch/x86/acpi/globutil.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Scope(\_SB) { diff --git a/src/arch/x86/acpi/statdef.asl b/src/arch/x86/acpi/statdef.asl index 99194f4..d6959ff 100644 --- a/src/arch/x86/acpi/statdef.asl +++ b/src/arch/x86/acpi/statdef.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Status and notification definitions */ diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index 130f97a..a7061fa 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <bootstate.h> #include <cbmem.h> diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 1092c73..9f1710e 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <string.h> #include <arch/acpi.h> diff --git a/src/arch/x86/acpi_pld.c b/src/arch/x86/acpi_pld.c index 6fbbfe7..135009a 100644 --- a/src/arch/x86/acpi_pld.c +++ b/src/arch/x86/acpi_pld.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <stdint.h> #include <string.h> diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ecfe34c..bf17980 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <console/console.h> #include <string.h> diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 9162cdb..a599b0e 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* How much nesting do we support? */ #define ACPIGEN_LENSTACK_SIZE 10 diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c index 294c6c3..ecac3fe 100644 --- a/src/arch/x86/acpigen_dsm.c +++ b/src/arch/x86/acpigen_dsm.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <arch/acpigen.h> #include <arch/acpigen_dsm.h> diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index fef5ce9..d48d28f 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <rules.h> diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index ada49d0..ae14bc2 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <commonlib/helpers.h> #include <console/console.h> diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 3256731..5d3ba4e 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -1,16 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * This is the modern bootblock. It prepares the system for C environment runtime * setup. The actual setup is done by hardware-specific code. * diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index b6b31af..e5de255 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <cbfs.h> #include <fallback.h> diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 8872439..1148e05 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <cpu/x86/post_code.h> #include <arch/ram_segs.h> diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 2e29112..5e5493a 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This file is included inside a SECTIONS block */ . = CONFIG_DCACHE_RAM_BASE; diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index b20eb67..55215f6 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <cbmem.h> diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c index d93bed7..675d5ed 100644 --- a/src/arch/x86/cf9_reset.c +++ b/src/arch/x86/cf9_reset.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <arch/io.h> #include <arch/cache.h> diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 30d2cca..4c1bce0 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <bootstate.h> #include <boot/coreboot_tables.h> diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index 0fd0af0..1646b44 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <cpu/cpu.h> diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c index f92f305..4ac1359 100644 --- a/src/arch/x86/ebda.c +++ b/src/arch/x86/ebda.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <stdint.h> #include <arch/acpi.h> diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index a599e79..e238fe7 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <arch/cpu.h> #include <arch/exception.h> diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 8c28784..e9b260d 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <cpu/x86/mtrr.h> #include <cpu/x86/cr.h> diff --git a/src/arch/x86/gdt.c b/src/arch/x86/gdt.c index 27e4af3..511e689 100644 --- a/src/arch/x86/gdt.c +++ b/src/arch/x86/gdt.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <types.h> #include <string.h> diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S index f66cd43..1bf3910 100644 --- a/src/arch/x86/gdt_init.S +++ b/src/arch/x86/gdt_init.S @@ -1,15 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + .code32 .section ".text._gdt_", "ax", @progbits diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S index 6151990..dd447e6 100644 --- a/src/arch/x86/id.S +++ b/src/arch/x86/id.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <build.h> diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld index 2a50f9c..31d5738 100644 --- a/src/arch/x86/id.ld +++ b/src/arch/x86/id.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ SECTIONS { . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; diff --git a/src/arch/x86/idt.S b/src/arch/x86/idt.S index 9c36d81..0d6101b 100644 --- a/src/arch/x86/idt.S +++ b/src/arch/x86/idt.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ .section ".text._idt", "ax", @progbits #ifdef __x86_64__ diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 67f4be2..fc20c79 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * coreboot ACPI support - headers and defines. diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index 90af81b..e9c5cd4 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ACPI_DEVICE_H #define __ACPI_DEVICE_H diff --git a/src/arch/x86/include/arch/acpi_ivrs.h b/src/arch/x86/include/arch/acpi_ivrs.h index 784b5a3..d8d62d4 100644 --- a/src/arch/x86/include/arch/acpi_ivrs.h +++ b/src/arch/x86/include/arch/acpi_ivrs.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * AMD I/O Virtualization Technology (IOMMU) diff --git a/src/arch/x86/include/arch/acpi_pld.h b/src/arch/x86/include/arch/acpi_pld.h index f23aacd..944eb31 100644 --- a/src/arch/x86/include/arch/acpi_pld.h +++ b/src/arch/x86/include/arch/acpi_pld.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ACPI_PLD_H #define __ACPI_PLD_H diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 34c5197..4aba5f9 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef LIBACPI_H #define LIBACPI_H diff --git a/src/arch/x86/include/arch/acpigen_dsm.h b/src/arch/x86/include/arch/acpigen_dsm.h index 49ed6db..c51c12b 100644 --- a/src/arch/x86/include/arch/acpigen_dsm.h +++ b/src/arch/x86/include/arch/acpigen_dsm.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_ACPIGEN_DSM_H__ #define __ARCH_ACPIGEN_DSM_H__ diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index 644f24e..3e7b0b5 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BERT_STORAGE_H_ #define _BERT_STORAGE_H_ diff --git a/src/arch/x86/include/arch/boot/boot.h b/src/arch/x86/include/arch/boot/boot.h index 0c9053f..bfa2351 100644 --- a/src/arch/x86/include/arch/boot/boot.h +++ b/src/arch/x86/include/arch/boot/boot.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ASM_I386_BOOT_H #define ASM_I386_BOOT_H diff --git a/src/arch/x86/include/arch/bootblock.h b/src/arch/x86/include/arch/bootblock.h index 1ca4a76..a4dcb3a 100644 --- a/src/arch/x86/include/arch/bootblock.h +++ b/src/arch/x86/include/arch/bootblock.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_BOOTBLOCK_H__ #define __ARCH_BOOTBLOCK_H__ diff --git a/src/arch/x86/include/arch/byteorder.h b/src/arch/x86/include/arch/byteorder.h index 37cb8b6..096ef75 100644 --- a/src/arch/x86/include/arch/byteorder.h +++ b/src/arch/x86/include/arch/byteorder.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BYTEORDER_H #define _BYTEORDER_H diff --git a/src/arch/x86/include/arch/cache.h b/src/arch/x86/include/arch/cache.h index 36476fd..5333c61 100644 --- a/src/arch/x86/include/arch/cache.h +++ b/src/arch/x86/include/arch/cache.h @@ -1,32 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef ARCH_CACHE_H #define ARCH_CACHE_H diff --git a/src/arch/x86/include/arch/cbconfig.h b/src/arch/x86/include/arch/cbconfig.h index b222ef3..21b4921 100644 --- a/src/arch/x86/include/arch/cbconfig.h +++ b/src/arch/x86/include/arch/cbconfig.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_CBCONFIG_H_ #define _ARCH_CBCONFIG_H_ diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 59eb9ad..e149c38 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_CPU_H #define ARCH_CPU_H diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h index 6ee3332..637ecc9 100644 --- a/src/arch/x86/include/arch/ebda.h +++ b/src/arch/x86/include/arch/ebda.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_EBDA_H #define __ARCH_EBDA_H diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h index df6f9e5..86cc7d5 100644 --- a/src/arch/x86/include/arch/exception.h +++ b/src/arch/x86/include/arch/exception.h @@ -1,29 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index 69f6d7d..01a20e5 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <rules.h> diff --git a/src/arch/x86/include/arch/hlt.h b/src/arch/x86/include/arch/hlt.h index a3f5c85..acb4365 100644 --- a/src/arch/x86/include/arch/hlt.h +++ b/src/arch/x86/include/arch/hlt.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_HLT_H #define ARCH_HLT_H diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h index baf6b78..cebfcbb 100644 --- a/src/arch/x86/include/arch/interrupt.h +++ b/src/arch/x86/include/arch/interrupt.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef INTERRUPT_H #define INTERRUPT_H diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 43cfc1b..8da7554 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_IO_H__ #define __ARCH_IO_H__ diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 5938cdc..078b212 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __I386_ARCH_IOAPIC_H #define __I386_ARCH_IOAPIC_H diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 11da892..2eea83f 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H diff --git a/src/arch/x86/include/arch/memory_clear.h b/src/arch/x86/include/arch/memory_clear.h index 2b887b8..960fe5d 100644 --- a/src/arch/x86/include/arch/memory_clear.h +++ b/src/arch/x86/include/arch/memory_clear.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MEMORY_CLEAR_H #define MEMORY_CLEAR_H diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h index efdbe27..1d7aeea 100644 --- a/src/arch/x86/include/arch/mmio.h +++ b/src/arch/x86/include/arch/mmio.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_MMIO_H__ #define __ARCH_MMIO_H__ diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 1e6934a..c2f85a8 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PCI_IO_CFG_H #define _PCI_IO_CFG_H diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index e706216..f11f612 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_I386_PCI_OPS_H #define ARCH_I386_PCI_OPS_H diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h index 60495a1..0e1f131 100644 --- a/src/arch/x86/include/arch/pirq_routing.h +++ b/src/arch/x86/include/arch/pirq_routing.h @@ -1,16 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + #ifndef ARCH_PIRQ_ROUTING_H #define ARCH_PIRQ_ROUTING_H diff --git a/src/arch/x86/include/arch/ram_segs.h b/src/arch/x86/include/arch/ram_segs.h index 39d0c64..0543b22 100644 --- a/src/arch/x86/include/arch/ram_segs.h +++ b/src/arch/x86/include/arch/ram_segs.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RAM_SEGS_H #define RAM_SEGS_H diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 8cf0d48..b47a787 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_REGISTERS_H #define __ARCH_REGISTERS_H diff --git a/src/arch/x86/include/arch/rom_segs.h b/src/arch/x86/include/arch/rom_segs.h index c11def6..da9623c 100644 --- a/src/arch/x86/include/arch/rom_segs.h +++ b/src/arch/x86/include/arch/rom_segs.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ROM_SEGS_H #define ROM_SEGS_H diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 83d15e4..0f9a358 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_ROMSTAGE_H__ #define __ARCH_ROMSTAGE_H__ diff --git a/src/arch/x86/include/arch/smp/atomic.h b/src/arch/x86/include/arch/smp/atomic.h index 75650c7..7a84e1f 100644 --- a/src/arch/x86/include/arch/smp/atomic.h +++ b/src/arch/x86/include/arch/smp/atomic.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_SMP_ATOMIC_H #define ARCH_SMP_ATOMIC_H diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h index 7500945..75f1be7 100644 --- a/src/arch/x86/include/arch/smp/mpspec.h +++ b/src/arch/x86/include/arch/smp/mpspec.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ASM_MPSPEC_H #define __ASM_MPSPEC_H diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 8bdb125..c45431d 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 0726cac..1e3cb97 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h index efe10fe..6f06baf 100644 --- a/src/arch/x86/include/arch/symbols.h +++ b/src/arch/x86/include/arch/symbols.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_SYMBOLS_H #define __ARCH_SYMBOLS_H diff --git a/src/arch/x86/include/cf9_reset.h b/src/arch/x86/include/cf9_reset.h index e05c2e1..9b2f053 100644 --- a/src/arch/x86/include/cf9_reset.h +++ b/src/arch/x86/include/cf9_reset.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef X86_CF9_RESET_H #define X86_CF9_RESET_H diff --git a/src/arch/x86/include/smm.h b/src/arch/x86/include/smm.h index 320bac6..e2eb40c 100644 --- a/src/arch/x86/include/smm.h +++ b/src/arch/x86/include/smm.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <stddef.h> #include <stdint.h> diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 757f7ee..5293000 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <device/mmio.h> #include <arch/ioapic.h> diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c index 80f5989..ec781b0 100644 --- a/src/arch/x86/memcpy.c +++ b/src/arch/x86/memcpy.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <string.h> diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index eff3738..05efac6 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <memlayout.h> #include <arch/header.ld> diff --git a/src/arch/x86/memmove.c b/src/arch/x86/memmove.c index 2cd7e48..20a5f11 100644 --- a/src/arch/x86/memmove.c +++ b/src/arch/x86/memmove.c @@ -1,17 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * This file is derived from memcpy_32.c in the Linux kernel. - * Unlike many coreboot files, this file may not be re-licensed as GPL V3 */ #include <string.h> diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c index 0767683..4f92a74 100644 --- a/src/arch/x86/memset.c +++ b/src/arch/x86/memset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the GNU C Library. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* From glibc-2.14, sysdeps/i386/memset.c */ diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index 74764fc..2358d72 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <boot_device.h> #include <endian.h> diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index eeca816..edb607e 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <console/console.h> #include <device/path.h> diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index ab3793c..b8d2e256 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -1,16 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + #include <console/console.h> #include <arch/pirq_routing.h> #include <commonlib/helpers.h> diff --git a/src/arch/x86/post.c b/src/arch/x86/post.c index b9cd26b..0aaf9b7 100644 --- a/src/arch/x86/post.c +++ b/src/arch/x86/post.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <stdint.h> #include <console/console.h> diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index add72c2..a3a521b 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <arch/romstage.h> #include <cbmem.h> diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index ee2c01b..2efa7ac 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <arch/romstage.h> #include <cbmem.h> diff --git a/src/arch/x86/prologue.inc b/src/arch/x86/prologue.inc index 4036ff9..4901dc5 100644 --- a/src/arch/x86/prologue.inc +++ b/src/arch/x86/prologue.inc @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <cpu/x86/post_code.h> diff --git a/src/arch/x86/rdrand.c b/src/arch/x86/rdrand.c index bf9e687..c526975 100644 --- a/src/arch/x86/rdrand.c +++ b/src/arch/x86/rdrand.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <random.h> diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8cd4518..c047d75 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <string.h> #include <smbios.h> diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 8ecf86d..066e635 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <console/console.h> #include <bootmem.h> diff --git a/src/arch/x86/thread.c b/src/arch/x86/thread.c index d92d8fd..4f98781 100644 --- a/src/arch/x86/thread.c +++ b/src/arch/x86/thread.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <thread.h> diff --git a/src/arch/x86/thread_switch.S b/src/arch/x86/thread_switch.S index 1c1dede..133be1b 100644 --- a/src/arch/x86/thread_switch.S +++ b/src/arch/x86/thread_switch.S @@ -1,15 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + .code32 .text diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index 8cf0f96..d156f1d 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <cpu/x86/tsc.h> #include <timestamp.h> diff --git a/src/arch/x86/timestamp.inc b/src/arch/x86/timestamp.inc index 1436906..052106d 100644 --- a/src/arch/x86/timestamp.inc +++ b/src/arch/x86/timestamp.inc @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Store the initial timestamp for booting in mmx registers. This works diff --git a/src/arch/x86/verstage.c b/src/arch/x86/verstage.c index ad13e60..2be33e2 100644 --- a/src/arch/x86/verstage.c +++ b/src/arch/x86/verstage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <arch/cpu.h> #include <main_decl.h> diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S index 187b96c..cfe0d64 100644 --- a/src/arch/x86/wakeup.S +++ b/src/arch/x86/wakeup.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define WAKEUP_BASE 0x600 #define RELOCATED(x) (x - __wakeup + WAKEUP_BASE) diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index ded6558..4a99add 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define CBFS_HEADER_PTR 0xfffffffc diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers index 300fde5..befdf3c 100755 --- a/util/lint/lint-stable-000-license-headers +++ b/util/lint/lint-stable-000-license-headers @@ -6,14 +6,11 @@ # Directories requiring SPDX Identifiers only util/lint/lint-000-license-headers "src/acpi" SPDX_ONLY +util/lint/lint-000-license-headers "src/arch" SPDX_ONLY util/lint/lint-000-license-headers "src/superio" SPDX_ONLY -util/lint/lint-000-license-headers "src/arch/arm" SPDX_ONLY -util/lint/lint-000-license-headers "src/arch/arm64" SPDX_ONLY -util/lint/lint-000-license-headers "src/arch/ppc64" SPDX_ONLY -util/lint/lint-000-license-headers "src/arch/riscv" SPDX_ONLY # Top level -util/lint/lint-000-license-headers "src/arch/x86 src/commonlib src/console \ +util/lint/lint-000-license-headers "src/commonlib src/console \ src/cpu src/device src/ec src/mainboard src/northbridge src/soc \ src/southbridge" -- To view, visit https://review.coreboot.org/c/coreboot/+/39284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5a92bb46ff2b9d2928aae3763daec71747044c2 Gerrit-Change-Number: 39284 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: src/arch/riscv: Convert to SPDX license header
by Patrick Georgi (Code Review) 06 Mar '20

06 Mar '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39283 ) Change subject: src/arch/riscv: Convert to SPDX license header ...................................................................... src/arch/riscv: Convert to SPDX license header This also drops individual copyright notices, all mentioned authors in that part of the tree are listed in AUTHORS. Change-Id: I770c1afd9b68a40ec0e69818f24b5ef3ad4f1d35 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M AUTHORS M src/arch/riscv/Makefile.inc M src/arch/riscv/arch_timer.c M src/arch/riscv/boot.c M src/arch/riscv/bootblock.S M src/arch/riscv/fit_payload.c M src/arch/riscv/fp_asm.S M src/arch/riscv/include/arch/barrier.h M src/arch/riscv/include/arch/boot.h M src/arch/riscv/include/arch/byteorder.h M src/arch/riscv/include/arch/cache.h M src/arch/riscv/include/arch/cbconfig.h M src/arch/riscv/include/arch/cpu.h M src/arch/riscv/include/arch/encoding.h M src/arch/riscv/include/arch/errno.h M src/arch/riscv/include/arch/exception.h M src/arch/riscv/include/arch/header.ld M src/arch/riscv/include/arch/hlt.h M src/arch/riscv/include/arch/memlayout.h M src/arch/riscv/include/arch/mmio.h M src/arch/riscv/include/arch/pmp.h M src/arch/riscv/include/arch/smp/atomic.h M src/arch/riscv/include/arch/smp/smp.h M src/arch/riscv/include/arch/smp/spinlock.h M src/arch/riscv/include/arch/stages.h M src/arch/riscv/include/bits.h M src/arch/riscv/include/mcall.h M src/arch/riscv/include/sbi.h M src/arch/riscv/include/vm.h M src/arch/riscv/mcall.c M src/arch/riscv/misaligned.c M src/arch/riscv/misc.c M src/arch/riscv/opensbi.c M src/arch/riscv/payload.c M src/arch/riscv/pmp.c M src/arch/riscv/ramstage.S M src/arch/riscv/romstage.c M src/arch/riscv/sbi.c M src/arch/riscv/smp.c M src/arch/riscv/tables.c M src/arch/riscv/trap_handler.c M src/arch/riscv/trap_util.S M src/arch/riscv/virtual_memory.c M util/lint/lint-stable-000-license-headers 44 files changed, 88 insertions(+), 695 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/39283/1 diff --git a/AUTHORS b/AUTHORS index d41c958..9ec48bb 100644 --- a/AUTHORS +++ b/AUTHORS @@ -52,6 +52,7 @@ Gergely Kiss Google LLC Greg Watson +HardenedLinux Idwer Vollering Imagination Technologies Infineon Technologies @@ -125,6 +126,7 @@ Texas Instruments The ChromiumOS Authors The Linux Foundation +The Regents of the University of California Thomas Winischhofer Timothy Pearson Tobias Diedrich diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 0038523..17f225a 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -1,19 +1,8 @@ ################################################################################ ## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## -## Copyright (C) 2014 The ChromiumOS Authors -## Copyright (C) 2018 HardenedLinux -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ################################################################################ ################################################################################ diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c index 55b1f72..af5db5e 100644 --- a/src/arch/riscv/arch_timer.c +++ b/src/arch/riscv/arch_timer.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Philipp Hug <philipp(a)hug.cx> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <device/mmio.h> #include <arch/encoding.h> diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index f9f94a7..0e6e223 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <program_loading.h> #include <vm.h> diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index b0796f9..b25a541 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -1,18 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Early initialization code for RISC-V - * - * Copyright 2013 Google Inc. - * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. */ #include <arch/encoding.h> diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index 63cda84..58d40f3 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -1,18 +1,5 @@ -/* - * Copyright 2013 Google Inc. - * Copyright 2018 Facebook, Inc. - * Copyright 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include <cbfs.h> #include <commonlib/bsd/compression.h> diff --git a/src/arch/riscv/fp_asm.S b/src/arch/riscv/fp_asm.S index 9c6cc65..5961047 100644 --- a/src/arch/riscv/fp_asm.S +++ b/src/arch/riscv/fp_asm.S @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file define some function used to swap value between memory diff --git a/src/arch/riscv/include/arch/barrier.h b/src/arch/riscv/include/arch/barrier.h index 257e2a2..d5e61e8 100644 --- a/src/arch/riscv/include/arch/barrier.h +++ b/src/arch/riscv/include/arch/barrier.h @@ -1,33 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_BARRIER_H_ #define __ARCH_BARRIER_H__ diff --git a/src/arch/riscv/include/arch/boot.h b/src/arch/riscv/include/arch/boot.h index c05c669..be1e6f1 100644 --- a/src/arch/riscv/include/arch/boot.h +++ b/src/arch/riscv/include/arch/boot.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_RISCV_INCLUDE_ARCH_BOOT_H #define ARCH_RISCV_INCLUDE_ARCH_BOOT_H diff --git a/src/arch/riscv/include/arch/byteorder.h b/src/arch/riscv/include/arch/byteorder.h index 37cb8b6..096ef75 100644 --- a/src/arch/riscv/include/arch/byteorder.h +++ b/src/arch/riscv/include/arch/byteorder.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BYTEORDER_H #define _BYTEORDER_H diff --git a/src/arch/riscv/include/arch/cache.h b/src/arch/riscv/include/arch/cache.h index 37d0662..b42ad95 100644 --- a/src/arch/riscv/include/arch/cache.h +++ b/src/arch/riscv/include/arch/cache.h @@ -1,32 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef ARCH_CACHE_H #define ARCH_CACHE_H diff --git a/src/arch/riscv/include/arch/cbconfig.h b/src/arch/riscv/include/arch/cbconfig.h index 9467f52..fedc8bd 100644 --- a/src/arch/riscv/include/arch/cbconfig.h +++ b/src/arch/riscv/include/arch/cbconfig.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_CBCONFIG_H_ #define _ARCH_CBCONFIG_H_ diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index c62199e..e249aa3 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h index f84c9d4..8aae565 100644 --- a/src/arch/riscv/include/arch/encoding.h +++ b/src/arch/riscv/include/arch/encoding.h @@ -1,29 +1,5 @@ -/* - * Copyright (c) 2010-2017, The Regents of the University of California - * (Regents). All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ +/* SPDX-License-Identifier: BSD-4-Clause-UC */ +/* This file is part of the coreboot project. */ #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H diff --git a/src/arch/riscv/include/arch/errno.h b/src/arch/riscv/include/arch/errno.h index 6f80ee5..1aa8eeb 100644 --- a/src/arch/riscv/include/arch/errno.h +++ b/src/arch/riscv/include/arch/errno.h @@ -1,29 +1,5 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ +/* SPDX-License-Identifier: BSD-4-Clause-UC */ +/* This file is part of the coreboot project. */ #ifndef _RISCV_ERRNO_BASE_H #define _RISCV_ERRNO_BASE_H diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h index 6fbbdf0..3e8da6c 100644 --- a/src/arch/riscv/include/arch/exception.h +++ b/src/arch/riscv/include/arch/exception.h @@ -1,31 +1,5 @@ -/* - * This file is part of the libpayload project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld index 4b11047..1168b37 100644 --- a/src/arch/riscv/include/arch/header.ld +++ b/src/arch/riscv/include/arch/header.ld @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <rules.h> diff --git a/src/arch/riscv/include/arch/hlt.h b/src/arch/riscv/include/arch/hlt.h index a955ebb..4020def 100644 --- a/src/arch/riscv/include/arch/hlt.h +++ b/src/arch/riscv/include/arch/hlt.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ static __always_inline void hlt(void) { diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index ac707d0..fcbe6a7 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This file contains macro definitions for memlayout.ld linker scripts. */ diff --git a/src/arch/riscv/include/arch/mmio.h b/src/arch/riscv/include/arch/mmio.h index 4cbc07b..e66629e 100644 --- a/src/arch/riscv/include/arch/mmio.h +++ b/src/arch/riscv/include/arch/mmio.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_MMIO_H__ #define __ARCH_MMIO_H__ diff --git a/src/arch/riscv/include/arch/pmp.h b/src/arch/riscv/include/arch/pmp.h index 6cdb997..8335349 100644 --- a/src/arch/riscv/include/arch/pmp.h +++ b/src/arch/riscv/include/arch/pmp.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __RISCV_PMP_H__ #define __RISCV_PMP_H__ diff --git a/src/arch/riscv/include/arch/smp/atomic.h b/src/arch/riscv/include/arch/smp/atomic.h index de7fd19..1ac6e79 100644 --- a/src/arch/riscv/include/arch/smp/atomic.h +++ b/src/arch/riscv/include/arch/smp/atomic.h @@ -1,30 +1,5 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * Copyright (c) 2018, HardenedLinux. - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ +/* SPDX-License-Identifier: BSD-4-Clause-UC */ +/* This file is part of the coreboot project. */ #ifndef _RISCV_ATOMIC_H #define _RISCV_ATOMIC_H diff --git a/src/arch/riscv/include/arch/smp/smp.h b/src/arch/riscv/include/arch/smp/smp.h index e996404..353f8f5 100644 --- a/src/arch/riscv/include/arch/smp/smp.h +++ b/src/arch/riscv/include/arch/smp/smp.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _RISCV_SMP_H #define _RISCV_SMP_H diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h index 95e60bf..c9c2e6c 100644 --- a/src/arch/riscv/include/arch/smp/spinlock.h +++ b/src/arch/riscv/include/arch/smp/spinlock.h @@ -1,17 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H diff --git a/src/arch/riscv/include/arch/stages.h b/src/arch/riscv/include/arch/stages.h index 138298f..2d81668 100644 --- a/src/arch/riscv/include/arch/stages.h +++ b/src/arch/riscv/include/arch/stages.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 The ChromiumOS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H diff --git a/src/arch/riscv/include/bits.h b/src/arch/riscv/include/bits.h index d824f3e..8afb14a 100644 --- a/src/arch/riscv/include/bits.h +++ b/src/arch/riscv/include/bits.h @@ -1,29 +1,5 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ +/* SPDX-License-Identifier: BSD-4-Clause-UC */ +/* This file is part of the coreboot project. */ #ifndef _BITS_H #define _BITS_H diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index d7d67ce..44b2d27 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 The ChromiumOS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MCALL_H #define _MCALL_H diff --git a/src/arch/riscv/include/sbi.h b/src/arch/riscv/include/sbi.h index 2943704..2905310 100644 --- a/src/arch/riscv/include/sbi.h +++ b/src/arch/riscv/include/sbi.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RISCV_SBI_H #define RISCV_SBI_H diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index 9f6236e..5c2b1d4 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -1,29 +1,5 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ +/* SPDX-License-Identifier: BSD-4-Clause-UC */ +/* This file is part of the coreboot project. */ #ifndef _VM_H #define _VM_H diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c index afb17c1..8e788a7 100644 --- a/src/arch/riscv/mcall.c +++ b/src/arch/riscv/mcall.c @@ -1,29 +1,5 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ +/* SPDX-License-Identifier: BSD-4-Clause-UC */ +/* This file is part of the coreboot project. */ #include <mcall.h> #include <string.h> diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c index ebff2d6..172b215 100644 --- a/src/arch/riscv/misaligned.c +++ b/src/arch/riscv/misaligned.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <stddef.h> #include <stdint.h> diff --git a/src/arch/riscv/misc.c b/src/arch/riscv/misc.c index 1909dbc..71bef1d 100644 --- a/src/arch/riscv/misc.c +++ b/src/arch/riscv/misc.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <delay.h> diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c index 695c24f..d9fdc2f 100644 --- a/src/arch/riscv/opensbi.c +++ b/src/arch/riscv/opensbi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <sbi/fw_dynamic.h> #include <arch/boot.h> diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c index 297d30d..715d7f3 100644 --- a/src/arch/riscv/payload.c +++ b/src/arch/riscv/payload.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google Inc - * Copyright (C) 2018 HardenedLinux - * Copyright (C) 2018 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <program_loading.h> #include <stdint.h> diff --git a/src/arch/riscv/pmp.c b/src/arch/riscv/pmp.c index 5e32f9c..e707051 100644 --- a/src/arch/riscv/pmp.c +++ b/src/arch/riscv/pmp.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <arch/encoding.h> #include <stdint.h> diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S index 2468c23..676c59b 100644 --- a/src/arch/riscv/ramstage.S +++ b/src/arch/riscv/ramstage.S @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <arch/encoding.h> #include <bits.h> diff --git a/src/arch/riscv/romstage.c b/src/arch/riscv/romstage.c index d5f5a43..0991c68 100644 --- a/src/arch/riscv/romstage.c +++ b/src/arch/riscv/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Entry points must be placed at the location the previous stage jumps diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index 2770189..bbde935 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <mcall.h> #include <stdint.h> diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index 95d116a..eb435d8 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <stddef.h> #include <arch/encoding.h> diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index c5bcab0..8a60b43 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2005 Steve Magnani - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <bootmem.h> #include <boot/tables.h> diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 6b39fab..91db114 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -1,17 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Early initialization code for riscv - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. */ #include <arch/encoding.h> diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 8aba48b..0e7d53b 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -1,17 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Early initialization code for riscv - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. */ #include <bits.h> diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 2f13ecb..431f711 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -1,17 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Early initialization code for riscv virtual memory - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. */ #include <arch/cpu.h> diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers index 99eea7f..300fde5 100755 --- a/util/lint/lint-stable-000-license-headers +++ b/util/lint/lint-stable-000-license-headers @@ -10,9 +10,10 @@ util/lint/lint-000-license-headers "src/arch/arm" SPDX_ONLY util/lint/lint-000-license-headers "src/arch/arm64" SPDX_ONLY util/lint/lint-000-license-headers "src/arch/ppc64" SPDX_ONLY +util/lint/lint-000-license-headers "src/arch/riscv" SPDX_ONLY # Top level -util/lint/lint-000-license-headers "src/arch/riscv src/arch/x86 src/commonlib src/console \ +util/lint/lint-000-license-headers "src/arch/x86 src/commonlib src/console \ src/cpu src/device src/ec src/mainboard src/northbridge src/soc \ src/southbridge" -- To view, visit https://review.coreboot.org/c/coreboot/+/39283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I770c1afd9b68a40ec0e69818f24b5ef3ad4f1d35 Gerrit-Change-Number: 39283 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2020