coreboot-gerrit March 2020

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Change in coreboot[master]: soc/intel/common/block/smm: add Kconfig for TCO SMI
by Aaron Durbin (Code Review) 05 Mar '20

05 Mar '20

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39326 ) Change subject: soc/intel/common/block/smm: add Kconfig for TCO SMI ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id22777e9573376e5a079a375400caa687bc41afb Gerrit-Change-Number: 39326 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 05 Mar 2020 20:47:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: tco: enable intruder SMI
by Michael Niewöhner (Code Review) 05 Mar '20

05 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39264 ) Change subject: soc/intel/common/block: tco: enable intruder SMI ...................................................................... Patch Set 6: > Patch Set 5: > > (1 comment) ack, see cb:39326 -- To view, visit https://review.coreboot.org/c/coreboot/+/39264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7 Gerrit-Change-Number: 39264 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Mar 2020 20:40:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/smm: add Kconfig for TCO SMI
by Michael Niewöhner (Code Review) 05 Mar '20

05 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39326 ) Change subject: soc/intel/common/block/smm: add Kconfig for TCO SMI ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/39326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id22777e9573376e5a079a375400caa687bc41afb Gerrit-Change-Number: 39326 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 05 Mar 2020 20:39:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/smm: add case intrusion to SMI handler
by Michael Niewöhner (Code Review) 05 Mar '20

05 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39265 ) Change subject: soc/intel/common/block/smm: add case intrusion to SMI handler ...................................................................... Uploaded patch set 6: Patch Set 5 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/39265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifad675bb09215ada760efebdcd915958febf5778 Gerrit-Change-Number: 39265 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Mar 2020 20:38:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: tco: enable intruder SMI
by Michael Niewöhner (Code Review) 05 Mar '20

05 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39264 ) Change subject: soc/intel/common/block: tco: enable intruder SMI ...................................................................... Uploaded patch set 6: Patch Set 5 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/39264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7 Gerrit-Change-Number: 39264 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Mar 2020 20:38:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers
by Michael Niewöhner (Code Review) 05 Mar '20

05 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39263 ) Change subject: intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers ...................................................................... Uploaded patch set 6: Patch Set 5 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/39263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If12d21e8e6721abb877cbbfbbba8f0127a86d96b Gerrit-Change-Number: 39263 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Mar 2020 20:38:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected
by Michael Niewöhner (Code Review) 05 Mar '20

05 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39262 ) Change subject: intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected ...................................................................... Uploaded patch set 6. -- To view, visit https://review.coreboot.org/c/coreboot/+/39262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Gerrit-Change-Number: 39262 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 05 Mar 2020 20:38:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected
by Michael Niewöhner (Code Review) 05 Mar '20

05 Mar '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Paul Menzel, Andrey Petrov, Andrey Petrov, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Felix Held, HAOUAS Elyes, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39262 to look at the new patch set (#6). Change subject: intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected ...................................................................... intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected Enable TCO SMIs in common code, if selected by Kconfig. This is needed for the follow-up commits regarding INTRUDER interrupt. Tested on X11SSM-F. Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/common/block/smm/smm.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/tigerlake/include/soc/pm.h 6 files changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/39262/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/39262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Gerrit-Change-Number: 39262 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Enable ELOG
by Brandon Breitenstein (Code Review) 05 Mar '20

05 Mar '20

Brandon Breitenstein has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/22851 ) Change subject: soc/intel/cannonlake: Enable ELOG ...................................................................... Abandoned Very old code not needed -- To view, visit https://review.coreboot.org/c/coreboot/+/22851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0100a9699e717a0d9d32e5ae92bebb350f803537 Gerrit-Change-Number: 22851 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: ec/google/chromeec : Enable TCSS port set flag
by Brandon Breitenstein (Code Review) 05 Mar '20

05 Mar '20

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38726 ) Change subject: ec/google/chromeec : Enable TCSS port set flag ...................................................................... ec/google/chromeec : Enable TCSS port set flag Kernel needs a way to know if coreboot initialized any Type-C SubSytem ports during boot. This API allows EC to store this information and pass it on to the Kernel when it checks for port status. BUG = NONE BRANCH = NONE TEST = Built coreboot image and tested that the flag was being set Change-Id: Idfc1e6515411fab75b7da1b60775c26d17089c1c Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_commands.h M src/soc/intel/tigerlake/early_tcss.c 4 files changed, 52 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38726/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 9bcb4a3..4dd5aaf 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1472,6 +1472,31 @@ return 0; } +int google_chromeec_set_early_tcss_state(int port, int state) +{ + struct ec_params_usb_pd_set_tcss_state params = { + .port = port, + .tcss_state = state, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_USB_PD_SET_TCSS_STATE, + .cmd_version = 0, + .cmd_data_in = &params, + .cmd_size_in = sizeof(params), + .cmd_data_out = NULL, + .cmd_dev_index = 0, + }; + + int rv; + + rv = google_chromeec_command(&cmd); + if (rv) + return rv; + + return 0; +} + + void google_chromeec_init(void) { google_chromeec_log_uptimeinfo(); diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f25c0b3..9c66037 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -49,6 +49,9 @@ uint8_t google_chromeec_pd_get_port_info(int port); /* Returns data role and type of device connected */ int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, int *dp_mode); +/* Set the TCSS early init state */ +int google_chromeec_set_early_tcss_state(int port, int state); + int google_chromeec_wait_for_displayport(long timeout); /* Device events */ diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index ace8e05..f84eb99 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -5249,7 +5249,7 @@ char state[32]; uint8_t cc_state; /* enum pd_cc_states representing cc state */ uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ - uint8_t reserved; /* Reserved for future use */ + uint8_t tcss_state; /* Early boot state of Type-C Sub Systems */ uint8_t control_flags; /* USB_PD_CTRL_*flags */ uint8_t cable_speed; /* TBT_SS_* cable speed */ uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ @@ -5318,6 +5318,18 @@ uint8_t port_count; } __ec_align1; +/* + * This command synchronizes the coreboot and Kernel TCSS (Type-C Sub Systems) + * states by saving the coreboot's early boot TCSS state of USB-C ports. When + * the Kernel boots, it determines the next TCSS state based on the coreboot's + * early boot state available in EC. + */ +#define EC_CMD_USB_PD_SET_TCSS_STATE 0x0106 +struct ec_params_usb_pd_set_tcss_state { + uint8_t port; + uint8_t tcss_state; +} __ec_align1; + /* Write USB-PD device FW */ #define EC_CMD_USB_PD_FW_UPDATE 0x0110 diff --git a/src/soc/intel/tigerlake/early_tcss.c b/src/soc/intel/tigerlake/early_tcss.c index 8965f0b..4dbb2a1 100644 --- a/src/soc/intel/tigerlake/early_tcss.c +++ b/src/soc/intel/tigerlake/early_tcss.c @@ -28,6 +28,8 @@ #define USB_PD_MUX_TBT_ACTIVE_CABLE BIT(0) /* Active/Passive Cable */ +#define TCSS_PORT_SET 0x1 + /* DP Mode pin definitions */ #define MODE_DP_PIN_A BIT(0) #define MODE_DP_PIN_B BIT(1) @@ -64,6 +66,7 @@ uint32_t tcss_res = 0; int req_size; int ret = 0; + int port_state = 0; /* Set the PMC IPC command to USB and Sub Command to 0 */ cmd.ipc_cmd.cmd = PMC_IPC_USBC_CMD_ID; @@ -86,6 +89,7 @@ memcpy(wbuf, tcss_req, req_size); cmd.ipc_cmd.len = req_size; + port_state = TCSS_PORT_SET; ret = pmc_send_ipc_cmd(&cmd.cmd, req_size, wbuf, rbuf); } @@ -115,6 +119,7 @@ memcpy(wbuf, tcss_req, req_size); cmd.ipc_cmd.len = req_size; + port_state = TCSS_PORT_SET; ret = pmc_send_ipc_cmd(&cmd.cmd, req_size, wbuf, rbuf); } @@ -122,6 +127,12 @@ if (ret) printk(BIOS_ERR, "Port %d mux set failed with error %d\n", port, ret); + if (port_state) + ret = google_chromeec_set_early_tcss_state(port, port_state); + + if (ret) + printk(BIOS_ERR, "Port %d flag was not correctly set by ec\n", port); + printk(BIOS_DEBUG, "Port %d tcss_res=0x%x", port, tcss_res); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfc1e6515411fab75b7da1b60775c26d17089c1c Gerrit-Change-Number: 38726 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2020