coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block: tco: enable intruder SMI
by Aaron Durbin (Code Review) 05 Mar '20

05 Mar '20

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39264 ) Change subject: soc/intel/common/block: tco: enable intruder SMI ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/39264/5/src/soc/intel/common/block… File src/soc/intel/common/block/smbus/tco.c: https://review.coreboot.org/c/coreboot/+/39264/5/src/soc/intel/common/block… PS5, Line 105: /* Make TCO issue an SMI on INTRD_DET assertion */ > not sure if I got this right; you would like to have multiple options, one for TCO SMI general and o […] We can start with one option, TCO SMI, but if there's ever a case where people would like more granularity then we can add more. -- To view, visit https://review.coreboot.org/c/coreboot/+/39264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7 Gerrit-Change-Number: 39264 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Mar 2020 17:15:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede Add Audio support for waddledoo
by Varshit B Pandya (Code Review) 05 Mar '20

05 Mar '20

Hello Usha P, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39322 to review the following change. Change subject: mb/google/dedede Add Audio support for waddledoo ...................................................................... mb/google/dedede Add Audio support for waddledoo 1. Configure Audio GPIOs. 2. Set i2c4 configuration. Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Signed-off-by: Yong Zhi <yong.zhi(a)intel.com> Change-Id: Ic0516c7a8fee79ce17343a7f42895d6ef534fec9 Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: Ic3dc7e199a74ff5335ce3e9f490629a01438d576 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 66 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/39322/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index ebca580..cfb8813 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,5 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI @@ -14,7 +16,6 @@ select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select SOC_INTEL_JASPERLAKE - if BOARD_GOOGLE_BASEBOARD_DEDEDE config BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 8049040..1e5f859 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -13,6 +13,19 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { + /* R0 : I2S_HP_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : I2S_HP_LRCK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : I2S_HP_AUDIO */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + /* R3 : I2S_HP_MIC */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R6 : I2S_SPK_LRCK */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1), + /* R7 : I2S_SPK_AUDIO */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1), + /* GPP_A0 thru GPP_A6 come configured out of reset, do not touch */ /* A0 : ESPI_IO0 */ /* A1 : ESPI_IO1 */ @@ -47,6 +60,15 @@ /* B23 : EC_AP_USB_C1_HDMI_HPD */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), + /* S2 : DMIC_CLK_1 */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* S3 : DMIC_DATA_1 */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* S6 : DMIC_CLK_0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : DMIC_DATA_0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + /* C0 : RAM_STRAP_0 */ PAD_CFG_GPI(GPP_C0, NONE, DEEP), /* C3 : RAM_STRAP_1 */ @@ -72,6 +94,13 @@ /* C23 : UART2_CTS_N */ PAD_NC(GPP_C23, DN_20K), + /* D16 : HP_INT_ODL*/ + PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, EDGE_BOTH), + /* D17 : EN_SPK */ + PAD_CFG_GPO(GPP_D17, 1, PLTRST), + /* D18 : I2S_MCLK */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* F7 : EMMC_CMD */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : EMMC_DATA0 */ @@ -126,6 +155,8 @@ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* H9 : AP_I2C_AUDIO_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H15 : I2S_SPK_BCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 061a0f8..87dd187 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -36,6 +36,12 @@ }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } }, }" device domain 0 on @@ -49,5 +55,32 @@ device i2c 15 on end end end #I2C 0 + device pci 19.0 on + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/39322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dc7e199a74ff5335ce3e9f490629a01438d576 Gerrit-Change-Number: 39322 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/tco: clear TCO1_STS register, too
by Aaron Durbin (Code Review) 05 Mar '20

05 Mar '20

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39259 ) Change subject: soc/intel/common/block/tco: clear TCO1_STS register, too ...................................................................... Patch Set 2: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/39259/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39259/2//COMMIT_MSG@16 PS2, Line 16: the SMI handler by unconditionally (re)setting it. > The problem was that the same variable (tco2_sts) was used for resetting and returning the set SMIs. […] Makes sense. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/39259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia57c203a672fdd0095355a7e2a0e01aaa6657968 Gerrit-Change-Number: 39259 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Mar 2020 16:26:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Add SSDT generator for ChromeOS EC
by Tim Wawrzynczak (Code Review) 05 Mar '20

05 Mar '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38541 ) Change subject: ec/google/chromeec: Add SSDT generator for ChromeOS EC ...................................................................... ec/google/chromeec: Add SSDT generator for ChromeOS EC Newer versions of the Linux kernel would like to consume information about the USB PD ports that are attached to the device. This information is obtained from the CrOS EC and exposed in the SSDT ACPI table. Also, the device enable for this PCI device was moved from ec_lpc.c to ec.c, where this new generic code can live, and allows bus-specific code to still call functions on device enable (so that PnP enable for the LPC device still gets called). BUG=b:146506369 BRANCH=none TEST=Verify the SSDT contains the expected information Change-Id: I729caecd64d9320fb02c0404c8315122f010970b Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_lpc.c 3 files changed, 177 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38541/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 7a4f27f..5548541 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -38,6 +38,9 @@ #define INVALID_HCMD 0xFF +#define GOOGLE_CHROMEEC_USBC_DEVICE_HID "GOOG0014" +#define GOOGLE_CHROMEEC_USBC_DEVICE_NAME "USBC" + /* * Map UHEPI masks to non UHEPI commands in order to support old EC FW * which does not support UHEPI command. @@ -1568,3 +1571,169 @@ return 1; } + + + +#if !DEVTREE_EARLY +static const char *google_chromeec_acpi_name(const struct device *dev) +{ + return "EC0"; +} + +static const char *power_role_to_str(enum ec_pd_power_role_caps power_role) +{ + switch (power_role) { + case EC_PD_POWER_ROLE_SOURCE: + return "source"; + case EC_PD_POWER_ROLE_SINK: + return "sink"; + case EC_PD_POWER_ROLE_DUAL: + return "dual"; + default: + return "unknown"; + } +} + +static const char *try_power_role_to_str( + enum ec_pd_try_power_role_caps try_power_role) +{ + switch (try_power_role) { + case EC_PD_TRY_POWER_ROLE_NONE: + return "none"; + case EC_PD_TRY_POWER_ROLE_SINK: + return "sink"; + case EC_PD_TRY_POWER_ROLE_SOURCE: + return"source"; + default: + return "unknown"; + } +} + +static const char *data_role_to_str(enum ec_pd_data_role_caps data_role) +{ + switch (data_role) { + case EC_PD_DATA_ROLE_DFP: + return "dfp"; + case EC_PD_DATA_ROLE_UFP: + return "ufp"; + case EC_PD_DATA_ROLE_DUAL: + return "dual"; + default: + return "unknown"; + } +} + +static const char *port_location_to_str(enum ec_pd_port_location port_location) +{ + switch (port_location) { + case EC_PD_PORT_LOCATION_LEFT: + return "LEFT"; + case EC_PD_PORT_LOCATION_RIGHT: + return "RIGHT"; + case EC_PD_PORT_LOCATION_BACK: + return "BACK"; + case EC_PD_PORT_LOCATION_FRONT: + return "FRONT"; + case EC_PD_PORT_LOCATION_LEFT_FRONT: + return "LEFT_FRONT"; + case EC_PD_PORT_LOCATION_LEFT_BACK: + return "LEFT_BACK"; + case EC_PD_PORT_LOCATION_RIGHT_FRONT: + return "RIGHT_FRONT"; + case EC_PD_PORT_LOCATION_RIGHT_BACK: + return "RIGHT_BACK"; + case EC_PD_PORT_LOCATION_BACK_LEFT: + return "BACK_LEFT"; + case EC_PD_PORT_LOCATION_BACK_RIGHT: + return "BACK_RIGHT"; + case EC_PD_PORT_LOCATION_UNKNOWN: /* intentional fallthrough */ + default: + return "UNKNOWN"; + } +} + +static void google_chromeec_fill_ssdt_generator(struct device *dev) +{ + /*struct ec_response_usb_pd_power_info port_info;*/ + enum ec_pd_power_role_caps power_role_cap; + enum ec_pd_try_power_role_caps try_power_role_cap; + enum ec_pd_data_role_caps data_role_cap; + enum ec_pd_port_location port_location; + struct acpi_dp *dsd = NULL; + char con_name[] = "CON0"; + int rv; + int i; + int num_ports = 0; + const char *scope = acpi_device_path(dev); + + acpigen_write_scope(scope); + acpigen_write_device(GOOGLE_CHROMEEC_USBC_DEVICE_NAME); + acpigen_write_name_string("_HID", GOOGLE_CHROMEEC_USBC_DEVICE_HID); + acpigen_write_name_string("_DDN", "ChromeOS EC Embedded Controller " + "USB Type-C Control"); + + rv = google_chromeec_get_num_pd_ports(&num_ports); + if (rv) + return; + + for (i = 0; i < num_ports; ++i) { + rv = google_chromeec_get_pd_port_caps(i, + &power_role_cap, + &try_power_role_cap, + &data_role_cap, + &port_location); + if (rv) + continue; + + con_name[3] = (char)i + '0'; + acpigen_write_device(con_name); + acpigen_write_name_integer("_ADR", (uint64_t)i); + + /* _DSD */ + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_integer(dsd, "port-number", (uint64_t)i); + acpi_dp_add_string(dsd, "power-role", + power_role_to_str(power_role_cap)); + + if (try_power_role_cap != EC_PD_TRY_POWER_ROLE_NONE) + acpi_dp_add_string(dsd, "try-power-role", + try_power_role_to_str(try_power_role_cap)); + + acpi_dp_add_string(dsd, "data-role", + data_role_to_str(data_role_cap)); + acpi_dp_add_string(dsd, "port-location", + port_location_to_str(port_location)); + + acpi_dp_write(dsd); + acpigen_pop_len(); /* Device */ + } + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +__weak void google_ec_enable_extra(struct device *dev) +{ +} + +static struct device_operations ec_chromeec_ops = { +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = google_chromeec_acpi_name, + .acpi_fill_ssdt_generator = google_chromeec_fill_ssdt_generator, +#endif /* #if CONFIG(HAVE_ACPI_TABLES) */ +}; +#endif /* #if !DEVTREE_EARLY */ + +static void google_chromeec_enable(struct device *dev) +{ +#if !DEVTREE_EARLY + dev->ops = &ec_chromeec_ops; +#endif + + google_ec_enable_extra(dev); +} + +struct chip_operations ec_google_chromeec_ops = { + CHIP_NAME("ChromeOS EC") + .enable_dev = google_chromeec_enable +}; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 8051486..adb961a 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -18,6 +18,7 @@ #ifndef _EC_GOOGLE_CHROMEEC_EC_H #define _EC_GOOGLE_CHROMEEC_EC_H #include <types.h> +#include <device/device.h> #include "ec_commands.h" /* Fill in base and size of the IO port resources used. */ @@ -323,4 +324,10 @@ enum ec_pd_try_power_role_caps *try_power_role_cap, enum ec_pd_data_role_caps *data_role_cap, enum ec_pd_port_location *port_location); + +/** + * Allows bus-specific EC code to perform actions when the device is enabled. + */ +void google_ec_enable_extra(struct device *dev); + #endif /* _EC_GOOGLE_CHROMEEC_EC_H */ diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 6bc4fbd..9afb1fd 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -458,16 +458,11 @@ { NULL, 0, 0, 0, } }; -static void enable_dev(struct device *dev) +void google_ec_enable_extra(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -struct chip_operations ec_google_chromeec_ops = { - CHIP_NAME("Google Chrome EC") - .enable_dev = enable_dev, -}; - static int google_chromeec_data_ready(u16 port) { return google_chromeec_status_check(port, EC_LPC_CMDR_DATA, -- To view, visit https://review.coreboot.org/c/coreboot/+/38541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I729caecd64d9320fb02c0404c8315122f010970b Gerrit-Change-Number: 38541 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/apl: add options to override USB port config
by Maxim Polyakov (Code Review) 05 Mar '20

05 Mar '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38815 ) Change subject: soc/apl: add options to override USB port config ...................................................................... Patch Set 18: (2 comments) https://review.coreboot.org/c/coreboot/+/38815/17//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38815/17//COMMIT_MSG@9 PS17, Line 9: overload > override? Done https://review.coreboot.org/c/coreboot/+/38815/17/src/soc/intel/apollolake/… File src/soc/intel/apollolake/chip.c: https://review.coreboot.org/c/coreboot/+/38815/17/src/soc/intel/apollolake/… PS17, Line 571: cfg->usb2_port[port].oc_pin; > Does this fit into 96 characters? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia94a2be1647f7743ef0c918ae3b34437a179261c Gerrit-Change-Number: 38815 Gerrit-PatchSet: 18 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Mar 2020 16:12:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/up/squared: remove NpkEn option from romstage
by Maxim Polyakov (Code Review) 05 Mar '20

05 Mar '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39120 ) Change subject: mb/up/squared: remove NpkEn option from romstage ...................................................................... Patch Set 11: (2 comments) https://review.coreboot.org/c/coreboot/+/39120/10//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39120/10//COMMIT_MSG@10 PS10, Line 10: device tree > nit: devicetree Done https://review.coreboot.org/c/coreboot/+/39120/10//COMMIT_MSG@10 PS10, Line 10: if > s/if/since Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I429f1129dc4149067503cd2ff9fb4c76cdc919f0 Gerrit-Change-Number: 39120 Gerrit-PatchSet: 11 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 05 Mar 2020 16:11:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron/mal10: Add COMe-mAL10 minimal support
by Maxim Polyakov (Code Review) 05 Mar '20

05 Mar '20

Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Angel Pons, Andrey Petrov, Patrick Rudolph, Aaron Durbin, Lance Zhao, Nico Huber, Martin Roth, Werner Zeh, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39133 to look at the new patch set (#11). Change subject: mb/kontron/mal10: Add COMe-mAL10 minimal support ...................................................................... mb/kontron/mal10: Add COMe-mAL10 minimal support This patch adds minimal support for the Kontron COMe-mAL10 module with the Apollo Lake processor together with Kontron T10-TNI carrierboard. Working: - console (Kontron CPLD) - USB2/3 - Ethernet network - eMMC - SATA - PCIe ports - Video/DP (*) Not tested: - Video/LVDS TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) - SDIO - Documentation As the payload was used: - Tianocore (*)(**) - SeaBIOS (*) (*) Video works only in linux (**) Works only with Tianocore "UEFIPayload" payload edk2-stable201903-1569-g3e63a91 (**) Booting with the "CorebootPayload" crashes: https://pastebin.com/cpCfrPCL Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A src/mainboard/kontron/mal10/Kconfig A src/mainboard/kontron/mal10/Kconfig.name A src/mainboard/kontron/mal10/Makefile.inc A src/mainboard/kontron/mal10/acpi/dptf.asl A src/mainboard/kontron/mal10/board_info.txt A src/mainboard/kontron/mal10/bootblock.c A src/mainboard/kontron/mal10/cmos.default A src/mainboard/kontron/mal10/cmos.layout A src/mainboard/kontron/mal10/data.vbt A src/mainboard/kontron/mal10/dsdt.asl A src/mainboard/kontron/mal10/gma-mainboard.ads A src/mainboard/kontron/mal10/gpio.h A src/mainboard/kontron/mal10/mal10.fmd A src/mainboard/kontron/mal10/ramstage.c A src/mainboard/kontron/mal10/romstage.c A src/mainboard/kontron/mal10/variants/baseboard/devicetree.cb A src/mainboard/kontron/mal10/variants/t10-tni/overridetree.cb 17 files changed, 1,151 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39133/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 11 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/apl: add options to override USB port config
by Maxim Polyakov (Code Review) 05 Mar '20

05 Mar '20

Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Andrey Petrov, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38815 to look at the new patch set (#18). Change subject: soc/apl: add options to override USB port config ...................................................................... soc/apl: add options to override USB port config Allows to override the PortUsb20Enable and PortUsb30Enable FSP options (which are set to 1 by default) to enable/disable USB ports if the usb_config_override flag is set to "1". Therefore, these changes will not affect other boards with an Apollo Lake processor. Change-Id: Ia94a2be1647f7743ef0c918ae3b34437a179261c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/include/soc/usb.h 3 files changed, 47 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/38815/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/38815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia94a2be1647f7743ef0c918ae3b34437a179261c Gerrit-Change-Number: 38815 Gerrit-PatchSet: 18 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: security/vboot: Support enabling EC EFS with EC software sync
by Tim Wawrzynczak (Code Review) 05 Mar '20

05 Mar '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39272 ) Change subject: security/vboot: Support enabling EC EFS with EC software sync ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I697e90748e19d15af154011413b30c0f2a0bf52e Gerrit-Change-Number: 39272 Gerrit-PatchSet: 2 Gerrit-Owner: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Mar 2020 15:42:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in libgfxinit[master]: gma bxt panel: Allow to use secondary panel control logic
by Nico Huber (Code Review) 05 Mar '20

05 Mar '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/38276 ) Change subject: gma bxt panel: Allow to use secondary panel control logic ...................................................................... gma bxt panel: Allow to use secondary panel control logic Broxton has control logic for two panels. Reflect that. Change-Id: Ie84d21a07a0f064f993a54b277e051b8d1ca541c Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/Makefile.inc M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-panel.adb M common/hw-gfx-gma.ads M configs/broxton 5 files changed, 113 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/76/38276/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index 9378f41..af6dc11 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -47,10 +47,13 @@ gfxinit-y += hw-gfx-framebuffer_filler.adb gfxinit-y += hw-gfx-framebuffer_filler.ads +CONFIG_GFX_GMA_PANEL_2_PORT ?= Disabled + CONFIG_GFX_GMA_GENERATION := $(call strip_quotes,$(CONFIG_GFX_GMA_GENERATION)) CONFIG_GFX_GMA_CPU := $(call strip_quotes,$(CONFIG_GFX_GMA_CPU)) CONFIG_GFX_GMA_CPU_VARIANT := $(call strip_quotes,$(CONFIG_GFX_GMA_CPU_VARIANT)) CONFIG_GFX_GMA_PANEL_1_PORT := $(call strip_quotes,$(CONFIG_GFX_GMA_PANEL_1_PORT)) +CONFIG_GFX_GMA_PANEL_2_PORT := $(call strip_quotes,$(CONFIG_GFX_GMA_PANEL_2_PORT)) CONFIG_GFX_GMA_ANALOG_I2C_PORT := $(call strip_quotes,$(CONFIG_GFX_GMA_ANALOG_I2C_PORT)) _GEN_NONCONST := $(strip \ @@ -73,6 +76,7 @@ printf " GENERATE $(patsubst /%,%,$(subst $(obj)/,,$@))\n" sed -e's/<<GEN>>/$(CONFIG_GFX_GMA_GENERATION)/' \ -e's/<<PANEL_1_PORT>>/$(CONFIG_GFX_GMA_PANEL_1_PORT)/' \ + -e's/<<PANEL_2_PORT>>/$(CONFIG_GFX_GMA_PANEL_2_PORT)/' \ -e's/<<ANALOG_I2C_PORT>>/$(CONFIG_GFX_GMA_ANALOG_I2C_PORT)/' \ -e's/<<DEFAULT_MMIO_BASE>>/$(CONFIG_GFX_GMA_DEFAULT_MMIO)/' \ -e'/constant Gen_CPU$_Var$\?/d' \ @@ -91,6 +95,7 @@ -e's/<<CPU>>/$(CONFIG_GFX_GMA_CPU)/' \ -e's/<<CPU_VARIANT>>/$(CONFIG_GFX_GMA_CPU_VARIANT)/' \ -e's/<<PANEL_1_PORT>>/$(CONFIG_GFX_GMA_PANEL_1_PORT)/' \ + -e's/<<PANEL_2_PORT>>/$(CONFIG_GFX_GMA_PANEL_2_PORT)/' \ -e's/<<ANALOG_I2C_PORT>>/$(CONFIG_GFX_GMA_ANALOG_I2C_PORT)/' \ -e's/<<DEFAULT_MMIO_BASE>>/$(CONFIG_GFX_GMA_DEFAULT_MMIO)/' \ -e":s$$(printf '\n ')/,$$/{N;s/,\n.*Dyn_CPU$_Var$\?[^,)]*//;ts$$(printf '\n ')P;D;}" \ diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 39fa825..8cd3cff 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -44,7 +44,8 @@ CPU_Var : constant Gen_CPU_Variant := <<CPU_VARIANT>>; Panel_Ports : constant array (Valid_Panels) of Port_Type := - (Panel_1 => <<PANEL_1_PORT>>); + (Panel_1 => <<PANEL_1_PORT>>, + Panel_2 => <<PANEL_2_PORT>>); Analog_I2C_Port : constant PCH_Port := <<ANALOG_I2C_PORT>>; diff --git a/common/hw-gfx-gma-panel.adb b/common/hw-gfx-gma-panel.adb index 36faf31..ad4d45b 100644 --- a/common/hw-gfx-gma-panel.adb +++ b/common/hw-gfx-gma-panel.adb @@ -38,7 +38,7 @@ BL_Off_To_Power_Down => 50_000, Power_Cycle_Delay => 510_000); - Delays_US : Panel_Power_Delays; + Delays_US : array (Valid_Panels) of Panel_Power_Delays; ---------------------------------------------------------------------------- @@ -53,8 +53,9 @@ -- and the hardware power sequencer. The latter option would be less error -- prone, as the hardware might just don't work as expected. - Power_Cycle_Timer : Time.T; - Power_Up_Timer : Time.T; + type Panel_Times is array (Valid_Panels) of Time.T; + Power_Cycle_Timer : Panel_Times; + Power_Up_Timer : Panel_Times; ---------------------------------------------------------------------------- @@ -99,18 +100,28 @@ DIVISOR : Registers.Registers_Index; end record; - Panel_PP_Regs : constant PP_Regs := (if Config.Has_PCH_Panel_Power then - (STATUS => Registers.PCH_PP_STATUS, - CONTROL => Registers.PCH_PP_CONTROL, - ON_DELAYS => Registers.PCH_PP_ON_DELAYS, - OFF_DELAYS => Registers.PCH_PP_OFF_DELAYS, - DIVISOR => Registers.PCH_PP_DIVISOR) - else - (STATUS => Registers.GMCH_PP_STATUS, - CONTROL => Registers.GMCH_PP_CONTROL, - ON_DELAYS => Registers.GMCH_PP_ON_DELAYS, - OFF_DELAYS => Registers.GMCH_PP_OFF_DELAYS, - DIVISOR => Registers.GMCH_PP_DIVISOR)); + PP : constant array (Valid_Panels) of PP_Regs := + (if Config.Has_PCH_Panel_Power then + (Panel_1 => + (STATUS => Registers.PCH_PP_STATUS, + CONTROL => Registers.PCH_PP_CONTROL, + ON_DELAYS => Registers.PCH_PP_ON_DELAYS, + OFF_DELAYS => Registers.PCH_PP_OFF_DELAYS, + DIVISOR => Registers.PCH_PP_DIVISOR), + Panel_2 => + (STATUS => Registers.BXT_PP_STATUS_2, + CONTROL => Registers.BXT_PP_CONTROL_2, + ON_DELAYS => Registers.BXT_PP_ON_DELAYS_2, + OFF_DELAYS => Registers.BXT_PP_OFF_DELAYS_2, + DIVISOR => Registers.PCH_PP_DIVISOR)) -- won't be used + + else + (Panel_1 .. Panel_2 => + (STATUS => Registers.GMCH_PP_STATUS, + CONTROL => Registers.GMCH_PP_CONTROL, + ON_DELAYS => Registers.GMCH_PP_ON_DELAYS, + OFF_DELAYS => Registers.GMCH_PP_OFF_DELAYS, + DIVISOR => Registers.GMCH_PP_DIVISOR))); function PCH_PP_ON_DELAYS_PWR_UP (US : Natural) return Word32 is begin @@ -162,6 +173,22 @@ BXT_BLC_PWM_CTL_ENABLE : constant := 16#00_0001# * 2 ** 31; + type BLC_Regs is record + CTL : Registers.Registers_Index; + FREQ : Registers.Registers_Index; + DUTY : Registers.Registers_Index; + end record; + + BLC : constant array (Valid_Panels) of BLC_Regs := + (Panel_1 => + (CTL => Registers.BXT_BLC_PWM_CTL_1, + FREQ => Registers.BXT_BLC_PWM_FREQ_1, + DUTY => Registers.BXT_BLC_PWM_DUTY_1), + Panel_2 => + (CTL => Registers.BXT_BLC_PWM_CTL_2, + FREQ => Registers.BXT_BLC_PWM_FREQ_2, + DUTY => Registers.BXT_BLC_PWM_DUTY_2)); + ---------------------------------------------------------------------------- procedure Static_Init @@ -171,10 +198,10 @@ Input => (Time.State)) is begin - Power_Cycle_Timer := Time.Now; + Power_Cycle_Timer := (others => Time.Now); Power_Up_Timer := Power_Cycle_Timer; - Delays_US := Default_EDP_Delays_US; + Delays_US := (others => Default_EDP_Delays_US); end Static_Init; ---------------------------------------------------------------------------- @@ -191,7 +218,7 @@ end loop; end Check_PP_Delays; - procedure Setup_PP_Sequencer (Default_Delays : Boolean := False) + procedure Setup_PP_Sequencer (Panel : Valid_Panels; Default_Delays : Boolean) is Power_Delay, Port_Select : Word32; @@ -199,35 +226,34 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Static_Init; - if Default_Delays then Override_Delays := True; else - Registers.Read (Panel_PP_Regs.ON_DELAYS, Power_Delay); - Delays_US (Power_Up_Delay) := 100 * Natural + Registers.Read (PP (Panel).ON_DELAYS, Power_Delay); + Delays_US (Panel) (Power_Up_Delay) := 100 * Natural (Shift_Right (Power_Delay and PCH_PP_ON_DELAYS_PWR_UP_MASK, 16)); - Delays_US (Power_Up_To_BL_On) := 100 * Natural + Delays_US (Panel) (Power_Up_To_BL_On) := 100 * Natural (Power_Delay and PCH_PP_ON_DELAYS_PWR_UP_BL_ON_MASK); - Registers.Read (Panel_PP_Regs.OFF_DELAYS, Power_Delay); - Delays_US (Power_Down_Delay) := 100 * Natural + Registers.Read (PP (Panel).OFF_DELAYS, Power_Delay); + Delays_US (Panel) (Power_Down_Delay) := 100 * Natural (Shift_Right (Power_Delay and PCH_PP_OFF_DELAYS_PWR_DOWN_MASK, 16)); - Delays_US (BL_Off_To_Power_Down) := 100 * Natural + Delays_US (Panel) (BL_Off_To_Power_Down) := 100 * Natural (Power_Delay and PCH_PP_OFF_DELAYS_BL_OFF_PWR_DOWN_MASK); if Config.Has_PP_Divisor_Reg then - Registers.Read (Panel_PP_Regs.DIVISOR, Power_Delay); + Registers.Read (PP (Panel).DIVISOR, Power_Delay); else - Registers.Read (Panel_PP_Regs.CONTROL, Power_Delay); - Power_Delay := Shift_Right (Power_Delay, BXT_PP_CONTROL_PWR_CYC_DELAY_SHIFT); + Registers.Read (PP (Panel).CONTROL, Power_Delay); + Power_Delay := Shift_Right + (Power_Delay, BXT_PP_CONTROL_PWR_CYC_DELAY_SHIFT); end if; if (Power_Delay and PCH_PP_DIVISOR_PWR_CYC_DELAY_MASK) > 1 then - Delays_US (Power_Cycle_Delay) := 100_000 * (Natural + Delays_US (Panel) (Power_Cycle_Delay) := 100_000 * (Natural (Power_Delay and PCH_PP_DIVISOR_PWR_CYC_DELAY_MASK) - 1); end if; - Check_PP_Delays (Delays_US, Override_Delays); + Check_PP_Delays (Delays_US (Panel), Override_Delays); end if; if Override_Delays then @@ -245,51 +271,65 @@ -- Force power-up to backlight-on delay to 100us as recommended by PRM. Registers.Unset_And_Set_Mask - (Register => Panel_PP_Regs.ON_DELAYS, + (Register => PP (Panel).ON_DELAYS, Mask_Unset => PCH_PP_ON_DELAYS_PORT_SELECT_MASK or PCH_PP_ON_DELAYS_PWR_UP_MASK or PCH_PP_ON_DELAYS_PWR_UP_BL_ON_MASK, Mask_Set => Port_Select or - PCH_PP_ON_DELAYS_PWR_UP (Delays_US (Power_Up_Delay)) + PCH_PP_ON_DELAYS_PWR_UP + (Delays_US (Panel) (Power_Up_Delay)) or PCH_PP_ON_DELAYS_PWR_UP_BL_ON (100)); Registers.Unset_And_Set_Mask - (Register => Panel_PP_Regs.OFF_DELAYS, + (Register => PP (Panel).OFF_DELAYS, Mask_Unset => PCH_PP_OFF_DELAYS_PWR_DOWN_MASK or PCH_PP_OFF_DELAYS_BL_OFF_PWR_DOWN_MASK, Mask_Set => PCH_PP_OFF_DELAYS_PWR_DOWN - (Delays_US (Power_Down_Delay)) or + (Delays_US (Panel) (Power_Down_Delay)) or PCH_PP_OFF_DELAYS_BL_OFF_PWR_DOWN - (Delays_US (BL_Off_To_Power_Down))); + (Delays_US (Panel) (BL_Off_To_Power_Down))); if Config.Has_PP_Divisor_Reg then Registers.Unset_And_Set_Mask - (Register => Panel_PP_Regs.DIVISOR, + (Register => PP (Panel).DIVISOR, Mask_Unset => PCH_PP_DIVISOR_PWR_CYC_DELAY_MASK, Mask_Set => PCH_PP_DIVISOR_PWR_CYC_DELAY - (Delays_US (Power_Cycle_Delay))); + (Delays_US (Panel) (Power_Cycle_Delay))); else Registers.Unset_And_Set_Mask - (Register => Panel_PP_Regs.CONTROL, + (Register => PP (Panel).CONTROL, Mask_Unset => BXT_PP_CONTROL_PWR_CYC_DELAY_MASK, Mask_Set => BXT_PP_CONTROL_PWR_CYC_DELAY - (Delays_US (Power_Cycle_Delay))); + (Delays_US (Panel) (Power_Cycle_Delay))); end if; end if; if Config.Has_PP_Write_Protection then Registers.Unset_And_Set_Mask - (Register => Panel_PP_Regs.CONTROL, + (Register => PP (Panel).CONTROL, Mask_Unset => PCH_PP_CONTROL_WRITE_PROTECT_MASK, Mask_Set => PCH_PP_CONTROL_WRITE_PROTECT_KEY or PCH_PP_CONTROL_POWER_DOWN_ON_RESET); else Registers.Set_Mask - (Register => Panel_PP_Regs.CONTROL, + (Register => PP (Panel).CONTROL, Mask => PCH_PP_CONTROL_POWER_DOWN_ON_RESET); end if; end Setup_PP_Sequencer; + procedure Setup_PP_Sequencer (Default_Delays : Boolean := False) is + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + Static_Init; + + for Panel in Valid_Panels loop + if Config.Panel_Ports (Panel) /= Disabled then + Setup_PP_Sequencer (Panel, Default_Delays); + end if; + end loop; + end Setup_PP_Sequencer; + ---------------------------------------------------------------------------- procedure VDD_Override (Panel : Panel_Control) is @@ -317,14 +357,15 @@ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Registers.Is_Set_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_TARGET_ON, Was_On); + Registers.Is_Set_Mask (PP (Panel).CONTROL, PCH_PP_CONTROL_TARGET_ON, Was_On); if not Was_On then - Time.Delay_Until (Power_Cycle_Timer); + Time.Delay_Until (Power_Cycle_Timer (Panel)); end if; - Registers.Set_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_TARGET_ON); + Registers.Set_Mask (PP (Panel).CONTROL, PCH_PP_CONTROL_TARGET_ON); if not Was_On then - Power_Up_Timer := Time.US_From_Now (Delays_US (Power_Up_Delay)); + Power_Up_Timer (Panel) := + Time.US_From_Now (Delays_US (Panel) (Power_Up_Delay)); end if; if Wait then Wait_On (Panel); @@ -339,13 +380,13 @@ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Time.Delay_Until (Power_Up_Timer); + Time.Delay_Until (Power_Up_Timer (Panel)); Registers.Wait_Unset_Mask - (Register => Panel_PP_Regs.STATUS, + (Register => PP (Panel).STATUS, Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK, TOut_MS => 300); - Registers.Unset_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_VDD_OVERRIDE); + Registers.Unset_Mask (PP (Panel).CONTROL, PCH_PP_CONTROL_VDD_OVERRIDE); end Wait_On; procedure Off (Panel : Panel_Control) @@ -358,20 +399,21 @@ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Registers.Is_Set_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_TARGET_ON, Was_On); + Registers.Is_Set_Mask (PP (Panel).CONTROL, PCH_PP_CONTROL_TARGET_ON, Was_On); Registers.Unset_Mask - (Register => Panel_PP_Regs.CONTROL, + (Register => PP (Panel).CONTROL, Mask => PCH_PP_CONTROL_TARGET_ON or PCH_PP_CONTROL_VDD_OVERRIDE); if Was_On then - Time.U_Delay (Delays_US (Power_Down_Delay)); + Time.U_Delay (Delays_US (Panel) (Power_Down_Delay)); end if; Registers.Wait_Unset_Mask - (Register => Panel_PP_Regs.STATUS, + (Register => PP (Panel).STATUS, Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK, TOut_MS => 600); if Was_On then - Power_Cycle_Timer := Time.US_From_Now (Delays_US (Power_Cycle_Delay)); + Power_Cycle_Timer (Panel) := + Time.US_From_Now (Delays_US (Panel) (Power_Cycle_Delay)); end if; end Off; @@ -387,11 +429,11 @@ if Config.Has_New_Backlight_Control then Registers.Set_Mask - (Register => Registers.BXT_BLC_PWM_CTL_1, + (Register => BLC (Panel).CTL, Mask => BXT_BLC_PWM_CTL_ENABLE); else Registers.Set_Mask - (Register => Panel_PP_Regs.CONTROL, + (Register => PP (Panel).CONTROL, Mask => PCH_PP_CONTROL_BACKLIGHT_ENABLE); end if; end Backlight_On; @@ -406,11 +448,11 @@ if Config.Has_New_Backlight_Control then Registers.Unset_Mask - (Register => Registers.BXT_BLC_PWM_CTL_1, + (Register => BLC (Panel).CTL, Mask => BXT_BLC_PWM_CTL_ENABLE); else Registers.Unset_Mask - (Register => Panel_PP_Regs.CONTROL, + (Register => PP (Panel).CONTROL, Mask => PCH_PP_CONTROL_BACKLIGHT_ENABLE); end if; end Backlight_Off; @@ -424,7 +466,7 @@ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); if Config.Has_New_Backlight_Control then - Registers.Write (Registers.BXT_BLC_PWM_DUTY_1, Level); + Registers.Write (BLC (Panel).DUTY, Level); else Registers.Unset_And_Set_Mask (Register => Registers.BLC_PWM_CPU_CTL, @@ -443,7 +485,7 @@ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); if Config.Has_New_Backlight_Control then - Registers.Read (Registers.BXT_BLC_PWM_FREQ_1, Level); + Registers.Read (BLC (Panel).FREQ, Level); else Registers.Read (Registers.BLC_PWM_PCH_CTL2, Level); Level := Shift_Right (Level, PCH_BLC_PWM_CTL2_BL_MOD_FREQ_SHIFT); diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 0c44434..1215fc5 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -253,8 +253,8 @@ subtype PCH_HDMI_Port is PCH_Port range PCH_HDMI_B .. PCH_HDMI_D; subtype PCH_DP_Port is PCH_Port range PCH_DP_B .. PCH_DP_D; - type Panel_Control is (No_Panel, Panel_1); - subtype Valid_Panels is Panel_Control range Panel_1 .. Panel_1; + type Panel_Control is (No_Panel, Panel_1, Panel_2); + subtype Valid_Panels is Panel_Control range Panel_1 .. Panel_2; type Port_Config is record diff --git a/configs/broxton b/configs/broxton index 35a6f6c..5d3b859 100644 --- a/configs/broxton +++ b/configs/broxton @@ -2,6 +2,7 @@ CONFIG_GFX_GMA_GENERATION = Broxton CONFIG_GFX_GMA_CPU = Broxton CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A -CONFIG_GFX_GMA_PANEL_1_PORT = eDP +CONFIG_GFX_GMA_PANEL_1_PORT = Disabled +CONFIG_GFX_GMA_PANEL_2_PORT = eDP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# -- To view, visit https://review.coreboot.org/c/libgfxinit/+/38276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ie84d21a07a0f064f993a54b277e051b8d1ca541c Gerrit-Change-Number: 38276 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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coreboot-gerrit March 2020