Hello build bot (Jenkins), Edward O'Callaghan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39273
to look at the new patch set (#2).
Change subject: mb/google/hatch/puff: Enable VBOOT_EC_EFS
......................................................................
mb/google/hatch/puff: Enable VBOOT_EC_EFS
If the ChromeOS EC uses EC early firmware selection (EFS), the AP vboot
build must also enable EC EFS. Puff EC uses EFS, so enable it in the AP
vboot build.
BUG=b:150742950
TEST=Puff can boot with EC EFS with hardware write protect enabled
BRANCH=none
Signed-off-by: Sam McNally <sammc(a)chromium.org>
Change-Id: I0877000b7d277106436831f2d69775c25299da9e
---
M src/mainboard/google/hatch/Kconfig.name
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/39273/2
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Gerrit-Change-Id: I0877000b7d277106436831f2d69775c25299da9e
Gerrit-Change-Number: 39273
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Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Edward O'Callaghan, Tim Wawrzynczak, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39272
to look at the new patch set (#2).
Change subject: security/vboot: Support enabling EC EFS with EC software sync
......................................................................
security/vboot: Support enabling EC EFS with EC software sync
If the ChromeOS EC uses EC early firmware selection (EFS), the AP vboot
build must also enable EC EFS. Add an option to control this, passing it
through to vboot.
BUG=b:150742950
TEST=none
BRANCH=none
Signed-off-by: Sam McNally <sammc(a)chromium.org>
Change-Id: I697e90748e19d15af154011413b30c0f2a0bf52e
---
M src/security/vboot/Kconfig
M src/security/vboot/Makefile.inc
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/39272/2
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39265 )
Change subject: soc/intel/common/block/smm: add case intrusion to SMI handler
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39265/5/src/soc/intel/common/block…
File src/soc/intel/common/block/smm/smihandler.c:
https://review.coreboot.org/c/coreboot/+/39265/5/src/soc/intel/common/block…
PS5, Line 444: if (tco_sts & (TCO_INTRD_DET << 16)) { /* INTRUDER# assertion */
> Shouldn't all these events have optional callback instead of just printing things?
I had that idea, too, but I wasn't sure if anyone would be happy with introducing more weak functions
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39262 )
Change subject: intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs
......................................................................
Patch Set 5:
> Patch Set 5:
>
> > Patch Set 5:
> >
> > > Patch Set 4:
> > >
> > > > Patch Set 4:
> > > >
> > > > > Patch Set 4: Code-Review-1
> > > > >
> > > > > This should be made into an option. From a Chrome OS perspective we do not want to take SMIs for these events. It leads to having more complex handlers and the associated policy with them.
> > > >
> > > > What is Chrome OS using instead?
> > >
> > > We don't use TCO SMIs for anything. For intruder specifically we don't currently plumb anything up. For example, I don't want to take an SMI for a TCO timer expiration -- just want a reset on double expiration. Maybe we will in the future, but I don't want to enable TCO SMIs by default.
> >
> > Hm, but why can't you just ignore the fact that maybe SMI are raised? It doesn't interfere with anything, does it? Currently there is no functionality implemented but it's just a stub to make that possible.
> >
> > Don't get me wrong, I'm not against having an option for that. I just want to understand how that could affect Chrome OS or others.
>
> I don't like taking unnecessary SMIs as it steals cycles and it adds more attack surface area.
ack
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39264 )
Change subject: soc/intel/common/block: tco: enable intruder SMI
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39264/5/src/soc/intel/common/block…
File src/soc/intel/common/block/smbus/tco.c:
https://review.coreboot.org/c/coreboot/+/39264/5/src/soc/intel/common/block…
PS5, Line 105: /* Make TCO issue an SMI on INTRD_DET assertion */
> This should be driven by config policy as well -- falls under the broader TCO SMI option.
not sure if I got this right; you would like to have multiple options, one for TCO SMI general and one for each sub-SMI?
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39259 )
Change subject: soc/intel/common/block/tco: clear TCO1_STS register, too
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39259/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/39259/2//COMMIT_MSG@16
PS2, Line 16: the SMI handler by unconditionally (re)setting it.
> I don't see how your change is different than previous code in this regard. […]
The problem was that the same variable (tco2_sts) was used for resetting and returning the set SMIs. Since SECOND_TO_STS was set in tco2_sts, SECOND_TO_STS was always set when reaching the SMI handler, even when SECOND_TO_STS was never issued.
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