March 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: intel/soc: icl,cnl,apl,skl,tgl,common: enable TCO SMIs
by Michael Niewöhner (Code Review) March 4, 2020

March 4, 2020

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39262 ) Change subject: intel/soc: icl,cnl,apl,skl,tgl,common: enable TCO SMIs ...................................................................... Patch Set 4: > Patch Set 4: Code-Review-1 > > This should be made into an option. From a Chrome OS perspective we do not want to take SMIs for these events. It leads to having more complex handlers and the associated policy with them. What is Chrome OS using instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/39262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Gerrit-Change-Number: 39262 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 04 Mar 2020 18:55:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Fix potential NULL pointer dereferences and memory leak
by Francois Toguo Fotso (Code Review) March 4, 2020

March 4, 2020

Francois Toguo Fotso has uploaded a new patch set (#3) to the change originally created by Francois Toguo Fotso. ( https://review.coreboot.org/c/coreboot/+/30098 ) Change subject: Fix potential NULL pointer dereferences and memory leak ...................................................................... Fix potential NULL pointer dereferences and memory leak Found-by: Klockwork BUG=None TEST=Boot to OS Change-Id: I38a8910e68b7a8ce0e97ca4cdb9ef7f595c0e319 Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> --- M src/arch/x86/acpi_device.c M src/arch/x86/acpigen.c M src/include/nhlt.h M src/lib/nhlt.c M src/soc/intel/common/nhlt.c 5 files changed, 17 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30098/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/30098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38a8910e68b7a8ce0e97ca4cdb9ef7f595c0e319 Gerrit-Change-Number: 30098 Gerrit-PatchSet: 3 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mainboard/libretrend/lt1000: Initial commit
by Matt DeVillier (Code Review) March 4, 2020

March 4, 2020

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: src/mainboard/libretrend/lt1000: Initial commit ...................................................................... Patch Set 13: (2 comments) https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… File Documentation/mainboard/libretrend/lt1000.md: https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… PS13, Line 47: Fastboot > MRC cache to speed up ram training what data is missing that prevents this from working? https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… PS13, Line 62: - speakers and mic header > Actually, Linux is able to initialize the codec and the audio works somehow. […] System 76's coreboot-collector app does a nice job of dumping codecs (and GPIOs) from Linux: https://github.com/system76/coreboot-collector -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 13 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 04 Mar 2020 16:44:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZE
by Arthur Heymans (Code Review) March 4, 2020

March 4, 2020

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36239 ) Change subject: soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZE ...................................................................... soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZE The cache as ram code will use one form of a non-eviction mode. Change-Id: I418eb48434aa3da3bf5ca65315bb8c9077523966 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/skylake/Kconfig 4 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36239/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a1d3c07..ee473ba 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -48,7 +48,6 @@ select HAVE_SMI_HANDLER select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA - select NO_FIXED_XIP_ROM_SIZE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PARALLEL_MP_AP_WORK diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c1f53b1..12d9375 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -73,7 +73,6 @@ select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC select MRC_SETTINGS_PROTECT - select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d..0882dd8 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -21,6 +21,7 @@ config SOC_INTEL_COMMON_BLOCK_CAR bool default n + select NO_FIXED_XIP_ROM_SIZE help This option allows you to select how cache-as-ram (CAR) is set up. diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 901e5f9..0e889cf 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -42,7 +42,6 @@ select INTEL_GMA_ACPI select IOAPIC select MRC_SETTINGS_PROTECT - select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK select PCIEX_LENGTH_64MB -- To view, visit https://review.coreboot.org/c/coreboot/+/36239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I418eb48434aa3da3bf5ca65315bb8c9077523966 Gerrit-Change-Number: 36239 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mainboard/libretrend/lt1000: Initial commit
by Michał Żygowski (Code Review) March 4, 2020

March 4, 2020

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: src/mainboard/libretrend/lt1000: Initial commit ...................................................................... Patch Set 13: > Patch Set 13: > > (18 comments) > > Nice, thank you for upstreaming this. > > Already use SPDX headers? Yup, I will convert to SPDX. -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 13 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 04 Mar 2020 16:31:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard/libretrend/lt1000: Initial commit
by Michał Żygowski (Code Review) March 4, 2020

March 4, 2020

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: src/mainboard/libretrend/lt1000: Initial commit ...................................................................... Patch Set 13: (8 comments) https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… File Documentation/mainboard/libretrend/lt1000.jpg: PS13: > This image is a bit too grainy for its size. […] Hmm, my intention was to show as much as possible. This mainboard has so many option to connect peripherals that it is hard to show them all. Secondly, I did not wan't the image to be too big, so maybe I went overboard with JPG quality reduction. Suggestions welcome https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… File Documentation/mainboard/libretrend/lt1000.md: https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… PS13, Line 47: Fastboot > What is that? MRC cache to speed up ram training https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… PS13, Line 60: LVDS header > It's not going to work with libgfxinit, though. It's disabled. This is a general purpose mainboard put in generic case. This is rather an information that LVDS header is and was not tested at all. https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… PS13, Line 62: - speakers and mic header > Judging from the missing verbs, this does not work? Actually, Linux is able to initialize the codec and the audio works somehow. Verbs are missing because I haven't yest found time to analyze how to create them. Any pointers welcome. https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… PS13, Line 102: Super I/O, EC > Is it both? Kind of. It is Super I/O with integrated Environmental Controller (EC). Not the same as Embedded Controller thou. Should I leave it as Super I/O only? https://review.coreboot.org/c/coreboot/+/30360/13/src/mainboard/libretrend/… File src/mainboard/libretrend/lt1000/acpi/ec.asl: PS13: > I think this file must be here. Indeed. Otherwise it is not building. https://review.coreboot.org/c/coreboot/+/30360/13/src/mainboard/libretrend/… File src/mainboard/libretrend/lt1000/acpi/mainboard.asl: https://review.coreboot.org/c/coreboot/+/30360/13/src/mainboard/libretrend/… PS13, Line 1: /* > Looks like a lot of boards use that, so it should be put in some common location. IIRC there was a discussion some time ago about correctness of adding power button in ACPI. I will look for it and see what was it about. https://review.coreboot.org/c/coreboot/+/30360/13/src/mainboard/libretrend/… PS13, Line 21: Name (PBST, One) > What is this good for? Probably nothing. Copy-paste error. -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 13 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 04 Mar 2020 16:30:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/lint: use env to locate the bash binary
by Idwer Vollering (Code Review) March 4, 2020

March 4, 2020

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38227 ) Change subject: util/lint: use env to locate the bash binary ...................................................................... util/lint: use env to locate the bash binary Otherwise there will, after make gitconfig, be (hidden) shell command failures: gmake: util/lint/check-style: Command not found gmake: *** [Makefile.inc:632: check-style] Error 127 Change-Id: I3891dee53702ee10e5e44dae408193e49d7a89f1 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M util/lint/check-style 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/38227/1 diff --git a/util/lint/check-style b/util/lint/check-style index f72d7b4..5d21b8b 100755 --- a/util/lint/check-style +++ b/util/lint/check-style @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # git pre-commit hook that runs an clang-format stylecheck. # Features: # - abort commit when commit does not comply with the style guidelines -- To view, visit https://review.coreboot.org/c/coreboot/+/38227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3891dee53702ee10e5e44dae408193e49d7a89f1 Gerrit-Change-Number: 38227 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/gitconfig: Fix commit-msg for BSD grep
by Patrick Elsen (Code Review) March 4, 2020

March 4, 2020

Patrick Elsen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38205 ) Change subject: util/gitconfig: Fix commit-msg for BSD grep ...................................................................... util/gitconfig: Fix commit-msg for BSD grep BSD grep (on macOS) doesn't like repeated repetition operators, it throws the error grep: repetition-operator operand invalid This removes the superfluous repetition operator to make the commit-msg hook work on macOS and other platforms not using GNU grep. Change-Id: Id0f57d0f14634f7844b889d71342b2982fcadeb2 Signed-off-by: Patrick Elsen <pelsen(a)xfbs.net> --- M util/gitconfig/commit-msg 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/38205/1 diff --git a/util/gitconfig/commit-msg b/util/gitconfig/commit-msg index 2eef752..ba6fa3f 100755 --- a/util/gitconfig/commit-msg +++ b/util/gitconfig/commit-msg @@ -169,7 +169,7 @@ git hash-object -t commit --stdin } -if ! grep -qi '^[[:space:]]*\+Signed-off-by:' "$MSG"; then +if ! grep -qi '^[[:space:]]*Signed-off-by:' "$MSG"; then printf "\nError: No Signed-off-by line in the commit message.\n" exit 1 fi -- To view, visit https://review.coreboot.org/c/coreboot/+/38205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0f57d0f14634f7844b889d71342b2982fcadeb2 Gerrit-Change-Number: 38205 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Elsen Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/amd/agesa/[...]/Config: Avoid out-of-bounds warnings
by Name of user not set (Code Review) March 4, 2020

March 4, 2020

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38176 ) Change subject: vc/amd/agesa/[...]/Config: Avoid out-of-bounds warnings ...................................................................... vc/amd/agesa/[...]/Config: Avoid out-of-bounds warnings The memNTrainFlowControl array is generating Coverity warnings in multiple places in code where it attempts to write to index 1. The array is defined as either 2 elements or 1 of NULL depending on #if (AGESA_ENTRY_INIT_POST == TRUE). This is likely a false alarm from Coverity (memory should not be training outside of a POST), but adding a second NULL element for the AGESA_ENTRY_INIT_POST == FALSE case. Change-Id: Iaebe0830471e1854d6191c69cdaa552f900ba7a6 Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1357451, 1357452, 1357453 --- M src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h M src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h M src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/38176/1 diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h index 57dc0c8..231b263 100644 --- a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h @@ -680,7 +680,8 @@ *--------------------------------------------------------------------------------------------------- */ OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control - NULL + NULL, + NULL, }; /*--------------------------------------------------------------------------------------------------- * DEFAULT TECHNOLOGY BLOCK diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h index 457c51e..f662db2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h @@ -4662,7 +4662,8 @@ *--------------------------------------------------------------------------------------------------- */ OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control - NULL + NULL, + NULL, }; /*--------------------------------------------------------------------------------------------------- * DEFAULT TECHNOLOGY BLOCK diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h index e2d4e03..c5484f1 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h @@ -1531,7 +1531,8 @@ *--------------------------------------------------------------------------------------------------- */ OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control - NULL + NULL, + NULL, }; /*--------------------------------------------------------------------------------------------------- * DEFAULT TECHNOLOGY BLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/38176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaebe0830471e1854d6191c69cdaa552f900ba7a6 Gerrit-Change-Number: 38176 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mainboard/lenovo/t530/Kconfig: Fix PCI device id for the iGPU
by Prasun Gera (Code Review) March 4, 2020

March 4, 2020

Prasun Gera has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35431 ) Change subject: src/mainboard/lenovo/t530/Kconfig: Fix PCI device id for the iGPU ...................................................................... src/mainboard/lenovo/t530/Kconfig: Fix PCI device id for the iGPU Both T530 and W530 share the same PCI device id of 0166 for the iGPU. Change-Id: Idce809e3820a653144db424aff1c55b70c4c693a Signed-off-by: Prasun Gera <prasun.gera(a)gmail.com> --- M src/mainboard/lenovo/t530/Kconfig 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/35431/1 diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index f63a120..4fcbcb5 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -60,7 +60,10 @@ config VGA_BIOS_FILE string - default "pci8086,0106.rom" if BOARD_LENOVO_T530 - default "pci8086,0166.rom" if BOARD_LENOVO_W530 + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idce809e3820a653144db424aff1c55b70c4c693a Gerrit-Change-Number: 35431 Gerrit-PatchSet: 1 Gerrit-Owner: Prasun Gera Gerrit-MessageType: newchange

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