coreboot-gerrit March 2020

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Change in coreboot[master]: vc/amd/agesa: Delete mfParallelTraining.c
by Name of user not set (Code Review) 04 Mar '20

04 Mar '20

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38035 ) Change subject: vc/amd/agesa: Delete mfParallelTraining.c ...................................................................... vc/amd/agesa: Delete mfParallelTraining.c Potential for out-of-bounds read. However, this code is not used on F14, F15tn, or F16kb platforms. As can be seen in vc/amd/agesa/f15tn/Config/PlatformInstall.h only multiple socket F10 is supported. Tested on Lenovo G505s. Change-Id: Ib71fe32d89840b9f25619d74980e562fd626952b Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1241831 --- M src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/Makefile.inc D src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/Makefile.inc D src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/Makefile.inc D src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfParallelTraining.c 6 files changed, 0 insertions(+), 865 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/38035/1 diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/Makefile.inc b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/Makefile.inc index 90c8566..c88f907 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/Makefile.inc @@ -1,2 +1 @@ -libagesa-y += mfParallelTraining.c libagesa-y += mfStandardTraining.c diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c deleted file mode 100644 index d8b6859..0000000 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c +++ /dev/null @@ -1,286 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfParallelTraining.c - * - * This is the parallel training feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/PARTRN) - * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ - * - **/ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "mfParallelTraining.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE - -/*----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -extern MEM_TECH_CONSTRUCTOR* memTechInstalled[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the main function to perform parallel training on all nodes. - * This is the routine which will run on the remote AP. - * - * @param[in,out] *EnvPtr - Pointer to the Training Environment Data - * @param[in,out] *StdHeader - Pointer to the Standard Header of the AP - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ -BOOLEAN -MemFParallelTraining ( - IN OUT REMOTE_TRAINING_ENV *EnvPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - MEM_PARAMETER_STRUCT ParameterList; - MEM_NB_BLOCK NB; - MEM_TECH_BLOCK TB; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - UINT8 p; - UINT8 i; - UINT8 Dct; - UINT8 Channel; - UINT8 *BufferPtr; - UINT8 DctCount; - UINT8 ChannelCount; - UINT8 RowCount; - UINT8 ColumnCount; - UINT16 SizeOfNewBuffer; - AP_DATA_TRANSFER ReturnData; - - // - // Initialize Parameters - // - ReturnData.DataPtr = NULL; - ReturnData.DataSizeInDwords = 0; - ReturnData.DataTransferFlags = 0; - - ASSERT (EnvPtr != NULL); - // - // Replace Standard header of a AP - // - LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader)); - - - // - // Allocate buffer for training data - // - BufferPtr = (UINT8 *) (&EnvPtr->DieStruct); - DctCount = EnvPtr->DieStruct.DctCount; - BufferPtr += sizeof (DIE_STRUCT); - ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount; - BufferPtr += DctCount * sizeof (DCT_STRUCT); - RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount; - ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount; - - SizeOfNewBuffer = sizeof (DIE_STRUCT) + - DctCount * ( - sizeof (DCT_STRUCT) + ( - ChannelCount * ( - sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( - RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) - ) - ) - ) - ); - AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer; - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - BufferPtr = AllocHeapParams.BufferPtr; - LibAmdMemCopy ( BufferPtr, - &(EnvPtr->DieStruct), - sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))), - StdHeader - ); - - // - // Fix up pointers - // - MCTPtr = (DIE_STRUCT *) BufferPtr; - BufferPtr += sizeof (DIE_STRUCT); - MCTPtr->DctData = (DCT_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT); - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT); - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct]; - } - } - NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr; - BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK); - - ReturnData.DataPtr = AllocHeapParams.BufferPtr; - ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4; - ReturnData.DataTransferFlags = 0; - - // - // Allocate Memory for the MEM_DATA_STRUCT we will use - // - AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); - AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr; - - LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader); - - // - // Copy Parameters from environment - // - ParameterList.HoleBase = EnvPtr->HoleBase; - ParameterList.BottomIo = EnvPtr->BottomIo; - ParameterList.UmaSize = EnvPtr->UmaSize; - ParameterList.SysLimit = EnvPtr->SysLimit; - ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations; - ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration; - MemPtr->ParameterListPtr = &ParameterList; - - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p]; - } - - MemPtr->ErrorHandling = EnvPtr->ErrorHandling; - // - // Create Local NBBlock and Tech Block - // - EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr); - NB.RefPtr = &ParameterList; - NB.MemPtr = MemPtr; - i = 0; - while (memTechInstalled[i] != NULL) { - if (memTechInstalled[i] (&TB, &NB)) { - break; - } - i++; - } - NB.TechPtr = &TB; - NB.TechBlockSwitch (&NB); - - // - // Setup CPU Mem Type MSRs on the AP - // - NB.CpuMemTyping (&NB); - - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node); - // - // Call Technology Specific Training routine - // - NB.TrainingFlow (&NB); - // - // Copy training data to ReturnData buffer - // - LibAmdMemCopy ( BufferPtr, - MCTPtr->DctData[0].ChData[0].RcvEnDlys, - ((DctCount * ChannelCount) * ( - (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) - ) - ), - StdHeader); - - HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); - // - // Restore pointers - // - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct]; - - MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask; - } - MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData; - } - MCTPtr->DctData = EnvPtr->DieStruct.DctData; - } - - // - // Signal to BSP that training is complete and Send Results - // - ASSERT (ReturnData.DataPtr != NULL); - ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader); - - // - // Clean up and exit. - // - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader); - } else { - MCTPtr = &EnvPtr->DieStruct; - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/Makefile.inc index 90c8566..c88f907 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/Makefile.inc @@ -1,2 +1 @@ -libagesa-y += mfParallelTraining.c libagesa-y += mfStandardTraining.c diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c deleted file mode 100644 index 5203b4f..0000000 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c +++ /dev/null @@ -1,288 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfParallelTraining.c - * - * This is the parallel training feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/PARTRN) - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "mfParallelTraining.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE - -/*----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -extern MEM_TECH_CONSTRUCTOR* memTechInstalled[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the main function to perform parallel training on all nodes. - * This is the routine which will run on the remote AP. - * - * @param[in,out] *EnvPtr - Pointer to the Training Environment Data - * @param[in,out] *StdHeader - Pointer to the Standard Header of the AP - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ -BOOLEAN -MemFParallelTraining ( - IN OUT REMOTE_TRAINING_ENV *EnvPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - MEM_PARAMETER_STRUCT ParameterList; - MEM_NB_BLOCK NB; - MEM_TECH_BLOCK TB; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - UINT8 p; - UINT8 i; - UINT8 Dct; - UINT8 Channel; - UINT8 *BufferPtr; - UINT8 DctCount; - UINT8 ChannelCount; - UINT8 RowCount; - UINT8 ColumnCount; - UINT16 SizeOfNewBuffer; - AP_DATA_TRANSFER ReturnData; - - // - // Initialize Parameters - // - ReturnData.DataPtr = NULL; - ReturnData.DataSizeInDwords = 0; - ReturnData.DataTransferFlags = 0; - - ASSERT (EnvPtr != NULL); - // - // Replace Standard header of a AP - // - LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader)); - - - // - // Allocate buffer for training data - // - BufferPtr = (UINT8 *) (&EnvPtr->DieStruct); - DctCount = EnvPtr->DieStruct.DctCount; - BufferPtr += sizeof (DIE_STRUCT); - ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount; - BufferPtr += DctCount * sizeof (DCT_STRUCT); - RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount; - ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount; - - SizeOfNewBuffer = sizeof (DIE_STRUCT) + - DctCount * ( - sizeof (DCT_STRUCT) + ( - ChannelCount * ( - sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( - RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + - (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES) - ) - ) - ) - ); - AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer; - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - BufferPtr = AllocHeapParams.BufferPtr; - LibAmdMemCopy ( BufferPtr, - &(EnvPtr->DieStruct), - sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))), - StdHeader - ); - - // - // Fix up pointers - // - MCTPtr = (DIE_STRUCT *) BufferPtr; - BufferPtr += sizeof (DIE_STRUCT); - MCTPtr->DctData = (DCT_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT); - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT); - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct]; - } - } - NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr; - BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK); - - ReturnData.DataPtr = AllocHeapParams.BufferPtr; - ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4; - ReturnData.DataTransferFlags = 0; - - // - // Allocate Memory for the MEM_DATA_STRUCT we will use - // - AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); - AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr; - - LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader); - - // - // Copy Parameters from environment - // - ParameterList.HoleBase = EnvPtr->HoleBase; - ParameterList.BottomIo = EnvPtr->BottomIo; - ParameterList.UmaSize = EnvPtr->UmaSize; - ParameterList.SysLimit = EnvPtr->SysLimit; - ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations; - ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration; - MemPtr->ParameterListPtr = &ParameterList; - - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p]; - } - - MemPtr->ErrorHandling = EnvPtr->ErrorHandling; - // - // Create Local NBBlock and Tech Block - // - EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr); - NB.RefPtr = &ParameterList; - NB.MemPtr = MemPtr; - i = 0; - while (memTechInstalled[i] != NULL) { - if (memTechInstalled[i] (&TB, &NB)) { - break; - } - i++; - } - NB.TechPtr = &TB; - NB.TechBlockSwitch (&NB); - - // - // Setup CPU Mem Type MSRs on the AP - // - NB.CpuMemTyping (&NB); - - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node); - // - // Call Technology Specific Training routine - // - NB.TrainingFlow (&NB); - // - // Copy training data to ReturnData buffer - // - LibAmdMemCopy ( BufferPtr, - MCTPtr->DctData[0].ChData[0].RcvEnDlys, - ((DctCount * ChannelCount) * ( - (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + - (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES) - ) - ), - StdHeader); - - HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); - // - // Restore pointers - // - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct]; - - MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqs2dDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqs2dDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask; - } - MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData; - } - MCTPtr->DctData = EnvPtr->DieStruct.DctData; - } - - // - // Signal to BSP that training is complete and Send Results - // - ASSERT (ReturnData.DataPtr != NULL); - ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader); - - // - // Clean up and exit. - // - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader); - } else { - MCTPtr = &EnvPtr->DieStruct; - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/Makefile.inc index 90c8566..c88f907 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/Makefile.inc @@ -1,2 +1 @@ -libagesa-y += mfParallelTraining.c libagesa-y += mfStandardTraining.c diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfParallelTraining.c deleted file mode 100644 index 2fd10c5..0000000 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfParallelTraining.c +++ /dev/null @@ -1,288 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfParallelTraining.c - * - * This is the parallel training feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/PARTRN) - * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "mfParallelTraining.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE - -/*----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -extern MEM_TECH_CONSTRUCTOR* memTechInstalled[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the main function to perform parallel training on all nodes. - * This is the routine which will run on the remote AP. - * - * @param[in,out] *EnvPtr - Pointer to the Training Environment Data - * @param[in,out] *StdHeader - Pointer to the Standard Header of the AP - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ -BOOLEAN -MemFParallelTraining ( - IN OUT REMOTE_TRAINING_ENV *EnvPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - MEM_PARAMETER_STRUCT ParameterList; - MEM_NB_BLOCK NB; - MEM_TECH_BLOCK TB; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - UINT8 p; - UINT8 i; - UINT8 Dct; - UINT8 Channel; - UINT8 *BufferPtr; - UINT8 DctCount; - UINT8 ChannelCount; - UINT8 RowCount; - UINT8 ColumnCount; - UINT16 SizeOfNewBuffer; - AP_DATA_TRANSFER ReturnData; - - // - // Initialize Parameters - // - ReturnData.DataPtr = NULL; - ReturnData.DataSizeInDwords = 0; - ReturnData.DataTransferFlags = 0; - - ASSERT (EnvPtr != NULL); - // - // Replace Standard header of a AP - // - LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader)); - - - // - // Allocate buffer for training data - // - BufferPtr = (UINT8 *) (&EnvPtr->DieStruct); - DctCount = EnvPtr->DieStruct.DctCount; - BufferPtr += sizeof (DIE_STRUCT); - ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount; - BufferPtr += DctCount * sizeof (DCT_STRUCT); - RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount; - ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount; - - SizeOfNewBuffer = sizeof (DIE_STRUCT) + - DctCount * ( - sizeof (DCT_STRUCT) + ( - ChannelCount * ( - sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( - RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + - (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES) - ) - ) - ) - ); - AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer; - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - BufferPtr = AllocHeapParams.BufferPtr; - LibAmdMemCopy ( BufferPtr, - &(EnvPtr->DieStruct), - sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))), - StdHeader - ); - - // - // Fix up pointers - // - MCTPtr = (DIE_STRUCT *) BufferPtr; - BufferPtr += sizeof (DIE_STRUCT); - MCTPtr->DctData = (DCT_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT); - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT); - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct]; - } - } - NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr; - BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK); - - ReturnData.DataPtr = AllocHeapParams.BufferPtr; - ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4; - ReturnData.DataTransferFlags = 0; - - // - // Allocate Memory for the MEM_DATA_STRUCT we will use - // - AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); - AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr; - - LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader); - - // - // Copy Parameters from environment - // - ParameterList.HoleBase = EnvPtr->HoleBase; - ParameterList.BottomIo = EnvPtr->BottomIo; - ParameterList.UmaSize = EnvPtr->UmaSize; - ParameterList.SysLimit = EnvPtr->SysLimit; - ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations; - ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration; - MemPtr->ParameterListPtr = &ParameterList; - - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p]; - } - - MemPtr->ErrorHandling = EnvPtr->ErrorHandling; - // - // Create Local NBBlock and Tech Block - // - EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr); - NB.RefPtr = &ParameterList; - NB.MemPtr = MemPtr; - i = 0; - while (memTechInstalled[i] != NULL) { - if (memTechInstalled[i] (&TB, &NB)) { - break; - } - i++; - } - NB.TechPtr = &TB; - NB.TechBlockSwitch (&NB); - - // - // Setup CPU Mem Type MSRs on the AP - // - NB.CpuMemTyping (&NB); - - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node); - // - // Call Technology Specific Training routine - // - NB.TrainingFlow (&NB); - // - // Copy training data to ReturnData buffer - // - LibAmdMemCopy ( BufferPtr, - MCTPtr->DctData[0].ChData[0].RcvEnDlys, - ((DctCount * ChannelCount) * ( - (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + - (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES) - ) - ), - StdHeader); - - HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); - // - // Restore pointers - // - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct]; - - MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqs2dDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqs2dDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask; - } - MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData; - } - MCTPtr->DctData = EnvPtr->DieStruct.DctData; - } - - // - // Signal to BSP that training is complete and Send Results - // - ASSERT (ReturnData.DataPtr != NULL); - ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader); - - // - // Clean up and exit. - // - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader); - } else { - MCTPtr = &EnvPtr->DieStruct; - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data - } - return TRUE; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib71fe32d89840b9f25619d74980e562fd626952b Gerrit-Change-Number: 38035 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: vc/amd/agesa: Fix uninitialized scalar variable
by Name of user not set (Code Review) 04 Mar '20

04 Mar '20

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37194 ) Change subject: vc/amd/agesa: Fix uninitialized scalar variable ...................................................................... vc/amd/agesa: Fix uninitialized scalar variable AllocParams.Persist is used uninitialized when calling HeapAllocateBuffer. This could lead to unpredictable or unintended results. The f15tn and f16 versions of AmdS3Save.c have already addressed this by initializing AllocParams.Persist=0 in the same location in the code, so adding to f14 only. Change-Id: I2cbfbc4ad14a861e0cd92f130209b3b0f5b76a17 Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1241806 --- M src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/37194/1 diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c index eeab385..bc5102b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c @@ -202,7 +202,7 @@ // AllocParams.RequestedBufferSize = EarlyBufferSize + LateBufferSize; AllocParams.BufferHandle = AMD_S3_INFO_BUFFER_HANDLE; - + AllocParams.Persist = 0; AGESA_TESTPOINT (TpIfBeforeAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader); if (HeapAllocateBuffer (&AllocParams, &AmdS3SaveParams->StdHeader) != AGESA_SUCCESS) { if (AGESA_ERROR > ReturnStatus) { -- To view, visit https://review.coreboot.org/c/coreboot/+/37194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cbfbc4ad14a861e0cd92f130209b3b0f5b76a17 Gerrit-Change-Number: 37194 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: vc/amd/agesa/f14/Proc/Mem: Fix uninitialized variable
by Name of user not set (Code Review) 04 Mar '20

04 Mar '20

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38048 ) Change subject: vc/amd/agesa/f14/Proc/Mem: Fix uninitialized variable ...................................................................... vc/amd/agesa/f14/Proc/Mem: Fix uninitialized variable Unitialized variable will contain an arbitrary value left from earlier computations. This issue has already been addressed in the f15tn and f16kb versions of this same file, so am backporting the fix. Change-Id: Id876107265689e08ad6760e514a4911f32b53da7 Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1241856 --- M src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38048/1 diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c index 4963b4b..a19b8bd 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c @@ -249,6 +249,7 @@ // Base on the size of the device list, apply for a buffer for it. AllocHeapParams.RequestedBufferSize = BufferSize + sizeof (DEVICE_BLOCK_HEADER); AllocHeapParams.BufferHandle = AMD_S3_NB_INFO_BUFFER_HANDLE; + AllocHeapParams.Persist = HEAP_S3_RESUME; AGESA_TESTPOINT (TpIfBeforeAllocateMemoryS3SaveBuffer, StdHeader); if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { return AGESA_FATAL; -- To view, visit https://review.coreboot.org/c/coreboot/+/38048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id876107265689e08ad6760e514a4911f32b53da7 Gerrit-Change-Number: 38048 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: nb/intel/nehalem: Use common clflush function
by Arthur Heymans (Code Review) 04 Mar '20

04 Mar '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37195 ) Change subject: nb/intel/nehalem: Use common clflush function ...................................................................... nb/intel/nehalem: Use common clflush function Change-Id: I0ca311c12f013e54e23ff0427421bfad0b747ea6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37195/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index a393cb7..fe5d5c9 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -21,6 +21,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <cpu/x86/msr.h> +#include <cpu/x86/cache.h> #include <cbmem.h> #include <cf9_reset.h> #include <arch/cbfs.h> @@ -97,12 +98,6 @@ #include <lib.h> /* Prototypes */ - -static void clflush(u32 addr) -{ - asm volatile ("clflush (%0)"::"r" (addr)); -} - typedef struct _u128 { u64 lo; u64 hi; -- To view, visit https://review.coreboot.org/c/coreboot/+/37195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca311c12f013e54e23ff0427421bfad0b747ea6 Gerrit-Change-Number: 37195 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: vc/amd/agesa/[...]/Proc/Mem: Delete unused function
by Name of user not set (Code Review) 04 Mar '20

04 Mar '20

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38493 ) Change subject: vc/amd/agesa/[...]/Proc/Mem: Delete unused function ...................................................................... vc/amd/agesa/[...]/Proc/Mem: Delete unused function This generic function is unused, and generates a Coverity warning of an unused switch case. Only family specific versions of this function are called elsewhere. Delete unused function. Change-Id: I2afc83861f4b3a13bfc1eef4920cd3023e608e94 Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1241810 --- M src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c M src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h 4 files changed, 0 insertions(+), 115 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/38493/1 diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c index 00024e2..724202b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c @@ -1933,62 +1933,6 @@ } } - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates and programs NB P-state dependent registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramNbPstateDependentRegistersUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 RdPtrInit; - UINT8 Dct; - - RdPtrInit = (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 6 : 5; - MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit); - - switch (RdPtrInit) { - case 4: - if (MemNGetBitFieldNb (NBPtr, BFNbPsSel) == 0) { - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 2); - } else { - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); - } - break; - case 5: - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); - break; - case 6: - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 0); - break; - default: - ASSERT (FALSE); - } - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - // Set ProcOdtAdv - if (NBPtr->DCTPtr->Timings.Speed <= DDR1333_FREQUENCY) { - MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0); - } else { - MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0x4000); - } - } - } - - NBPtr->FamilySpecificHook[OverrideDataTxFifoWrDly] (NBPtr, NBPtr); - IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader); -} - /* -----------------------------------------------------------------------------*/ CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3}; CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56}; diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h index e25c938..a17906a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h @@ -1186,11 +1186,6 @@ ); VOID -MemNProgramNbPstateDependentRegistersUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID MemNProgramNbPstateDependentRegistersClientNb ( IN OUT MEM_NB_BLOCK *NBPtr ); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c index a3b5d76..6aa4868 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c @@ -2310,55 +2310,6 @@ MemFInitTableDrive (NBPtr, MTAfterFreqChg); } - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates and programs NB P-state dependent registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramNbPstateDependentRegistersUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 RdPtrInit; - - RdPtrInit = (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 6 : 4; - MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit); - - MemFInitTableDrive (NBPtr, MTAfterNbPstateChange); - - IDS_HDT_CONSOLE_DEBUG_CODE ( - RdPtrInit = (UINT8) MemNGetBitFieldNb (NBPtr, BFRdPtrInit); - ); - - switch (RdPtrInit) { - case 4: - if (MemNGetBitFieldNb (NBPtr, BFNbPsSel) == 0) { - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 2); - } else { - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); - } - break; - case 5: - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); - break; - case 6: - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 0); - break; - default: - ASSERT (FALSE); - } - - NBPtr->FamilySpecificHook[OverrideDataTxFifoWrDly] (NBPtr, NBPtr); - IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader); -} - /* -----------------------------------------------------------------------------*/ CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3}; CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h index 4be78a3..c09e2be 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h @@ -1290,11 +1290,6 @@ ); VOID -MemNProgramNbPstateDependentRegistersUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID MemNProgramNbPstateDependentRegistersClientNb ( IN OUT MEM_NB_BLOCK *NBPtr ); -- To view, visit https://review.coreboot.org/c/coreboot/+/38493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2afc83861f4b3a13bfc1eef4920cd3023e608e94 Gerrit-Change-Number: 38493 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/lenovo/t530/devicetree: Select docking_supported
by Peter Lemenkov (Code Review) 04 Mar '20

04 Mar '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38710 ) Change subject: mb/lenovo/t530/devicetree: Select docking_supported ...................................................................... mb/lenovo/t530/devicetree: Select docking_supported Looks like it should select it like any other Lenovo xx20/xx30 boards around. UNTESTED. Change-Id: Iaa4983c0a6365d77ac647f68d112a405d782d501 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t530/variants/t530/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/38710/1 diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 19fc18e..d6d9e2c 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -70,6 +70,8 @@ register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x04000201" + register "docking_supported" = "1" + register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" -- To view, visit https://review.coreboot.org/c/coreboot/+/38710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4983c0a6365d77ac647f68d112a405d782d501 Gerrit-Change-Number: 38710 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: Makefile: Explicitly silence sub-makes
by Nico Huber (Code Review) 04 Mar '20

04 Mar '20

Hello Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38931 to review the following change. Change subject: Makefile: Explicitly silence sub-makes ...................................................................... Makefile: Explicitly silence sub-makes GNU Make 4.3 doesn't propagate a global .SILENT to sub-processes anymore. Let's make it explicit to maintain the behaviour we are used to. From the changelog: [SV 54740] Ensure .SILENT settings do not leak into sub-makes Change-Id: I3de51c245d3344b062dc0fe9c62b8d5c0ac5e67d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/38931/1 diff --git a/Makefile b/Makefile index 41a9b3a..3f60493 100644 --- a/Makefile +++ b/Makefile @@ -82,6 +82,7 @@ ifneq ($(V),1) ifneq ($(Q),) .SILENT: +MAKEFLAGS += -s endif endif -- To view, visit https://review.coreboot.org/c/coreboot/+/38931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3de51c245d3344b062dc0fe9c62b8d5c0ac5e67d Gerrit-Change-Number: 38931 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/lenovo/[tw]530/devicetree: Fix comment about chip codename
by Peter Lemenkov (Code Review) 04 Mar '20

04 Mar '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38708 ) Change subject: mb/lenovo/[tw]530/devicetree: Fix comment about chip codename ...................................................................... mb/lenovo/[tw]530/devicetree: Fix comment about chip codename Change-Id: I3323e713970041b0665ca17bbcad985cba600687 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t530/variants/t530/devicetree.cb M src/mainboard/lenovo/t530/variants/w530/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/38708/1 diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 6f6dd1c..19fc18e 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -43,7 +43,7 @@ device pci 01.0 on end # PCIe bridge for discrete graphics device pci 02.0 on end # Internal graphics VGA controller - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + chip southbridge/intel/bd82x6x # Intel Series 6 Panther Point PCH # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index da5a094..c2e32e3 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -48,7 +48,7 @@ subsystemid 0x17aa 0x21f5 end - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + chip southbridge/intel/bd82x6x # Intel Series 6 Panther Point PCH # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) -- To view, visit https://review.coreboot.org/c/coreboot/+/38708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3323e713970041b0665ca17bbcad985cba600687 Gerrit-Change-Number: 38708 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/lenovo/t530/*/*/devicetree: whitespace and comments
by Peter Lemenkov (Code Review) 04 Mar '20

04 Mar '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37601 ) Change subject: mb/lenovo/t530/*/*/devicetree: whitespace and comments ...................................................................... mb/lenovo/t530/*/*/devicetree: whitespace and comments Only whitespace, minor comments. This helps making diff between devicetrees shorter. Change-Id: Ia1a84728abbece96a3d05b3b1616ac58535845bc Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t530/variants/t530/devicetree.cb M src/mainboard/lenovo/t530/variants/w530/devicetree.cb 2 files changed, 66 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37601/1 diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 47e40c3..c2a9259 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -39,9 +39,9 @@ device domain 0 on subsystemid 0x17aa 0x21f6 inherit - device pci 00.0 on end # host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -86,9 +86,9 @@ device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on + device pci 1c.2 on # PCIe Port #3 smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #3 (expresscard) + end device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 @@ -96,10 +96,9 @@ device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device pci 1f.0 on # PCI-LPC bridge chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -162,9 +161,9 @@ register "has_thinker1" = "1" end - end # LPC bridge + end device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on + device pci 1f.3 on # SMBus # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -176,7 +175,7 @@ device i2c 5e on end device i2c 5f on end end - end # SMBus + end device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 on end # Thermal end diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 135627f..f814c3f 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -14,31 +14,40 @@ register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms + register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" - device cpu_cluster 0x0 on - chip cpu/intel/model_206ax # FIXME: check all registers - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + device cpu_cluster 0 on + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip device lapic 0x0 on end device lapic 0xacac off end + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) end end register "pci_mmio_size" = "2048" - device domain 0x0 on + device domain 0 on subsystemid 0x17aa 0x21f6 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x21f5 + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) @@ -48,20 +57,30 @@ register "gpi1_routing" = "2" register "gpi13_routing" = "2" - register "c2_latency" = "0x0065" - register "docking_supported" = "1" - register "gen1_dec" = "0x007c1601" - register "gen2_dec" = "0x000c15e1" - register "gen4_dec" = "0x000c06a1" - register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" - register "sata_interface_speed_support" = "0x3" + # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) register "sata_port_map" = "0x3f" + # Set max SATA speed to 6.0 Gb/s + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen4_dec" = "0x0c06a1" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" # c2 not supported + + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + register "xhci_overcurrent_mapping" = "0x4000201" + + register "docking_supported" = "1" + register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x04000201" - register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 @@ -71,7 +90,7 @@ subsystemid 0x17aa 0x21f3 end device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # High Definition Audio device pci 1c.0 on # PCIe Port #1 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x83" @@ -90,11 +109,11 @@ device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 1f.0 on # PCI-LPC bridge chip ec/lenovo/pmh7 + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" - device pnp ff.1 on end # dummy end chip drivers/pc80/tpm @@ -102,14 +121,23 @@ end chip ec/lenovo/h8 - register "beepmask0" = "0x00" - register "beepmask1" = "0x86" + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end register "config0" = "0xa7" register "config1" = "0x01" register "config2" = "0xa0" register "config3" = "0xe2" + register "has_keyboard_backlight" = "1" + + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "has_power_management_beeps" = "0" register "event2_enable" = "0xff" register "event3_enable" = "0xff" register "event4_enable" = "0xd0" @@ -124,18 +152,9 @@ register "eventd_enable" = "0xff" register "evente_enable" = "0x0d" - register "has_keyboard_backlight" = "1" - register "has_power_management_beeps" = "0" register "has_bdc_detection" = "1" register "bdc_gpio_num" = "54" register "bdc_gpio_lvl" = "0" - - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end end chip drivers/lenovo/hybrid_graphics device pnp ff.f on end # dummy @@ -154,7 +173,8 @@ end device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBus - chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end device i2c 56 on end @@ -168,10 +188,5 @@ device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x17aa 0x21f5 - end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a84728abbece96a3d05b3b1616ac58535845bc Gerrit-Change-Number: 37601 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: util/testing/Makefile.inc: Remove viatool
by Angel Pons (Code Review) 04 Mar '20

04 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38853 ) Change subject: util/testing/Makefile.inc: Remove viatool ...................................................................... util/testing/Makefile.inc: Remove viatool It somehow creeps into `make clean`, but is not used at all. Change-Id: Ia7e11379a6db650b5190a056226a9101c2be7dec Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/testing/Makefile.inc 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/38853/1 diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 8e3882f..bf096d3 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -66,8 +66,7 @@ inteltool \ intelvbttool \ nvramtool \ -superiotool \ -viatool +superiotool TEST_PAYLOADLIST_INTERNAL= \ coreinfo \ -- To view, visit https://review.coreboot.org/c/coreboot/+/38853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e11379a6db650b5190a056226a9101c2be7dec Gerrit-Change-Number: 38853 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2020