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Change in coreboot[master]: src: capitalize 'PCIe'
by HAOUAS Elyes (Code Review) 04 Mar '20

04 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39101 ) Change subject: src: capitalize 'PCIe' ...................................................................... src: capitalize 'PCIe' Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family14/fixme.c M src/mainboard/asrock/e350m1/acpi/routing.asl M src/mainboard/asus/f2a85-m/acpi/routing.asl M src/mainboard/gizmosphere/gizmo/acpi/routing.asl M src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl M src/mainboard/lenovo/g505s/acpi/routing.asl M src/mainboard/msi/ms7721/acpi/routing.asl M src/mainboard/pcengines/apu1/acpi/routing.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/baytrail/pcie.c M src/soc/intel/braswell/acpi/globalnvs.asl M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/denverton_ns/smm.c M src/soc/intel/icelake/chip.h M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/chip.h M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/nvs.h M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/ibexpeak/nvs.h M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/nvs.h 28 files changed, 30 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39101/1 diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index be7c635..658434d 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -100,7 +100,7 @@ PciValue |= 0x80000000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize GMM Base Address for Pcie Mode + /* Initialize GMM Base Address for PCIe Mode * Modify B0D1F0x18 */ PciAddress.Address.Bus = 0; @@ -112,7 +112,7 @@ PciValue |= 0x96000000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize FB Base Address for Pcie Mode + /* Initialize FB Base Address for PCIe Mode * Modify B0D1F0x10 */ PciAddress.Address.Register = 0x10; diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl index 537bcac..0675012 100644 --- a/src/mainboard/asrock/e350m1/acpi/routing.asl +++ b/src/mainboard/asrock/e350m1/acpi/routing.asl @@ -199,7 +199,7 @@ /* Package(){0x00140005, 1, 0, 17 }, */ /* Package(){0x00140006, 1, 0, 17 }, */ - /* TODO: pcie */ + /* TODO: PCIe */ Package(){0x0015FFFF, 0, 0, 16 }, Package(){0x0015FFFF, 1, 0, 17 }, Package(){0x0015FFFF, 2, 0, 18 }, diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl index c0aef87..38ba142 100644 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -78,7 +78,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl index 447d992..af05ec6 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl @@ -200,7 +200,7 @@ /* Package(){0x00140005, 1, 0, 17 }, */ /* Package(){0x00140006, 1, 0, 17 }, */ - /* TODO: pcie */ + /* TODO: PCIe */ Package(){0x0015FFFF, 0, 0, 16 }, Package(){0x0015FFFF, 1, 0, 17 }, Package(){0x0015FFFF, 2, 0, 18 }, diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl index 22c4550..a1ce860 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl @@ -90,7 +90,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl index 22c4550..a1ce860 100644 --- a/src/mainboard/lenovo/g505s/acpi/routing.asl +++ b/src/mainboard/lenovo/g505s/acpi/routing.asl @@ -90,7 +90,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/msi/ms7721/acpi/routing.asl b/src/mainboard/msi/ms7721/acpi/routing.asl index 0af6b42..5443dd5 100644 --- a/src/mainboard/msi/ms7721/acpi/routing.asl +++ b/src/mainboard/msi/ms7721/acpi/routing.asl @@ -71,7 +71,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/pcengines/apu1/acpi/routing.asl b/src/mainboard/pcengines/apu1/acpi/routing.asl index 9a63d72..79ebef3 100644 --- a/src/mainboard/pcengines/apu1/acpi/routing.asl +++ b/src/mainboard/pcengines/apu1/acpi/routing.asl @@ -162,7 +162,7 @@ /* Package(){0x00140005, 1, 0, 17 }, */ /* Package(){0x00140006, 1, 0, 17 }, */ - /* TODO: pcie */ + /* TODO: PCIe */ Package(){0x0015FFFF, 0, 0, 16 }, Package(){0x0015FFFF, 1, 0, 17 }, Package(){0x0015FFFF, 2, 0, 18 }, diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index f33fcf6..4764931 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -99,7 +99,7 @@ PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 4a89eb9..8532728 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -83,7 +83,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 6dc0346..6b6c28d 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -163,7 +163,7 @@ dev->path.pci.devfn &= ~0x7; dev->path.pci.devfn |= func; - /* is pcie device there */ + /* is PCIe device there */ if (pci_read_config32(dev, 0) == 0xFFFFFFFF) continue; diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 9bd9afc..70b83be 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -101,7 +101,7 @@ PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 33800ef..f4cd8f2 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -86,7 +86,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index 9ceeca5..1508b06 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -91,7 +91,7 @@ PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 456fda6..ea64341 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -75,7 +75,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd2; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index fd37d26..a7ad07e 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -180,7 +180,7 @@ /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index d05e76b..75f179e 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -53,7 +53,7 @@ { printk(BIOS_DEBUG, "Enabling SMIs.\n"); - /* Configure events Disable pcie wake. */ + /* Configure events Disable PCIe wake. */ enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); disable_gpe(PME_B0_EN); diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 0687513..e82bec0 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -134,7 +134,7 @@ /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index b2467f9..372f527 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -106,7 +106,7 @@ PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index b189a16..2c3d3a5 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -226,7 +226,7 @@ u8 PchDciEn; /* - * Pcie Root Port configuration: + * PCIe Root Port configuration: * each element of array corresponds to * respective PCIe root port. */ diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index d5f62f6..24e4cf1 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -88,7 +88,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 75a399f..8176b07 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -114,7 +114,7 @@ /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index f7652ee..3983962 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -166,7 +166,7 @@ PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index a6b0bdb..0ec0c05 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -138,7 +138,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 5c2b130..7c672b3 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -351,8 +351,8 @@ * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 * - * This check is done here instead of pcie driver - * because the pcie driver enable() handler is not + * This check is done here instead of PCIe driver + * because the PCIe driver enable() handler is not * called unless the device is enabled. */ if ((PCI_FUNC(dev->path.pci.devfn) == 0 || diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index a956398..a0422f2 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -137,7 +137,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index ba9f850..fc8e219 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -161,7 +161,7 @@ PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 3aca7bb..34c2537 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -114,7 +114,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Gerrit-Change-Number: 39101 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: Makefile.inc: Ignore _HID & _ADR conflicts in Broadwell & Lynxpoint
by Patrick Georgi (Code Review) 04 Mar '20

04 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38959 ) Change subject: Makefile.inc: Ignore _HID & _ADR conflicts in Broadwell & Lynxpoint ...................................................................... Makefile.inc: Ignore _HID & _ADR conflicts in Broadwell & Lynxpoint We haven't been able to update IASL in 8 months because of this conflict. Ignoring it doesn't make things any worse than they are now. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Iced2e55e9f2aa7a262a5c1ffeff32af78acfa35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38810 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> (cherry picked from commit 12e9c5ee86f9aa87b1e84bfc59e6cdbab5a4b254) Reviewed-on: https://review.coreboot.org/c/coreboot/+/38959 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile.inc 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/Makefile.inc b/Makefile.inc index f26fead..0b09472 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -261,7 +261,16 @@ # Redundant offset remarks are not useful in any way and are masking useful # ones that might indicate an issue so it is better to hide them. REDUNDANT_OFFSET_REMARK = 2158 +# Ignore _HID & _ADR coexisting in Intel Lynxpoint and Broadwell ASL code. +# See cb:38803 & cb:38802 +# "Multiple types (Device object requires either a _HID or _ADR, but not both)" +MULTIPLE_TYPES_WARNING = 3073 + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y) +IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(MULTIPLE_TYPES_WARNING) +else IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) +endif define asl_template $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml -- To view, visit https://review.coreboot.org/c/coreboot/+/38959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Iced2e55e9f2aa7a262a5c1ffeff32af78acfa35e Gerrit-Change-Number: 38959 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[4.11_branch]: Makefile.inc: Ignore _HID & _ADR conflicts in Broadwell & Lynxpoint
by Patrick Georgi (Code Review) 04 Mar '20

04 Mar '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38959 ) Change subject: Makefile.inc: Ignore _HID & _ADR conflicts in Broadwell & Lynxpoint ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Iced2e55e9f2aa7a262a5c1ffeff32af78acfa35e Gerrit-Change-Number: 38959 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 04 Mar 2020 15:50:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/agesa/family14/acpi: Fix comment
by HAOUAS Elyes (Code Review) 04 Mar '20

04 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38054 ) Change subject: nb/amd/agesa/family14/acpi: Fix comment ...................................................................... nb/amd/agesa/family14/acpi: Fix comment "amdfam10" is no more. Change-Id: Ibf4892bb4076eb88b864fc0e894b986bf6f6e5bf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/38054/1 diff --git a/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl b/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl index fb33772..c1e4413 100644 --- a/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl +++ b/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl @@ -25,7 +25,7 @@ * Scope (\_SB.PCI0) { * Device (K10M) { * Name (_ADR, 0x00180003) - * #include <northbridge/amd/amdfam10/thermal_mixin.asl> + * #include <northbridge/amd/agesa/family14/acpi/thermal_mixin.asl> * } * } * -- To view, visit https://review.coreboot.org/c/coreboot/+/38054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf4892bb4076eb88b864fc0e894b986bf6f6e5bf Gerrit-Change-Number: 38054 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/cpu/amd: Drop unused file
by HAOUAS Elyes (Code Review) 04 Mar '20

04 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38055 ) Change subject: include/cpu/amd: Drop unused file ...................................................................... include/cpu/amd: Drop unused file Change-Id: Iff14250e52854d598967cfd3cbc98061be06e581 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/include/cpu/amd/amdfam10_sysconf.h 1 file changed, 0 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/38055/1 diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h deleted file mode 100644 index fc7b6bf..0000000 --- a/src/include/cpu/amd/amdfam10_sysconf.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_SYSCONF_H -#define AMDFAM10_SYSCONF_H - -#include "northbridge/amd/amdfam10/nums.h" - -#include <cpu/x86/msr.h> - -struct p_state_t { - unsigned int corefreq; - unsigned int power; - unsigned int transition_lat; - unsigned int busmaster_lat; - unsigned int control; - unsigned int status; -}; - -struct amdfam10_sysconf_t { - //ht - unsigned int hc_possible_num; - unsigned int pci1234[HC_POSSIBLE_NUM]; - unsigned int hcdn[HC_POSSIBLE_NUM]; - unsigned int hcid[HC_POSSIBLE_NUM]; //record ht chain type - unsigned int sbdn; - unsigned int sblk; - - unsigned int nodes; - unsigned int ht_c_num; // we only can have 32 ht chain at most - // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable - unsigned int ht_c_conf_bus[HC_NUMS]; - unsigned int io_addr_num; - unsigned int conf_io_addr[HC_NUMS]; - unsigned int conf_io_addrx[HC_NUMS]; - unsigned int mmio_addr_num; - unsigned int conf_mmio_addr[HC_NUMS*2]; // mem and pref mem - unsigned int conf_mmio_addrx[HC_NUMS*2]; - unsigned int segbit; - unsigned int hcdn_reg[HC_NUMS]; // it will be used by get_pci1234 - - // quad cores all cores in one node should be the same, and p0,..p5 - msr_t msr_pstate[NODE_NUMS * 5]; - unsigned int needs_update_pstate_msrs; - - unsigned int bsp_apicid; - int enabled_apic_ext_id; - unsigned int lift_bsp_apicid; - int apicid_offset; - - void *mb; // pointer for mb related struct - -}; - -extern struct amdfam10_sysconf_t sysconf; - -void get_bus_conf(void); -void get_pci1234(void); -void get_default_pci1234(int mb_hc_possible); - -extern u8 pirq_router_bus; - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/38055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff14250e52854d598967cfd3cbc98061be06e581 Gerrit-Change-Number: 38055 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/hatch/Kconfig: Add support for boot with tianocore payload
by Meera Ravindranath (Code Review) 04 Mar '20

04 Mar '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36067 ) Change subject: mainboard/hatch/Kconfig: Add support for boot with tianocore payload ...................................................................... mainboard/hatch/Kconfig: Add support for boot with tianocore payload Add new config and set the required GBB flags to support boot with tianocore payload. BUG=none TEST=Allows boot to tianocore on pressing Ctrl+L in depthcharge. Change-Id: I42fcf23523889d47f0490fbd662ca6b7587ab548 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/36067/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 004cc28..246e258 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -33,10 +33,18 @@ select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if BOARD_USES_TIANOCORE + select GBB_FLAG_ENABLE_ALTERNATE_OS if BOARD_USES_TIANOCORE select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH +config BOARD_USES_TIANOCORE + bool + default n + select USE_LEGACY_8254_TIMER + select USE_ACPI_PM_TIMER + config CHROMEOS_WIFI_SAR bool "Enable SAR options for Chrome OS build" depends on CHROMEOS -- To view, visit https://review.coreboot.org/c/coreboot/+/36067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42fcf23523889d47f0490fbd662ca6b7587ab548 Gerrit-Change-Number: 36067 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/soc: icl,cnl,apl,skl,tgl,common: enable TCO SMIs
by Aaron Durbin (Code Review) 04 Mar '20

04 Mar '20

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39262 ) Change subject: intel/soc: icl,cnl,apl,skl,tgl,common: enable TCO SMIs ...................................................................... Patch Set 4: Code-Review-1 This should be made into an option. From a Chrome OS perspective we do not want to take SMIs for these events. It leads to having more complex handlers and the associated policy with them. -- To view, visit https://review.coreboot.org/c/coreboot/+/39262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Gerrit-Change-Number: 39262 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 04 Mar 2020 15:14:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/elog: fix BUG: pch_log_rp_wake_source requests hidden
by 9elements QA (Code Review) 04 Mar '20

04 Mar '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39089 ) Change subject: soc/intel/skylake/elog: fix BUG: pch_log_rp_wake_source requests hidden ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1089 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1088 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1087 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/39089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id126e2c51aec84a4af9354b39754ee74687cefc8 Gerrit-Change-Number: 39089 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 04 Mar 2020 13:40:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/smm: add case intrusion to SMI handler
by Paul Menzel (Code Review) 04 Mar '20

04 Mar '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39265 ) Change subject: soc/intel/common/block/smm: add case intrusion to SMI handler ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/39265/4/src/soc/intel/common/block… File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/39265/4/src/soc/intel/common/block… PS4, Line 446: printk(BIOS_CRIT, "Intrusion detected.\n"); Be more elaborate? Add that an SMI fired, and the case was probably opened? -- To view, visit https://review.coreboot.org/c/coreboot/+/39265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifad675bb09215ada760efebdcd915958febf5778 Gerrit-Change-Number: 39265 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Mar 2020 13:36:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: tco: enable intruder SMI
by Paul Menzel (Code Review) 04 Mar '20

04 Mar '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39264 ) Change subject: soc/intel/common/block: tco: enable intruder SMI ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7 Gerrit-Change-Number: 39264 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Mar 2020 13:34:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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