coreboot-gerrit March 2020

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Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by Patrick Georgi (Code Review) 04 Mar '20

04 Mar '20

Patrick Georgi has uploaded a new patch set (#5) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/23586 ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... payloads/cbui: Add new payload CBUI Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Ported coreinfo and nvramcui * Allows to modify NVRAM and RTC * Works as ELF payload * Works as Seabios secondary payload * Basic support for multiple languages * Hacky support for BIOS calls (depends on NASM) * Runs in qemu and on real hardware * Use linker script to allocate low memory Shortcommings: * Doesn't work in VGA text mode * Untested on UEFI * int32 relocates itself to low memory Licenses: * GPLv2 (CBUI + libpayload) * BSD (libpayload) * MIT (nuklear) TODO: * Test on as much platforms as possible * Link int32 into low memory Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M payloads/Kconfig M payloads/Makefile.inc A payloads/cbui/Kconfig A payloads/cbui/Makefile A payloads/cbui/NuklearUI/NuklearCombo.c A payloads/cbui/NuklearUI/NuklearCombo.h A payloads/cbui/NuklearUI/NuklearDatePicker.c A payloads/cbui/NuklearUI/NuklearDatePicker.h A payloads/cbui/NuklearUI/NuklearGroup.c A payloads/cbui/NuklearUI/NuklearGroup.h A payloads/cbui/NuklearUI/NuklearIntegerRange.c A payloads/cbui/NuklearUI/NuklearIntegerRange.h A payloads/cbui/NuklearUI/NuklearLabel.c A payloads/cbui/NuklearUI/NuklearLabel.h A payloads/cbui/NuklearUI/NuklearObject.c A payloads/cbui/NuklearUI/NuklearObject.h A payloads/cbui/NuklearUI/NuklearRoot.c A payloads/cbui/NuklearUI/NuklearStyle.c A payloads/cbui/NuklearUI/NuklearStyle.h A payloads/cbui/NuklearUI/NuklearTabView.c A payloads/cbui/NuklearUI/NuklearTextView.c A payloads/cbui/NuklearUI/NuklearTextView.h A payloads/cbui/NuklearUI/NuklearTextfield.c A payloads/cbui/NuklearUI/NuklearTextfield.h A payloads/cbui/NuklearUI/NuklearTimePicker.c A payloads/cbui/NuklearUI/NuklearTimePicker.h A payloads/cbui/NuklearUI/NuklearUI.h A payloads/cbui/NuklearUI/NuklearVector.c A payloads/cbui/NuklearUI/NuklearVector.h A payloads/cbui/arch/x86/cpuid.c A payloads/cbui/arch/x86/cpuid.h A payloads/cbui/arch/x86/int32.h A payloads/cbui/arch/x86/int32.ld A payloads/cbui/arch/x86/int32.nasm A payloads/cbui/arch/x86/memcpy.c A payloads/cbui/arch/x86/memcpy.h A payloads/cbui/arch/x86/vga.c A payloads/cbui/arch/x86/vga.h A payloads/cbui/cbui.c A payloads/cbui/cbui.h A payloads/cbui/gfx/coreboot.c A payloads/cbui/gfx/coreboot.h A payloads/cbui/gfx/gfx.c A payloads/cbui/gfx/gfx.h A payloads/cbui/gfx/splash.c A payloads/cbui/gfx/splash.h A payloads/cbui/gfx/vbe.c A payloads/cbui/gfx/vbe.h A payloads/cbui/lang/de.c A payloads/cbui/lang/en.c A payloads/cbui/lang/lang.c A payloads/cbui/lang/lang.h A payloads/cbui/logo/cbui.png A payloads/cbui/lp.config A payloads/cbui/modules/bootlog_module.c A payloads/cbui/modules/cbfs_module.c A payloads/cbui/modules/cmos_module.c A payloads/cbui/modules/coreboot_module.c A payloads/cbui/modules/cpuinfo_module.c A payloads/cbui/modules/license_module.c A payloads/cbui/modules/modules.c A payloads/cbui/modules/nvram_module.c A payloads/cbui/modules/pci_module.c A payloads/cbui/modules/reboot_module.c A payloads/cbui/modules/rtc_module.c A payloads/cbui/modules/timestamps_module.c A payloads/cbui/modules/usb_module.c A payloads/libpayload/configs/defconfig-cbui 68 files changed, 8,715 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23586/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/23586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Gerrit-Change-Number: 23586 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload: Improve rtc functions
by Patrick Georgi (Code Review) 04 Mar '20

04 Mar '20

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Change in coreboot[master]: libpayload: Improve rtc functions
by Patrick Georgi (Code Review) 04 Mar '20

04 Mar '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18498 ) Change subject: libpayload: Improve rtc functions ...................................................................... Patch Set 4: (4 comments) https://review.coreboot.org/c/coreboot/+/18498/1/payloads/libpayload/driver… File payloads/libpayload/drivers/nvram.c: https://review.coreboot.org/c/coreboot/+/18498/1/payloads/libpayload/driver… PS1, Line 127: 0x04 > Please use defined constants (e.g. NVRAM_RTC_BINARY). Done https://review.coreboot.org/c/coreboot/+/18498/4/payloads/libpayload/driver… File payloads/libpayload/drivers/nvram.c: https://review.coreboot.org/c/coreboot/+/18498/4/payloads/libpayload/driver… PS4, Line 127: 0x04 > maybe give it a name? RTC_BINARY_FORMAT (with 0 == BCD) Done https://review.coreboot.org/c/coreboot/+/18498/4/payloads/libpayload/driver… PS4, Line 133: 0x02 > RTC_24HOURS? Done https://review.coreboot.org/c/coreboot/+/18498/4/payloads/libpayload/driver… PS4, Line 146: if (!(statusB & 0x02)) { : reg8 = nvram_read(NVRAM_RTC_HOURS); : time->tm_hour = reg8 & 0x7f; : time->tm_hour += (reg8 & 0x80) ? 12 : 0; : time->tm_hour %= 24; : } else : time->tm_hour = nvram_read(NVRAM_RTC_HOURS); : time->tm_year = nvram_read(NVRAM_RTC_YEAR); > factor out? or maybe not... -- To view, visit https://review.coreboot.org/c/coreboot/+/18498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id773c33e228973e190a7e14c3d11979678b1a619 Gerrit-Change-Number: 18498 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Wed, 04 Mar 2020 11:00:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: EC sync: Support enabling EC EFS with EC software sync.
by Paul Menzel (Code Review) 04 Mar '20

04 Mar '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39272 ) Change subject: EC sync: Support enabling EC EFS with EC software sync. ...................................................................... Patch Set 1: (5 comments) https://review.coreboot.org/c/coreboot/+/39272/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39272/1//COMMIT_MSG@7 PS1, Line 7: EC sync: Support enabling EC EFS with EC software sync. 1. Please prefix with *security*. 2. Please remove the dot/period at the end. https://review.coreboot.org/c/coreboot/+/39272/1//COMMIT_MSG@9 PS1, Line 9: EFS What is that? https://review.coreboot.org/c/coreboot/+/39272/1//COMMIT_MSG@11 PS1, Line 11: Why can’t the vboot code in coreboot not detect that at runtime? https://review.coreboot.org/c/coreboot/+/39272/1/src/security/vboot/Kconfig File src/security/vboot/Kconfig: https://review.coreboot.org/c/coreboot/+/39272/1/src/security/vboot/Kconfig… PS1, Line 264: Early-firmware No minus? https://review.coreboot.org/c/coreboot/+/39272/1/src/security/vboot/Kconfig… PS1, Line 268: need needs -- To view, visit https://review.coreboot.org/c/coreboot/+/39272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I697e90748e19d15af154011413b30c0f2a0bf52e Gerrit-Change-Number: 39272 Gerrit-PatchSet: 1 Gerrit-Owner: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 04 Mar 2020 10:45:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/hatch/puff: Enable VBOOT_EC_EFS.
by Paul Menzel (Code Review) 04 Mar '20

04 Mar '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39273 ) Change subject: mainboard/google/hatch/puff: Enable VBOOT_EC_EFS. ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/c/coreboot/+/39273/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39273/1//COMMIT_MSG@7 PS1, Line 7: mainboard mb https://review.coreboot.org/c/coreboot/+/39273/1//COMMIT_MSG@7 PS1, Line 7: mainboard/google/hatch/puff: Enable VBOOT_EC_EFS. Please remove the dot/period at the end. https://review.coreboot.org/c/coreboot/+/39273/1//COMMIT_MSG@8 PS1, Line 8: Please summarize the problem. -- To view, visit https://review.coreboot.org/c/coreboot/+/39273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0877000b7d277106436831f2d69775c25299da9e Gerrit-Change-Number: 39273 Gerrit-PatchSet: 1 Gerrit-Owner: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 04 Mar 2020 10:41:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: add read64() and write64()
by Thomas Heijligen (Code Review) 04 Mar '20

04 Mar '20

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34206 ) Change subject: libpayload: add read64() and write64() ...................................................................... libpayload: add read64() and write64() Change-Id: I6febf13ed54a7707f5a99d3d2715c36e18517c12 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M payloads/libpayload/include/x86/arch/io.h 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34206/1 diff --git a/payloads/libpayload/include/x86/arch/io.h b/payloads/libpayload/include/x86/arch/io.h index c417ce0..46836d9 100644 --- a/payloads/libpayload/include/x86/arch/io.h +++ b/payloads/libpayload/include/x86/arch/io.h @@ -64,6 +64,11 @@ return *((volatile uint32_t *)(addr)); } +static inline __attribute__((always_inline)) uint64_t read64(const volatile void *addr) +{ + return *((volatile uint64_t *)(addr)); +} + static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value) { *((volatile uint8_t *)(addr)) = value; @@ -79,6 +84,11 @@ *((volatile uint32_t *)(addr)) = value; } +static inline __attribute__((always_inline)) void write64(volatile void *addr, uint64_t value) +{ + *((volatile uint64_t *)(addr)) = value; +} + static inline unsigned int inl(int port) { unsigned long val; -- To view, visit https://review.coreboot.org/c/coreboot/+/34206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6febf13ed54a7707f5a99d3d2715c36e18517c12 Gerrit-Change-Number: 34206 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/model_206ax: Lock MSR on all cores
by Patrick Rudolph (Code Review) 04 Mar '20

04 Mar '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39199 ) Change subject: cpu/intel/model_206ax: Lock MSR on all cores ...................................................................... cpu/intel/model_206ax: Lock MSR on all cores Lock MSR MSR_PKG_CST_CONFIG_CONTROL on all cores, not only the one handling APM_CNT_FINALIZE. Tested on HP Z220: FWTS no longer reports this as an issue. Change-Id: I174d6c6c74fbba47992084cc44ebddf84eeeabd1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_206ax/finalize.c M src/cpu/intel/model_206ax/model_206ax_init.c 2 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39199/1 diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index d51fb21..a7754ae 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -25,9 +25,6 @@ void intel_model_206ax_finalize_smm(void) { - /* Lock C-State MSR */ - msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); - /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) msr_set_bit(MSR_FEATURE_CONFIG, 0); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 2571f8c..7739408 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -256,6 +256,8 @@ msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection msr.lo |= 7; // No package C-state limit + + msr.lo |= (1 << 15); // Lock C-State MSR wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR); -- To view, visit https://review.coreboot.org/c/coreboot/+/39199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I174d6c6c74fbba47992084cc44ebddf84eeeabd1 Gerrit-Change-Number: 39199 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake
by Srinidhi N Kaushik (Code Review) 04 Mar '20

04 Mar '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39169 ) Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ...................................................................... soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake update SerialIoUartAutoFlow settings for Tiger Lake platform. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879 --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39169/1 diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index d22cde0..b24156c 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -120,6 +121,8 @@ /* PCH UART selection for FSP Debug */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + ASSERT(CONFIG_UART_FOR_CONSOLE < ARRAY_SIZE(params->SerialIoUartAutoFlow)); + params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; /* SATA */ dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/39169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879 Gerrit-Change-Number: 39169 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton_ns: Generate ACPI DMAR Table
by Patrick Georgi (Code Review) 04 Mar '20

04 Mar '20

Patrick Georgi has uploaded a new patch set (#16) to the change originally created by Julien Viard de Galbert. ( https://review.coreboot.org/c/coreboot/+/25446 ) Change subject: soc/intel/denverton_ns: Generate ACPI DMAR Table ...................................................................... soc/intel/denverton_ns: Generate ACPI DMAR Table - Write ACPI DMAR Table if VT-d is enabled. - The entries are defined to follow FSP settings. Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/systemagent.h M src/soc/intel/denverton_ns/systemagent.c 6 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/25446/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/25446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Gerrit-Change-Number: 25446 Gerrit-PatchSet: 16 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/denverton_ns: Allow using FSP repo
by Felix Singer (Code Review) 04 Mar '20

04 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30931 Change subject: soc/intel/denverton_ns: Allow using FSP repo ...................................................................... soc/intel/denverton_ns: Allow using FSP repo Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/denverton_ns/Kconfig 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30931/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8156d18..6f5ed2a 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -85,7 +85,8 @@ bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE + SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ + SOC_INTEL_DENVERTON_NS help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 1096549..dfb5c37 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -78,6 +78,16 @@ help The memory location of the Intel FSP-S binary for this platform. +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" + # CAR memory layout on DENVERTON_NS hardware: ## CAR base address - 0xfef00000 ## CAR size 1MB - 0x100 (0xfff00) -- To view, visit https://review.coreboot.org/c/coreboot/+/30931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Gerrit-Change-Number: 30931 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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coreboot-gerrit March 2020