coreboot-gerrit March 2020

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Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Maulik V Vaghela (Code Review) 02 Mar '20

02 Mar '20

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Sooraj Govindan, Aamir Bohra, Justin TerAvest, Rizwan Qureshi, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Karthik Ramasubramanian, Meera Ravindranath, Ronak Kanabar, Usha P, Tim Wawrzynczak, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39111 to look at the new patch set (#12). Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support ...................................................................... soc/intel/tigerlake: Add Jasper lake GPIO support Add gpio definition for Jasper Lake gpio controller. Also created a separate file for JSL and TGL gpio keeping common asl file. gpio_soc_defs.h must pass correct information/macro values to asl file for code to work. GPIO controller includes 4 gpio community and 10 groups. Patch adds definition for all gpio within community and groups Updated IRQ mapping for all gpios TEST=Check if jslrvp and tglrvp code is compiling Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Usha P <usha.p(a)intel.com> --- A src/soc/intel/common/acpi/gpio_op.asl M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/chip.h A src/soc/intel/tigerlake/gpio_jsl.c R src/soc/intel/tigerlake/gpio_tgl.c M src/soc/intel/tigerlake/include/soc/gpio.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h M src/soc/intel/tigerlake/include/soc/pmc.h 13 files changed, 1,424 insertions(+), 475 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39111/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/39111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Gerrit-Change-Number: 39111 Gerrit-PatchSet: 12 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Maulik V Vaghela (Code Review) 02 Mar '20

02 Mar '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39111 ) Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support ...................................................................... Patch Set 11: (6 comments) https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/gpio_jsl.asl: https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac… PS2, Line 20: > Yes Karthik, I'll check this and work on it. Done https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac… PS2, Line 31: Memory32Fixed (ReadWrite, 0, 0, COM2) > Do we want to export ACPI objects for GPP_GPD group? I don't see it for TGL. […] No, this is not required. I have removed it from asl file. https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac… PS2, Line 40: /* GPIO Community 0 */ : CreateDWordField (^RBUF, ^COM0._BAS, BAS0) : CreateDWordField (^RBUF, ^COM0._LEN, LEN0) : Store (^^PCRB (PID_GPIOCOM0), BAS0) : Store (GPIO_BASE_SIZE, LEN0) : : /* GPIO Community 1 */ : CreateDWordField (^RBUF, ^COM1._BAS, BAS1) : CreateDWordField (^RBUF, ^COM1._LEN, LEN1) : Store (^^PCRB (PID_GPIOCOM1), BAS1) : Store (GPIO_BASE_SIZE, LEN1) : : /* GPIO Community 2 */ : CreateDWordField (^RBUF, ^COM2._BAS, BAS2) : CreateDWordField (^RBUF, ^COM2._LEN, LEN2) : Store (^^PCRB (PID_GPIOCOM2), BAS2) : Store (GPIO_BASE_SIZE, LEN2) : : /* GPIO Community 4 */ : CreateDWordField (^RBUF, ^COM4._BAS, BAS4) : CreateDWordField (^RBUF, ^COM4._LEN, LEN4) : Store (^^PCRB (PID_GPIOCOM4), BAS4) : Store (GPIO_BASE_SIZE, LEN4) : : /* GPIO Community 5 */ : CreateDWordField (^RBUF, ^COM5._BAS, BAS5) : CreateDWordField (^RBUF, ^COM5._LEN, LEN5) : Store (^^PCRB (PID_GPIOCOM5), BAS5) : Store (GPIO_BASE_SIZE, LEN5) > Let me check this. since I am on vacation I may take a day or two to correct it. Done https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/gpio_op.asl: PS2: > +1 Done https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/gpio_tgl.asl: https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac… PS2, Line 84: BAS4 = ^^PCRB (PID_GPIOCOM4) > Similar to what I mentioned in the gpio_jsl. […] Done https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h: https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/in… PS2, Line 67: GPIO_RSVD_0 > These are soc reserved gpio pins that's why name is reserved. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Gerrit-Change-Number: 39111 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Mar 2020 09:23:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by build bot (Jenkins) (Code Review) 02 Mar '20

02 Mar '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39111 ) Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/39111/11/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h: https://review.coreboot.org/c/coreboot/+/39111/11/src/soc/intel/tigerlake/i… PS11, Line 334: #define NUM_GPIO_COM4_PADS (GPIO_COM4_END -GPIO_COM4_START + 1) need consistent spacing around '-' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/39111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Gerrit-Change-Number: 39111 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Mar 2020 09:23:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Maulik V Vaghela (Code Review) 02 Mar '20

02 Mar '20

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Sooraj Govindan, Aamir Bohra, Justin TerAvest, Rizwan Qureshi, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Karthik Ramasubramanian, Meera Ravindranath, Ronak Kanabar, Usha P, Tim Wawrzynczak, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39111 to look at the new patch set (#11). Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support ...................................................................... soc/intel/tigerlake: Add Jasper lake GPIO support Add gpio definition for Jasper Lake gpio controller. Also created a separate file for JSL and TGL gpio keeping common asl file. gpio_soc_defs.h must pass correct information/macro values to asl file for code to work. GPIO controller includes 4 gpio community and 10 groups. Patch adds definition for all gpio within community and groups Updated IRQ mapping for all gpios TEST=Check if jslrvp and tglrvp code is compiling Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Usha P <usha.p(a)intel.com> --- A src/soc/intel/common/acpi/gpio_op.asl M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/chip.h A src/soc/intel/tigerlake/gpio_jsl.c R src/soc/intel/tigerlake/gpio_tgl.c M src/soc/intel/tigerlake/include/soc/gpio.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h M src/soc/intel/tigerlake/include/soc/pmc.h 13 files changed, 1,424 insertions(+), 475 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39111/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/39111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Gerrit-Change-Number: 39111 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: util/superiotool: Add AST2400
by Patrick Rudolph (Code Review) 01 Mar '20

01 Mar '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32984 Change subject: util/superiotool: Add AST2400 ...................................................................... util/superiotool: Add AST2400 Add support for AST2400 Super I/O. The device doesn't have an ID register, so probe for PCI devices and known bits in scratch registers. Tested on platform which has an AST2400. Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/superiotool/Makefile A util/superiotool/aspeed.c M util/superiotool/superiotool.h 3 files changed, 161 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/32984/1 diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 3a0bcf0..d1d7f243 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -53,7 +53,7 @@ ifeq ($(CONFIG_PCI), yes) CFLAGS += -DPCI_SUPPORT -OBJS += pci.o via.o amd.o +OBJS += pci.o via.o amd.o aspeed.o LIBS += -lpci ifeq ($(OS_ARCH),NetBSD) LIBS += -lpciutils diff --git a/util/superiotool/aspeed.c b/util/superiotool/aspeed.c new file mode 100644 index 0000000..0a7b624 --- /dev/null +++ b/util/superiotool/aspeed.c @@ -0,0 +1,151 @@ +/* + * This file is part of the superiotool project. + * + * Copyright (C) 2010 Google Inc. + * Written by David Hendricks <dhendrix(a)google.com> for Aspeed Technology Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "superiotool.h" + +#define DEVICE_SCRATCH_REG 0x21 + +static const struct superio_registers reg_table[] = { + {0x00, "AST2400", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x02, "SUART1", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x02,RSVD,EOT}}, + {0x03, "SUART1", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x02,0x00,EOT}}, + {0x04, "SWC", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67, + 0x70,0x71,EOT}, + {0x00,0x08,0xe6,0x08,0xe0,0x08,0xe4,0x08,0xe8, + 0x09,0x01,EOT}}, + {0x05, "Keyboard config (KBC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x72,0x73, + 0xf0,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x0c,0x02, + 0x83,EOT}}, + {0x07, "GPIO", + {0x30,0x38,0x70,0x71,EOT}, + {0x00,0x00,0x0b,0x01,EOT}}, + {0x0b, "SUART3", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x03,0xe8,0x06,0x02,0x00,EOT}}, + {0x0c, "SUART4", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x02,0xe8,0x05,0x02,0x00,EOT}}, + {0x0d, "iLPC2AHB", + {0x30,0x70,0x71,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5, + 0xf6,0xf7,0xf8,0xfe,EOT}, + {0x00,0x09,0x01,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,0x00,0x00,EOT}}, + {0x0e, "Mailbox", + {0x30,0x60,0x61,0x70,0x71,EOT}, + {0x00,0x08,0xc0,0x09,0x01,EOT}}, + {EOT}}}, + {EOT} +}; + +static void enter_conf_mode_ast(uint16_t port) +{ + OUTB(0xa5, port); + OUTB(0xa5, port); +} + +static void exit_conf_mode_ast(uint16_t port) +{ + OUTB(0xaa, port); +} + +static int detect_ast_pci(void) +{ + int i; + static const uint16_t ids[] = { + 0x2000, 0x1150, + }; + + for (i = 0; i < ARRAY_SIZE(ids); i++) { + if (pci_dev_find(0x1a03, ids[i])) + return 1; + } + + return 0; +} + +static int detect_ast_superio(uint16_t port) +{ + int i; + enter_conf_mode_ast(port); + + /* Aspeed devices doesn't have a DEVICE_ID_REG. + * Host cycles that aren't decoded read as 0xff. + * Probe for the scratch register that are initialized to zero. + * The firmware might overwrite that, but it's the best we have. + * Together with PCI detection that should be sufficient. + */ + + for (i = DEVICE_SCRATCH_REG; i < 0x30; i++) { + if (regval(port, i) == 0) + break; + } + if (i == 0x30) { + if (verbose) + printf(NOTFOUND + "scratch registers all read as non zero\n"); + } + exit_conf_mode_ast(port); + + return i < 0x30; +} + +void probe_idregs_aspeed(uint16_t port) +{ + uint16_t chip_id = 0; + + probing_for("Aspeed", "", port); + + if (!detect_ast_pci()) { + if (verbose) + printf(NOTFOUND "missing PCI device\n"); + return; + } + + if (!detect_ast_superio(port)) + return; + + if (superio_unknown(reg_table, chip_id)) { + if (verbose) + printf(NOTFOUND "id=0x%02x\n", chip_id); + return; + } + + printf("Found Aspeed %s (id=0x%02x) at 0x%x\n", + get_superio_name(reg_table, chip_id), chip_id, port); + chip_found = 1; + + enter_conf_mode_ast(port); + dump_superio("Aspeed", reg_table, port, chip_id, LDN_SEL); + exit_conf_mode_ast(port); +} + +void print_aspeed_chips(void) +{ + print_vendor_chips("Aspeed", reg_table); +} diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index 1a10fb6..f2a4d5e 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -184,6 +184,12 @@ void probe_idregs_ali(uint16_t port); void print_ali_chips(void); +/* aspeed.c */ +#ifdef PCI_SUPPORT +void probe_idregs_aspeed(uint16_t port); +void print_aspeed_chips(void); +#endif + /* amd.c */ void probe_idregs_amd(uint16_t port); void print_amd_chips(void); @@ -252,6 +258,8 @@ {probe_idregs_via, {0x2e, 0x4e, 0x3f0, EOT}}, /* in fact read the BASE from HW */ {probe_idregs_amd, {0xaa, EOT}}, + /* Probe for aspeed PCI devices */ + {probe_idregs_aspeed, {0x2e, 0x4e, EOT}}, #endif {probe_idregs_serverengines, {0x2e, EOT}}, {probe_idregs_infineon, {0x2e, 0x4e, EOT}}, @@ -272,6 +280,7 @@ #ifdef PCI_SUPPORT {print_via_chips}, {print_amd_chips}, + {print_aspeed_chips}, #endif {print_serverengines_chips}, {print_infineon_chips}, -- To view, visit https://review.coreboot.org/c/coreboot/+/32984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1 Gerrit-Change-Number: 32984 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Maulik V Vaghela (Code Review) 01 Mar '20

01 Mar '20

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Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572
by Angel Pons (Code Review) 01 Mar '20

01 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mainboard: Add Acer ES1-572 ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/38978/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38978/3//COMMIT_MSG@31 PS3, Line 31: UART 2 > The FSP has a UPD to enable these. Try using: […] Yes, I had issues with that before. Now it works. Also, I forgot to send this message yesterday. It's not really verbose, most of the fun stuff is done inside FSP anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Mar 2020 11:42:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/{cnl, apl, skl}: Make use of print_me_fw_version() from CSE...
by Sridhar Siricilla (Code Review) 01 Mar '20

01 Mar '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39011 ) Change subject: soc/intel/{cnl, apl, skl}: Make use of print_me_fw_version() from CSE lib ...................................................................... soc/intel/{cnl, apl, skl}: Make use of print_me_fw_version() from CSE lib Remove print_me_version/dump_me_version from cnl/skl/apl and make changes to call print_me_version() which is defined in the CSE lib. TEST=Verified on hatch, soraka and bobba. Change-Id: I9b4dcb6ff85cce09b548cdec4cb490bd8e34297e Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/apollolake/cse.c M src/soc/intel/cannonlake/me.c M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/me.c 4 files changed, 8 insertions(+), 213 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39011/1 diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 6ee1a15..2445289 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -36,9 +36,6 @@ #define READ_FILE_FLAG_EMULATED (1 << 2) #define READ_FILE_FLAG_HW (1 << 3) -#define MKHI_GROUP_ID_GEN 0xff -#define GET_FW_VERSION 0x02 - #define MCA_MAX_FILE_PATH_SIZE 64 #define FUSE_LOCK_FILE "/fpf/intel/SocCfgLock" @@ -180,59 +177,6 @@ return reg; } -static void dump_cse_version(void *unused) -{ - int res; - size_t reply_size; - struct mkhi_hdr msg; - struct version { - uint16_t minor; - uint16_t major; - uint16_t build; - uint16_t hotfix; - } __packed; - - struct fw_version_response { - struct mkhi_hdr hdr; - struct version code; - struct version nftp; - struct version fitc; - } __packed rsp; - - /* - * Print ME version only if UART debugging is enabled. Else, it takes - * ~0.6 second to talk to ME and get this information. - */ - if (!CONFIG(CONSOLE_SERIAL)) - return; - - msg.group_id = MKHI_GROUP_ID_GEN; - msg.command = GET_FW_VERSION; - - res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); - - if (!res) { - printk(BIOS_ERR, "Failed to send HECI message.\n"); - return; - } - - reply_size = sizeof(rsp); - res = heci_receive(&rsp, &reply_size); - - if (!res) { - printk(BIOS_ERR, "Failed to receive HECI reply.\n"); - return; - } - - if (rsp.hdr.result != 0) { - printk(BIOS_ERR, "Failed to get ME version.\n"); - return; - } - - printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", rsp.code.major, - rsp.code.minor, rsp.code.hotfix, rsp.code.build); -} - static void dump_cse_state(void) { uint32_t fwsts1; @@ -289,4 +233,4 @@ } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, fpf_blown, NULL); -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, dump_cse_version, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, print_me_fw_version, NULL); diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index 3d3fcb8..ccacbe2 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -23,14 +23,6 @@ #include <soc/pci_devs.h> #include <stdint.h> -/* Miscellaneous constants */ -enum { - MKHI_GEN_GROUP_ID = 0xFF, - MKHI_GET_FW_VERSION = 0x02, - ME_OPMODE_NORMAL = 0x00, - ME_WSTATE_NORMAL = 0x05, -}; - /* Host Firmware Status Register 2 */ union me_hfsts2 { uint32_t raw; @@ -115,76 +107,6 @@ } __packed fields; }; -/* - * From reading the documentation, this should work for both WHL and CML - * platforms. Also, calling this function from dump_me_status() does not - * work, as the ME does not respond and the command times out. - */ -static void print_me_version(void *unused) -{ - struct version { - uint16_t minor; - uint16_t major; - uint16_t build; - uint16_t hotfix; - } __packed; - - struct fw_ver_resp { - struct mkhi_hdr hdr; - struct version code; - struct version rec; - struct version fitc; - } __packed; - - union me_hfsts1 hfsts1; - const struct mkhi_hdr fw_ver_msg = { - .group_id = MKHI_GEN_GROUP_ID, - .command = MKHI_GET_FW_VERSION, - }; - struct fw_ver_resp resp; - size_t resp_size = sizeof(resp); - - /* Ignore if UART debugging is disabled */ - if (!CONFIG(CONSOLE_SERIAL)) - return; - - if (!is_cse_enabled()) - return; - - hfsts1.data = me_read_config32(PCI_ME_HFSTS1); - - /* - * Prerequisites: - * 1) HFSTS1 Current Working State is Normal - * 2) HFSTS1 Current Operation Mode is Normal - * 3) It's after DRAM INIT DONE message (taken care of by calling it - * during ramstage - */ - if ((hfsts1.fields.working_state != ME_WSTATE_NORMAL) || - (hfsts1.fields.operation_mode != ME_OPMODE_NORMAL)) - goto fail; - - heci_reset(); - - if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR, - HECI_MKHI_ADDR)) - goto fail; - - if (!heci_receive(&resp, &resp_size)) - goto fail; - - if (resp.hdr.result) - goto fail; - - printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, - resp.code.minor, resp.code.hotfix, resp.code.build); - return; - -fail: - printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); -} -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); - void dump_me_status(void *unused) { union me_hfsts1 hfsts1; @@ -252,3 +174,4 @@ } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 332340f..2f581fb 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -192,10 +192,6 @@ } __packed fields; }; -#define MKHI_GEN_GROUP_ID 0xff - -#define MKHI_GET_FW_VERSION 0x02 - void intel_me_status(void); int send_global_reset(void); diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index b45234e..45a7c48 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -196,80 +196,6 @@ "M0 kernel load", }; -static void print_me_version(void *unused) -{ - struct version { - uint16_t minor; - uint16_t major; - uint16_t build; - uint16_t hotfix; - } __packed; - - struct fw_ver_resp { - struct mkhi_hdr hdr; - struct version code; - struct version rec; - struct version fitc; - } __packed; - - const struct mkhi_hdr fw_ver_msg = { - .group_id = MKHI_GEN_GROUP_ID, - .command = MKHI_GET_FW_VERSION, - }; - - struct fw_ver_resp resp; - size_t resp_size = sizeof(resp); - union me_hfsts1 hfs1; - - /* - * Print ME version only if UART debugging is enabled. Else, it takes ~1 - * second to talk to ME and get this information. - */ - if (!CONFIG(CONSOLE_SERIAL)) - return; - - if (!is_cse_enabled()) - return; - - hfs1.data = me_read_config32(PCI_ME_HFSTS1); - /* - * This command can be run only if: - * - Working state is normal and - * - Operation mode is normal. - */ - if ((hfs1.fields.working_state != ME_HFS_CWS_NORMAL) || - (hfs1.fields.operation_mode != ME_HFS_MODE_NORMAL)) - goto failed; - - /* - * It is important to do a heci_reset to ensure BIOS and ME are in sync - * before reading firmware version. - */ - heci_reset(); - - if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR, - HECI_MKHI_ADDR)) - goto failed; - - if (!heci_receive(&resp, &resp_size)) - goto failed; - - if (resp.hdr.result) - goto failed; - - printk(BIOS_DEBUG, "ME: Version : %d.%d.%d.%d\n", resp.code.major, - resp.code.minor, resp.code.hotfix, resp.code.build); - return; - -failed: - printk(BIOS_DEBUG, "ME: Version : Unavailable\n"); -} -/* - * This can't be put in intel_me_status because by the time control - * reaches there, ME doesn't respond to GET_FW_VERSION command. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); - void intel_me_status(void) { union me_hfsts1 hfs1; @@ -445,3 +371,9 @@ ret: return status; } + +/* + * This can't be put in intel_me_status because by the time control + * reaches there, ME doesn't respond to GET_FW_VERSION command. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/39011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b4dcb6ff85cce09b548cdec4cb490bd8e34297e Gerrit-Change-Number: 39011 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

2 13

Change in coreboot[master]: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig
by Subrata Banik (Code Review) 01 Mar '20

01 Mar '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39152 ) Change subject: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig ...................................................................... soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_<SOC>LAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details. TEST=Able to connect ITP/DCI with target system. Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 7 files changed, 25 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/39152/1 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 15a5a31..b30b8c6 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -186,6 +186,17 @@ depends on FSP_USE_REPO default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" +config SOC_INTEL_ICELAKE_DEBUG_CONSENT + int "Debug Consent for ICL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + config ENABLE_DISPLAY_OVER_EXT_PCIE_GFX bool "Enable display over external PCIE GFX card" select ALWAYS_LOAD_OPROM diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 0687513..569160f 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -203,15 +203,6 @@ uint8_t PmTimerDisabled; - /* Desired platform debug type. */ - enum { - DebugConsent_Disabled, - DebugConsent_DCI_DBC, - DebugConsent_DCI, - DebugConsent_USB3_DBC, - DebugConsent_XDP, /* XDP/Mipi60 */ - DebugConsent_USB2_DBC, - } DebugConsent; /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 1f99604..8dd6bfd 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -87,7 +87,7 @@ /* Enable SMBus controller based on config */ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ICELAKE_DEBUG_CONSENT; /* Vt-D config */ m_cfg->VtdDisable = 0; diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 79d74b4..c18752f 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -212,4 +212,15 @@ default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE +config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT + int "Debug Consent for TGL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + endif diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 5442361..02855b1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -169,17 +169,6 @@ */ uint32_t PrmrrSize; uint8_t PmTimerDisabled; - /* Desired platform debug type. */ - enum { - DebugConsent_Disabled, - DebugConsent_DCI_DBC, - DebugConsent_DCI, - DebugConsent_USB3_DBC, - DebugConsent_XDP, /* XDP/Mipi60 */ - DebugConsent_USB2_DBC, - DebugConsent_2WIRE_DCI, - DebugConsent_Manual, - } DebugConsent; /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index e88d809..e02eb6a 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -80,7 +80,7 @@ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT; /* VT-d config */ m_cfg->VtdDisable = 0; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index ed6aa5a..d769615 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -109,7 +109,7 @@ /* Enable SMBus controller based on config */ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT; /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; -- To view, visit https://review.coreboot.org/c/coreboot/+/39152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Gerrit-Change-Number: 39152 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Subrata Banik (Code Review) 01 Mar '20

01 Mar '20

Subrata Banik has uploaded a new patch set (#10) to the change originally created by Maulik V Vaghela. ( https://review.coreboot.org/c/coreboot/+/39111 ) Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support ...................................................................... soc/intel/tigerlake: Add Jasper lake GPIO support Add gpio definition for Jasper Lake gpio controller. Also created a separate file for JSL and TGL gpios along with separate ASL files for JSL. GPIO controller includes 4 gpio community and 10 groups. Patch adds definition for all gpio within community and groups Updated IRQ mapping for all gpios TEST=Check if jslrvp code is compiling Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Usha P <usha.p(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/acpi/gpio.asl A src/soc/intel/tigerlake/acpi/gpio_jsl.asl A src/soc/intel/tigerlake/acpi/gpio_op.asl A src/soc/intel/tigerlake/acpi/gpio_tgl.asl M src/soc/intel/tigerlake/chip.h A src/soc/intel/tigerlake/gpio_jsl.c R src/soc/intel/tigerlake/gpio_tgl.c M src/soc/intel/tigerlake/include/soc/gpio.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h M src/soc/intel/tigerlake/include/soc/pmc.h 14 files changed, 1,634 insertions(+), 520 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39111/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/39111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Gerrit-Change-Number: 39111 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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