March 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: soc/intel/common/block/smm: add case intrusion to SMI handler
by Michael Niewöhner (Code Review) March 3, 2020

March 3, 2020

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39265 ) Change subject: soc/intel/common/block/smm: add case intrusion to SMI handler ...................................................................... Uploaded patch set 4: Patch Set 3 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/39265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifad675bb09215ada760efebdcd915958febf5778 Gerrit-Change-Number: 39265 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Mar 2020 22:29:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572
by Angel Pons (Code Review) March 3, 2020

March 3, 2020

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mainboard: Add Acer ES1-572 ...................................................................... Patch Set 4: (8 comments) https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/Kconfig: https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 1: ## > IMHO config is not copyrightable I think I get yelled at by the lint scripts if there isn't a copyright notice here. Moreover, there are maaany more Kconfig files with such a notice. https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 16: if BOARD_ACER_ES1_572 || BOARD_ACER_EXTENSA_2540 > if you're sure that there is no other device out there with that board, I'd be ok with that. […] The two symbols only change the part number. Other than that, the boards are the same. No other machine model seems to exist with this board. https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 60: config ADD_FSP_BINARIES : default y > I read somewhere we normally don't set this to default "yes" because coreboot should be free by defa […] Well, default settings enable microcode updates but USE_BLOBS is not set by default. It might be changed at some point. Also, adding FSP binaries by default results in a more comprehensive build test, and the resulting artifacts might as well be used for boot tests. Adding to that, it took me a while to find where that option is to enable it. I wouldn't want others to suffer as much as I did. I mean, I wanted to make sure I could boot fine on the first try, and I somehow managed to do so. https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 261: device pci 1f.0 on end # LPC Interface > no superio? It's a laptop board, and as commit message states, EC suppport is missing. In any case, ENE does not use SuperIO-like EC interfaces, unlike Winbond and ITE. https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/romstage.c: https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 25: static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) > I don't think you need this, since there is no soldered RAM. Can be removed IMO. I'll check, I'm not sure. https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 47: mainboard_fill_rcomp_res_data > same as above No. Don't you see that I actually went through the effort to check the schematics? I even added the names of the actual resistors 😄 https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 54: mainboard_fill_rcomp_strength_data > same No, Rcomp calibration is performed on this board. https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 74: d_fill_dq_map_data(&mem_cfg->DqByteMapCh0, &mem_cfg->DqByteMapCh1); : mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, &mem_cfg->DqsMapCpu2DramCh1); : mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); : mainboard_fill_rcomp_strength_data(&mem_cfg->Rcomp > same Maybe. In any case, I'll need to change this if I remove any of the functions. -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-Comment-Date: Tue, 03 Mar 2020 22:24:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/tco: clear TCO1_STS register, too
by Andrey Petrov (Code Review) March 3, 2020

March 3, 2020

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39259 ) Change subject: soc/intel/common/block/tco: clear TCO1_STS register, too ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia57c203a672fdd0095355a7e2a0e01aaa6657968 Gerrit-Change-Number: 39259 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Mar 2020 22:10:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/soc: icl,cnl,apl,skl,common: enable TCO SMIs
by Michael Niewöhner (Code Review) March 3, 2020

March 3, 2020

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Andrey Petrov, Paul Menzel, Andrey Petrov, Kyösti Mälkki, Patrick Rudolph, Felix Held, HAOUAS Elyes, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39262 to look at the new patch set (#3). Change subject: intel/soc: icl,cnl,apl,skl,common: enable TCO SMIs ...................................................................... intel/soc: icl,cnl,apl,skl,common: enable TCO SMIs Enable TCO SMIs on all platforms using common code. This is needed for the follow-up commits regarding INTRUDER interrupt. Tested on X11SSM-F. Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/common/block/smm/smm.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/skylake/include/soc/pm.h 5 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/39262/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/39262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Gerrit-Change-Number: 39262 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: intel/soc: icl,cnl,apl,skl,common: enable TCO SMIs
by Michael Niewöhner (Code Review) March 3, 2020

March 3, 2020

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39262 ) Change subject: intel/soc: icl,cnl,apl,skl,common: enable TCO SMIs ...................................................................... Uploaded patch set 3. -- To view, visit https://review.coreboot.org/c/coreboot/+/39262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Gerrit-Change-Number: 39262 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Mar 2020 22:08:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/soc: icl,cnl,apl,skl: add INTRUDER relevant registers
by Michael Niewöhner (Code Review) March 3, 2020

March 3, 2020

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39263 ) Change subject: intel/soc: icl,cnl,apl,skl: add INTRUDER relevant registers ...................................................................... Uploaded patch set 3: Patch Set 2 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/39263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If12d21e8e6721abb877cbbfbbba8f0127a86d96b Gerrit-Change-Number: 39263 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Mar 2020 22:08:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: tco: enable intruder SMI
by Michael Niewöhner (Code Review) March 3, 2020

March 3, 2020

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39264 ) Change subject: soc/intel/common/block: tco: enable intruder SMI ...................................................................... Uploaded patch set 3: Patch Set 2 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/39264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7 Gerrit-Change-Number: 39264 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Mar 2020 22:08:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/smm: add case intrusion to SMI handler
by Michael Niewöhner (Code Review) March 3, 2020

March 3, 2020

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39265 ) Change subject: soc/intel/common/block/smm: add case intrusion to SMI handler ...................................................................... Uploaded patch set 3: Patch Set 2 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/39265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifad675bb09215ada760efebdcd915958febf5778 Gerrit-Change-Number: 39265 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Mar 2020 22:08:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572
by Michael Niewöhner (Code Review) March 3, 2020

March 3, 2020

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mainboard: Add Acer ES1-572 ...................................................................... Patch Set 4: (3 comments) https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/romstage.c: https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 47: mainboard_fill_rcomp_res_data same as above https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 54: mainboard_fill_rcomp_strength_data same https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 74: d_fill_dq_map_data(&mem_cfg->DqByteMapCh0, &mem_cfg->DqByteMapCh1); : mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, &mem_cfg->DqsMapCpu2DramCh1); : mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); : mainboard_fill_rcomp_strength_data(&mem_cfg->Rcomp same -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-Comment-Date: Tue, 03 Mar 2020 22:06:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572
by Michael Niewöhner (Code Review) March 3, 2020

March 3, 2020

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mainboard: Add Acer ES1-572 ...................................................................... Patch Set 4: (4 comments) https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/Kconfig: https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 1: ## IMHO config is not copyrightable https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 16: if BOARD_ACER_ES1_572 || BOARD_ACER_EXTENSA_2540 if you're sure that there is no other device out there with that board, I'd be ok with that. otherwise why not use a "baseboard scheme" here? https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 60: config ADD_FSP_BINARIES : default y I read somewhere we normally don't set this to default "yes" because coreboot should be free by default (even when the board does not work) - not sure if that's still true https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 261: device pci 1f.0 on end # LPC Interface no superio? -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-Comment-Date: Tue, 03 Mar 2020 22:03:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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