Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Sooraj Govindan, Aamir Bohra, Justin TerAvest, Rizwan Qureshi, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Karthik Ramasubramanian, Meera Ravindranath, Ronak Kanabar, Usha P, Tim Wawrzynczak, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39111
to look at the new patch set (#12).
Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support
......................................................................
soc/intel/tigerlake: Add Jasper lake GPIO support
Add gpio definition for Jasper Lake gpio controller.
Also created a separate file for JSL and TGL gpio keeping common asl file.
gpio_soc_defs.h must pass correct information/macro values to asl file
for code to work.
GPIO controller includes 4 gpio community and 10 groups. Patch adds
definition for all gpio within community and groups
Updated IRQ mapping for all gpios
TEST=Check if jslrvp and tglrvp code is compiling
Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
Signed-off-by: Usha P <usha.p(a)intel.com>
---
A src/soc/intel/common/acpi/gpio_op.asl
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/acpi/gpio.asl
M src/soc/intel/tigerlake/chip.h
A src/soc/intel/tigerlake/gpio_jsl.c
R src/soc/intel/tigerlake/gpio_tgl.c
M src/soc/intel/tigerlake/include/soc/gpio.h
M src/soc/intel/tigerlake/include/soc/gpio_defs.h
A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h
A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h
M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h
M src/soc/intel/tigerlake/include/soc/pmc.h
13 files changed, 1,424 insertions(+), 475 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39111/12
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Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2
Gerrit-Change-Number: 39111
Gerrit-PatchSet: 12
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
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Gerrit-MessageType: newpatchset
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39111 )
Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support
......................................................................
Patch Set 11:
(6 comments)
https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac…
File src/soc/intel/tigerlake/acpi/gpio_jsl.asl:
https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac…
PS2, Line 20:
> Yes Karthik, I'll check this and work on it.
Done
https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac…
PS2, Line 31: Memory32Fixed (ReadWrite, 0, 0, COM2)
> Do we want to export ACPI objects for GPP_GPD group? I don't see it for TGL. […]
No, this is not required. I have removed it from asl file.
https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac…
PS2, Line 40: /* GPIO Community 0 */
: CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
: CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
: Store (^^PCRB (PID_GPIOCOM0), BAS0)
: Store (GPIO_BASE_SIZE, LEN0)
:
: /* GPIO Community 1 */
: CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
: CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
: Store (^^PCRB (PID_GPIOCOM1), BAS1)
: Store (GPIO_BASE_SIZE, LEN1)
:
: /* GPIO Community 2 */
: CreateDWordField (^RBUF, ^COM2._BAS, BAS2)
: CreateDWordField (^RBUF, ^COM2._LEN, LEN2)
: Store (^^PCRB (PID_GPIOCOM2), BAS2)
: Store (GPIO_BASE_SIZE, LEN2)
:
: /* GPIO Community 4 */
: CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
: CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
: Store (^^PCRB (PID_GPIOCOM4), BAS4)
: Store (GPIO_BASE_SIZE, LEN4)
:
: /* GPIO Community 5 */
: CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
: CreateDWordField (^RBUF, ^COM5._LEN, LEN5)
: Store (^^PCRB (PID_GPIOCOM5), BAS5)
: Store (GPIO_BASE_SIZE, LEN5)
> Let me check this. since I am on vacation I may take a day or two to correct it.
Done
https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac…
File src/soc/intel/tigerlake/acpi/gpio_op.asl:
PS2:
> +1
Done
https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac…
File src/soc/intel/tigerlake/acpi/gpio_tgl.asl:
https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/ac…
PS2, Line 84: BAS4 = ^^PCRB (PID_GPIOCOM4)
> Similar to what I mentioned in the gpio_jsl. […]
Done
https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/in…
File src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h:
https://review.coreboot.org/c/coreboot/+/39111/2/src/soc/intel/tigerlake/in…
PS2, Line 67: GPIO_RSVD_0
> These are soc reserved gpio pins that's why name is reserved.
Done
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Gerrit-Project: coreboot
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Gerrit-Change-Number: 39111
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Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-MessageType: comment
Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Sooraj Govindan, Aamir Bohra, Justin TerAvest, Rizwan Qureshi, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Karthik Ramasubramanian, Meera Ravindranath, Ronak Kanabar, Usha P, Tim Wawrzynczak, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39111
to look at the new patch set (#11).
Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support
......................................................................
soc/intel/tigerlake: Add Jasper lake GPIO support
Add gpio definition for Jasper Lake gpio controller.
Also created a separate file for JSL and TGL gpio keeping common asl file.
gpio_soc_defs.h must pass correct information/macro values to asl file
for code to work.
GPIO controller includes 4 gpio community and 10 groups. Patch adds
definition for all gpio within community and groups
Updated IRQ mapping for all gpios
TEST=Check if jslrvp and tglrvp code is compiling
Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
Signed-off-by: Usha P <usha.p(a)intel.com>
---
A src/soc/intel/common/acpi/gpio_op.asl
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/acpi/gpio.asl
M src/soc/intel/tigerlake/chip.h
A src/soc/intel/tigerlake/gpio_jsl.c
R src/soc/intel/tigerlake/gpio_tgl.c
M src/soc/intel/tigerlake/include/soc/gpio.h
M src/soc/intel/tigerlake/include/soc/gpio_defs.h
A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h
A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h
M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h
M src/soc/intel/tigerlake/include/soc/pmc.h
13 files changed, 1,424 insertions(+), 475 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39111/11
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Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39111 )
Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support
......................................................................
Patch Set 10:
> Patch Set 7:
>
> @Maulik, please sit on tree and don't break the tree as we are seeing rebasing issue
Sure Subrata..I will take care of it.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 )
Change subject: [WIP] mainboard: Add Acer ES1-572
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38978/3//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/38978/3//COMMIT_MSG@31
PS3, Line 31: UART 2
> The FSP has a UPD to enable these. Try using: […]
Yes, I had issues with that before. Now it works.
Also, I forgot to send this message yesterday. It's not really verbose, most of the fun stuff is done inside FSP anyway.
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Subrata Banik has uploaded a new patch set (#10) to the change originally created by Maulik V Vaghela. ( https://review.coreboot.org/c/coreboot/+/39111 )
Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support
......................................................................
soc/intel/tigerlake: Add Jasper lake GPIO support
Add gpio definition for Jasper Lake gpio controller.
Also created a separate file for JSL and TGL gpios along with separate
ASL files for JSL.
GPIO controller includes 4 gpio community and 10 groups. Patch adds
definition for all gpio within community and groups
Updated IRQ mapping for all gpios
TEST=Check if jslrvp code is compiling
Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
Signed-off-by: Usha P <usha.p(a)intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/acpi/gpio.asl
A src/soc/intel/tigerlake/acpi/gpio_jsl.asl
A src/soc/intel/tigerlake/acpi/gpio_op.asl
A src/soc/intel/tigerlake/acpi/gpio_tgl.asl
M src/soc/intel/tigerlake/chip.h
A src/soc/intel/tigerlake/gpio_jsl.c
R src/soc/intel/tigerlake/gpio_tgl.c
M src/soc/intel/tigerlake/include/soc/gpio.h
M src/soc/intel/tigerlake/include/soc/gpio_defs.h
A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h
A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h
A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h
M src/soc/intel/tigerlake/include/soc/pmc.h
14 files changed, 1,634 insertions(+), 520 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39111/10
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