coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block/tco: clear TCO1_STS register, too
by Michael Niewöhner (Code Review) 03 Mar '20

03 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39259 ) Change subject: soc/intel/common/block/tco: clear TCO1_STS register, too ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/39259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia57c203a672fdd0095355a7e2a0e01aaa6657968 Gerrit-Change-Number: 39259 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Tue, 03 Mar 2020 17:46:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: i82371eb: Drop ops entry for i82371sb
by Keith Hui (Code Review) 03 Mar '20

03 Mar '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38598 ) Change subject: i82371eb: Drop ops entry for i82371sb ...................................................................... i82371eb: Drop ops entry for i82371sb All boards with this chipset use i82371eb (that shares PCI ID with i82371ab). Change-Id: Iab1e83b8f5fff44a33619c7925e5448169a2a87c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/isa.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38598/1 diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 00fbb77..1442470 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -158,9 +158,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82371AB_ISA, }; - -static const struct pci_driver isa_SB_driver __pci_driver = { - .ops = &isa_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371SB_ISA, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/38598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab1e83b8f5fff44a33619c7925e5448169a2a87c Gerrit-Change-Number: 38598 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron/mal10: Add COMe-mAL10 minimal support
by Maxim Polyakov (Code Review) 03 Mar '20

03 Mar '20

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Change in coreboot[master]: mb/kontron/mal10: Add COMe-mAL10 minimal support
by Maxim Polyakov (Code Review) 03 Mar '20

03 Mar '20

Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Angel Pons, Andrey Petrov, Patrick Rudolph, Aaron Durbin, Lance Zhao, Nico Huber, Martin Roth, Werner Zeh, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39133 to look at the new patch set (#10). Change subject: mb/kontron/mal10: Add COMe-mAL10 minimal support ...................................................................... mb/kontron/mal10: Add COMe-mAL10 minimal support This patch adds minimal support for the Kontron COMe-mAL10 module with the Apollo Lake processor together with Kontron T10-TNI carrierboard. Working: - console (Kontron CPLD) - USB2/3 - Ethernet network - eMMC - SATA - PCIe ports - Video/DP (*) Not tested: - Video/LVDS TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) - SDIO - Documentation As the payload was used: - Tianocore (*)(**) - SeaBIOS (*) (*) Video works only in linux (**) Works only with Tianocore "UEFIPayload" payload edk2-stable201903-1569-g3e63a91 (**) Booting with the "CorebootPayload" crashes: https://pastebin.com/cpCfrPCL Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A src/mainboard/kontron/mal10/Kconfig A src/mainboard/kontron/mal10/Kconfig.name A src/mainboard/kontron/mal10/Makefile.inc A src/mainboard/kontron/mal10/acpi/dptf.asl A src/mainboard/kontron/mal10/board_info.txt A src/mainboard/kontron/mal10/bootblock.c A src/mainboard/kontron/mal10/cmos.default A src/mainboard/kontron/mal10/cmos.layout A src/mainboard/kontron/mal10/data.vbt A src/mainboard/kontron/mal10/dsdt.asl A src/mainboard/kontron/mal10/gma-mainboard.ads A src/mainboard/kontron/mal10/gpio.h A src/mainboard/kontron/mal10/mal10.fmd A src/mainboard/kontron/mal10/ramstage.c A src/mainboard/kontron/mal10/romstage.c A src/mainboard/kontron/mal10/variants/baseboard/devicetree.cb A src/mainboard/kontron/mal10/variants/t10-tni/overridetree.cb 17 files changed, 1,153 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39133/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 10 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/kontron/mal10: Add COMe-mAL10 minimal support
by Maxim Polyakov (Code Review) 03 Mar '20

03 Mar '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron/mal10: Add COMe-mAL10 minimal support ...................................................................... Patch Set 9: (10 comments) Thanks for the review https://review.coreboot.org/c/coreboot/+/39133/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39133/8//COMMIT_MSG@7 PS8, Line 7: md > mb? Done https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… File src/mainboard/kontron/mal10/acpi_tables.c: PS8: > This shouldn't be needed anymore Removed https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… File src/mainboard/kontron/mal10/board_info.txt: https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… PS8, Line 7: Flashrom support: n > Not supported at all? Sorry, I didn't notice flash chip "W25Q128" (16384 kB, SPI) Yes it is supported fixed https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… File src/mainboard/kontron/mal10/dsdt.asl: https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… PS8, Line 29: /* CPU */ > This comment does not add much value. […] Done https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… PS8, Line 32: Scope (\_SB) { : Device (PCI0) > Can use: […] Done https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… PS8, Line 40: /* Chipset specific sleep states */ > This comment was removed not too long ago Done https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… File src/mainboard/kontron/mal10/gpio.h: https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… PS8, Line 161: #if 0 : PAD_CFG_NF_IOSSTATE(GPIO_196, NATIVE, DEEP, NF1, MASK), /* PNL1_VDDEN */ : PAD_CFG_NF_IOSSTATE(GPIO_197, NATIVE, DEEP, NF1, MASK), /* PNL1_BKLTEN */ : PAD_CFG_NF_IOSSTATE(GPIO_198, NATIVE, DEEP, NF1, MASK), /* PNL1_BKLTCTL */ > why dead code? Sorry, I forgot to delete this lvds is currently disabled for this board There is no device to test this interface https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… File src/mainboard/kontron/mal10/mainboard.c: PS8: > This seems to be dead code. Yes you are right. And since I don't use VGA_ROM_RUN, call install_intel_vga_int15_handler isn't needed. https://github.com/coreboot/coreboot/blob/ef7a3267870f126cc2f815812cfe54500… Removed https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… File src/mainboard/kontron/mal10/mal10.fmd: https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… PS8, Line 13: 0xb7d000 > If you remove this size, the region will expand as much as possible. It helps to prevent gaps. Done, thanks https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… File src/mainboard/kontron/mal10/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/39133/8/src/mainboard/kontron/mal1… PS8, Line 75: IGPU > iGPU Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 9 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Mar 2020 16:38:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Andrey Petrov <anpetrov(a)fb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/apl: add options to override USB port config
by Maxim Polyakov (Code Review) 03 Mar '20

03 Mar '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38815 ) Change subject: soc/apl: add options to override USB port config ...................................................................... Patch Set 17: (1 comment) Thanks for the review https://review.coreboot.org/c/coreboot/+/38815/16/src/soc/intel/apollolake/… File src/soc/intel/apollolake/include/soc/usb.h: https://review.coreboot.org/c/coreboot/+/38815/16/src/soc/intel/apollolake/… PS16, Line 56: 0 > OC_SKIP? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia94a2be1647f7743ef0c918ae3b34437a179261c Gerrit-Change-Number: 38815 Gerrit-PatchSet: 17 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Mar 2020 16:23:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/apl: add options to override USB port config
by Maxim Polyakov (Code Review) 03 Mar '20

03 Mar '20

Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Angel Pons, Subrata Banik, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38815 to look at the new patch set (#17). Change subject: soc/apl: add options to override USB port config ...................................................................... soc/apl: add options to override USB port config Allows to overload the PortUsb20Enable and PortUsb30Enable FSP options (which are set to 1 by default) to enable/disable USB ports if the usb_config_override flag is set to "1". Therefore, these changes will not affect other boards with an Apollo Lake processor. Change-Id: Ia94a2be1647f7743ef0c918ae3b34437a179261c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/include/soc/usb.h 3 files changed, 49 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/38815/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/38815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia94a2be1647f7743ef0c918ae3b34437a179261c Gerrit-Change-Number: 38815 Gerrit-PatchSet: 17 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/kontron/mal10: Add COMe-mAL10 minimal support
by Maxim Polyakov (Code Review) 03 Mar '20

03 Mar '20

Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Angel Pons, Andrey Petrov, Patrick Rudolph, Aaron Durbin, Lance Zhao, Nico Huber, Martin Roth, Werner Zeh, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39133 to look at the new patch set (#9). Change subject: mb/kontron/mal10: Add COMe-mAL10 minimal support ...................................................................... mb/kontron/mal10: Add COMe-mAL10 minimal support This patch adds minimal support for the Kontron COMe-mAL10 module with the Apollo Lake processor together with Kontron T10-TNI carrierboard. Working: - console (Kontron CPLD) - USB2/3 - Ethernet network - eMMC - SATA - PCIe ports - Video/DP (*) Not tested: - Video/LVDS TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) - SDIO - Documentation As the payload was used: - Tianocore (*)(**) - SeaBIOS (*) (*) Video works only in linux (**) Works only with Tianocore "UEFIPayload" payload edk2-stable201903-1569-g3e63a91 (**) Booting with the "CorebootPayload" crashes: https://pastebin.com/cpCfrPCL Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A src/mainboard/kontron/mal10/Kconfig A src/mainboard/kontron/mal10/Kconfig.name A src/mainboard/kontron/mal10/Makefile.inc A src/mainboard/kontron/mal10/acpi/dptf.asl A src/mainboard/kontron/mal10/board_info.txt A src/mainboard/kontron/mal10/bootblock.c A src/mainboard/kontron/mal10/cmos.default A src/mainboard/kontron/mal10/cmos.layout A src/mainboard/kontron/mal10/data.vbt A src/mainboard/kontron/mal10/dsdt.asl A src/mainboard/kontron/mal10/gma-mainboard.ads A src/mainboard/kontron/mal10/gpio.h A src/mainboard/kontron/mal10/mal10.fmd A src/mainboard/kontron/mal10/ramstage.c A src/mainboard/kontron/mal10/romstage.c A src/mainboard/kontron/mal10/variants/baseboard/devicetree.cb A src/mainboard/kontron/mal10/variants/t10-tni/overridetree.cb 17 files changed, 1,169 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39133/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 9 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/up/squared: remove NpkEn option from romstage
by Maxim Polyakov (Code Review) 03 Mar '20

03 Mar '20

Hello Felix Singer, build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39120 to look at the new patch set (#11). Change subject: mb/up/squared: remove NpkEn option from romstage ...................................................................... mb/up/squared: remove NpkEn option from romstage There is no need to set the NpkEn option to disable the NPK device, since it has already been done in the devicetree. Change-Id: I429f1129dc4149067503cd2ff9fb4c76cdc919f0 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/up/squared/romstage.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/39120/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/39120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I429f1129dc4149067503cd2ff9fb4c76cdc919f0 Gerrit-Change-Number: 39120 Gerrit-PatchSet: 11 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/lynxpoint: hook up smmstore
by Matt DeVillier (Code Review) 03 Mar '20

03 Mar '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39189 ) Change subject: sb/lynxpoint: hook up smmstore ...................................................................... sb/lynxpoint: hook up smmstore Adapted from implementation in sb/intel/common. Test: build/boot variants of google/{beltino,slippy} with Tianocore and SMMSTORE enabled Change-Id: I64f520d17146206b8b9b41fc4f827539c5cfd507 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/southbridge/intel/lynxpoint/smihandler.c 1 file changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/39189/1 diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 72c3447..44fef1c 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -29,7 +29,7 @@ #include <southbridge/intel/common/finalize.h> #include <northbridge/intel/haswell/haswell.h> #include <cpu/intel/haswell/haswell.h> - +#include <smmstore.h> #include "me.h" #include "pch.h" #include "nvs.h" @@ -266,6 +266,26 @@ *ret = gsmi_exec(sub_command, param); } +static void southbridge_smi_store(void) +{ + u8 sub_command, ret; + em64t101_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(APM_CNT_SMMSTORE); + uint32_t reg_ebx; + + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* drivers/smmstore/smi.c */ + ret = smmstore_exec(sub_command, (void *)reg_ebx); + io_smi->rax = ret; +} + static void southbridge_smi_apmc(void) { u8 reg8; @@ -332,6 +352,10 @@ if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); break; + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + southbridge_smi_store(); + break; } mainboard_smi_apmc(reg8); -- To view, visit https://review.coreboot.org/c/coreboot/+/39189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64f520d17146206b8b9b41fc4f827539c5cfd507 Gerrit-Change-Number: 39189 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2020