coreboot-gerrit March 2020

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Change in coreboot[master]: soc/intel/gpio_defs: add a new macro for pad config
by Patrick Georgi (Code Review) 03 Mar '20

03 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38813 ) Change subject: soc/intel/gpio_defs: add a new macro for pad config ...................................................................... soc/intel/gpio_defs: add a new macro for pad config Adds PAD_CFG_NF_BUF_IOSSTATE_IOSTERM macro to configure native function, iosstate, iosterm and disable input/output buffer. This is used in the pad configurations for the Kontron COMe-mAL10 module board [1]. [1] https://review.coreboot.org/c/coreboot/+/39133 Change-Id: I7aa4d4dee34bd46a064079c576ed64525fd489e6 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38813 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 3e9250e..dda0247 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -226,6 +226,11 @@ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) +/* Configure native function, iosstate, iosterm and disable input/output buffer */ +#define PAD_CFG_NF_BUF_IOSSTATE_IOSTERM(pad, pull, rst, func, bufdis, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_BUF(bufdis) | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/38813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa4d4dee34bd46a064079c576ed64525fd489e6 Gerrit-Change-Number: 38813 Gerrit-PatchSet: 16 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake
by Patrick Georgi (Code Review) 03 Mar '20

03 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39168 ) Change subject: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake ...................................................................... vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake Update FSPM header to add Vtd related Upds for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I063f921832a4e4a45eb6978b6dbb37b1ac7dde7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/39168 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: caveh jalali <caveh(a)chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h 1 file changed, 68 insertions(+), 39 deletions(-) Approvals: build bot (Jenkins): Verified Srinidhi N Kaushik: Looks good to me, but someone else must approve caveh jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index e81131d..9bc1a40 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -269,7 +269,12 @@ /** Offset 0x015C - Reserved **/ - UINT8 Reserved4[40]; + UINT8 Reserved4[4]; + +/** Offset 0x0160 - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + UINT32 VtdBaseAddress[9]; /** Offset 0x0184 - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) @@ -277,9 +282,33 @@ **/ UINT8 VtdDisable; -/** Offset 0x0185 - Reserved +/** Offset 0x0185 - Vtd Programming for Igd + 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar + programming disabled) + $EN_DIS **/ - UINT8 Reserved5[4]; + UINT8 VtdIgdEnable; + +/** Offset 0x0186 - Vtd Programming for Ipu + 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIpuEnable; + +/** Offset 0x0187 - Vtd Programming for Iop + 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIopEnable; + +/** Offset 0x0188 - Vtd Programming for ITbt + 1=Enable/TRUE (ITbt VT-d Bar programming enabled), 0=Disable/FLASE (ITbt VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdItbtEnable; /** Offset 0x0189 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. @@ -297,7 +326,7 @@ /** Offset 0x018B - Reserved **/ - UINT8 Reserved6; + UINT8 Reserved5; /** Offset 0x018C - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile @@ -308,7 +337,7 @@ /** Offset 0x018D - Reserved **/ - UINT8 Reserved7[3]; + UINT8 Reserved6[3]; /** Offset 0x0190 - SA GV System Agent dynamic frequency support and when enabled memory will be training @@ -319,7 +348,7 @@ /** Offset 0x0191 - Reserved **/ - UINT8 Reserved8[2]; + UINT8 Reserved7[2]; /** Offset 0x0193 - Rank Margin Tool Enable/disable Rank Margin Tool. @@ -329,7 +358,7 @@ /** Offset 0x0194 - Reserved **/ - UINT8 Reserved9[10]; + UINT8 Reserved8[10]; /** Offset 0x019E - Memory Reference Clock 100MHz, 133MHz. @@ -339,7 +368,7 @@ /** Offset 0x019F - Reserved **/ - UINT8 Reserved10[22]; + UINT8 Reserved9[22]; /** Offset 0x01B5 - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller @@ -355,17 +384,17 @@ /** Offset 0x01B7 - Reserved **/ - UINT8 Reserved11[166]; + UINT8 Reserved10[166]; /** Offset 0x025D - IMGU CLKOUT Configuration The configuration of IMGU CLKOUT, 0: Disable;1: Enable. $EN_DIS **/ - UINT8 ImguClkOutEn[5]; + UINT8 ImguClkOutEn[6]; -/** Offset 0x0262 - Reserved +/** Offset 0x0263 - Reserved **/ - UINT8 Reserved12[7]; + UINT8 Reserved11[6]; /** Offset 0x0269 - RpClockReqMsgEnable **/ @@ -377,7 +406,7 @@ /** Offset 0x026E - Reserved **/ - UINT8 Reserved13[3]; + UINT8 Reserved12[3]; /** Offset 0x0271 - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -477,7 +506,7 @@ /** Offset 0x0281 - Reserved **/ - UINT8 Reserved14[126]; + UINT8 Reserved13[126]; /** Offset 0x02FF - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane @@ -486,7 +515,7 @@ /** Offset 0x0307 - Reserved **/ - UINT8 Reserved15[22]; + UINT8 Reserved14[22]; /** Offset 0x031D - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM @@ -498,7 +527,7 @@ /** Offset 0x031E - Reserved **/ - UINT8 Reserved16[5]; + UINT8 Reserved15[5]; /** Offset 0x0323 - Hyper Threading Enable/Disable Enable or Disable Hyper Threading; 0: Disable; 1: Enable @@ -508,7 +537,7 @@ /** Offset 0x0324 - Reserved **/ - UINT8 Reserved17; + UINT8 Reserved16; /** Offset 0x0325 - CPU ratio value CPU ratio value. Valid Range 0 to 63 @@ -517,7 +546,7 @@ /** Offset 0x0326 - Reserved **/ - UINT8 Reserved18[2]; + UINT8 Reserved17[2]; /** Offset 0x0328 - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- @@ -528,7 +557,7 @@ /** Offset 0x0329 - Reserved **/ - UINT8 Reserved19; + UINT8 Reserved18; /** Offset 0x032A - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable. @@ -538,7 +567,7 @@ /** Offset 0x032B - Reserved **/ - UINT8 Reserved20[31]; + UINT8 Reserved19[31]; /** Offset 0x034A - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -552,7 +581,7 @@ /** Offset 0x034C - Reserved **/ - UINT8 Reserved21[4]; + UINT8 Reserved20[4]; /** Offset 0x0350 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -566,7 +595,7 @@ /** Offset 0x0358 - Reserved **/ - UINT8 Reserved22[8]; + UINT8 Reserved21[8]; /** Offset 0x0360 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable @@ -580,7 +609,7 @@ /** Offset 0x0368 - Reserved **/ - UINT8 Reserved23[522]; + UINT8 Reserved22[522]; /** Offset 0x0572 - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. @@ -589,7 +618,7 @@ /** Offset 0x0573 - Reserved **/ - UINT8 Reserved24[4]; + UINT8 Reserved23[4]; /** Offset 0x0577 - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use @@ -604,7 +633,7 @@ /** Offset 0x0597 - Reserved **/ - UINT8 Reserved25[5]; + UINT8 Reserved24[5]; /** Offset 0x059C - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -627,7 +656,7 @@ /** Offset 0x05A2 - Reserved **/ - UINT8 Reserved26[14]; + UINT8 Reserved25[14]; /** Offset 0x05B0 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -637,7 +666,7 @@ /** Offset 0x05B1 - Reserved **/ - UINT8 Reserved27[4]; + UINT8 Reserved26[4]; /** Offset 0x05B5 - MRC Safe Config Enables/Disable MRC Safe Config @@ -683,7 +712,7 @@ /** Offset 0x05BC - Reserved **/ - UINT8 Reserved28[4]; + UINT8 Reserved27[4]; /** Offset 0x05C0 - Early Command Training Enables/Disable Early Command Training @@ -693,7 +722,7 @@ /** Offset 0x05C1 - Reserved **/ - UINT8 Reserved29[109]; + UINT8 Reserved28[109]; /** Offset 0x062E - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -703,7 +732,7 @@ /** Offset 0x0630 - Reserved **/ - UINT8 Reserved30[62]; + UINT8 Reserved29[62]; /** Offset 0x066E - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, @@ -716,7 +745,7 @@ /** Offset 0x066F - Reserved **/ - UINT8 Reserved31[2]; + UINT8 Reserved30[2]; /** Offset 0x0671 - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) @@ -726,7 +755,7 @@ /** Offset 0x0672 - Reserved **/ - UINT8 Reserved32[2]; + UINT8 Reserved31[2]; /** Offset 0x0674 - TCSS USB Port Enable Bitmap for per port enabling @@ -735,7 +764,7 @@ /** Offset 0x0675 - Reserved **/ - UINT8 Reserved33[80]; + UINT8 Reserved32[80]; /** Offset 0x06C5 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -746,7 +775,7 @@ /** Offset 0x06C6 - Reserved **/ - UINT8 Reserved34[2]; + UINT8 Reserved33[2]; /** Offset 0x06C8 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 @@ -756,7 +785,7 @@ /** Offset 0x06C9 - Reserved **/ - UINT8 Reserved35[122]; + UINT8 Reserved34[122]; /** Offset 0x0743 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. @@ -766,7 +795,7 @@ /** Offset 0x0744 - Reserved **/ - UINT8 Reserved36[3]; + UINT8 Reserved35[3]; /** Offset 0x0747 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -775,7 +804,7 @@ /** Offset 0x0749 - Reserved **/ - UINT8 Reserved37[3]; + UINT8 Reserved36[3]; /** Offset 0x074C - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* @@ -795,7 +824,7 @@ /** Offset 0x075D - Reserved **/ - UINT8 Reserved38[3]; + UINT8 Reserved37[3]; /** Offset 0x0760 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* @@ -832,7 +861,7 @@ /** Offset 0x0775 - Reserved **/ - UINT8 Reserved39[355]; + UINT8 Reserved38[355]; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/39168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I063f921832a4e4a45eb6978b6dbb37b1ac7dde7f Gerrit-Change-Number: 39168 Gerrit-PatchSet: 3 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: LGA1155 mainboards: Remove gfx.did and gfx.ndid
by Angel Pons (Code Review) 03 Mar '20

03 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39184 ) Change subject: LGA1155 mainboards: Remove gfx.did and gfx.ndid ...................................................................... LGA1155 mainboards: Remove gfx.did and gfx.ndid They are downright useless and result in ACPI errors. So, burn them. Also, do a minor update to autoport's README about these values. Change-Id: Idb5832cfd2e3043b8d70e13cbbe8bd94ad613120 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asus/p8h61-m_pro/devicetree.cb M src/mainboard/asus/p8z77-m_pro/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb M src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/z220_sff_workstation/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M util/autoport/readme.md 11 files changed, 1 insertion(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/39184/1 diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 32438a1..3fa3dec 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -15,9 +15,7 @@ # chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" register "gfx.link_frequency_270_mhz" = "0" - register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" register "gpu_cpu_backlight" = "0x00000000" register "gpu_dp_b_hotplug" = "4" diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index ee9a0fc4..ea64369 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -14,8 +14,6 @@ ## chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - register "gfx.ndid" = "3" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" diff --git a/src/mainboard/asus/p8z77-m_pro/devicetree.cb b/src/mainboard/asus/p8z77-m_pro/devicetree.cb index 0bec95c..cbc1629 100644 --- a/src/mainboard/asus/p8z77-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8z77-m_pro/devicetree.cb @@ -14,8 +14,6 @@ ## chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - register "gfx.ndid" = "3" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index e581470..fbc31b7 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -1,7 +1,4 @@ chip northbridge/intel/sandybridge - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" device cpu_cluster 0 on chip cpu/intel/model_206ax diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb index e4ec810..317d797 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb @@ -14,8 +14,6 @@ ## chip northbridge/intel/sandybridge - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb index 22d483e..a11ba0e 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb @@ -14,8 +14,6 @@ ## chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - register "gfx.ndid" = "3" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 9dc18be..de97bba 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -15,9 +15,7 @@ ## chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" register "gfx.link_frequency_270_mhz" = "0" - register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index ab6ee04..6c8ec4b 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -15,9 +15,7 @@ ## chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" register "gfx.link_frequency_270_mhz" = "0" - register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 9753c32..f520ea4 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -1,7 +1,5 @@ chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" register "gfx.link_frequency_270_mhz" = "0" - register "gfx.ndid" = "3" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 468c35a..9a42a7b 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -15,8 +15,6 @@ # chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - register "gfx.ndid" = "3" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 9af08f4..bfaaef6 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -342,7 +342,7 @@ ## `gfx.ndid` and `gfx.did` Those describe which video outputs are declared in ACPI tables. -Normally, there is no need to adjust these values, but if you miss some +Normally, there is no need to have these values, but if you miss some non-standard video output, you can declare it there. Bit 31 is set to indicate the presence of the output. Byte 1 is the type and byte 0 is used for disambigution so that ID composed of byte 1 and 0 is unique. -- To view, visit https://review.coreboot.org/c/coreboot/+/39184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb5832cfd2e3043b8d70e13cbbe8bd94ad613120 Gerrit-Change-Number: 39184 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion: Enable cbfs SAR value
by EricR Lai (Code Review) 03 Mar '20

03 Mar '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39194 ) Change subject: mb/google/drallion: Enable cbfs SAR value ...................................................................... mb/google/drallion: Enable cbfs SAR value Enable read SAR value from cbfs. BUG=b:150347463 TEST=NA Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I5f27b6f7245669728e3e394e9c6a39c11bfda3b8 --- M src/mainboard/google/drallion/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/39194/1 diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 61bae2b..3380e75 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -25,6 +25,7 @@ select USE_SAR select SAR_ENABLE select DSAR_ENABLE + select WIFI_SAR_CBFS if BOARD_GOOGLE_BASEBOARD_DRALLION -- To view, visit https://review.coreboot.org/c/coreboot/+/39194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f27b6f7245669728e3e394e9c6a39c11bfda3b8 Gerrit-Change-Number: 39194 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/intel/tigerlake: configure ethernet fsp param
by Wonkyu Kim (Code Review) 03 Mar '20

03 Mar '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39153 ) Change subject: soc/intel/tigerlake: configure ethernet fsp param ...................................................................... soc/intel/tigerlake: configure ethernet fsp param Configure ethernet based on board config BUG=none BRANCH=none TEST= build TGLRVP and check ethernet is disabled based on devicetree Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8 --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/39153/1 diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index d22cde0..b8a7d91 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -135,6 +135,13 @@ sizeof(params->SataPortsDevSlp)); } + /* Lan */ + dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); + if (!dev) + params->PchLanEnable = 0; + else + params->PchLanEnable = dev->enabled; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; -- To view, visit https://review.coreboot.org/c/coreboot/+/39153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8 Gerrit-Change-Number: 39153 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: treewide: Replace BOARD_EMULATION_QEMU_X86
by Angel Pons (Code Review) 03 Mar '20

03 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39182 ) Change subject: treewide: Replace BOARD_EMULATION_QEMU_X86 ...................................................................... treewide: Replace BOARD_EMULATION_QEMU_X86 It is equivalent to the CPU_QEMU_X86 symbol. Change-Id: Ic16233e3d80bab62cc97fd075bdcca1780a6a2b5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/console/Kconfig M src/device/pci_rom.c M src/drivers/emulation/qemu/Kconfig M src/mainboard/emulation/Kconfig 4 files changed, 3 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/39182/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index cc18ec3..b893698 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -280,7 +280,7 @@ config CONSOLE_QEMU_DEBUGCON bool "QEMU debug console output" - depends on BOARD_EMULATION_QEMU_X86 + depends on CPU_QEMU_X86 default y help Send coreboot debug output to QEMU's isa-debugcon device: diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 3676f9c..816255d 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -59,7 +59,7 @@ rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); if (rom_address == 0x00000000 || rom_address == 0xffffffff) { -#if CONFIG(BOARD_EMULATION_QEMU_X86) +#if CONFIG(CPU_QEMU_X86) if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) rom_address = 0xc0000; else diff --git a/src/drivers/emulation/qemu/Kconfig b/src/drivers/emulation/qemu/Kconfig index 58daaa44..c271825 100644 --- a/src/drivers/emulation/qemu/Kconfig +++ b/src/drivers/emulation/qemu/Kconfig @@ -1,7 +1,7 @@ config DRIVERS_EMULATION_QEMU_BOCHS bool "bochs dispi interface vga driver" default y - depends on BOARD_EMULATION_QEMU_X86 + depends on CPU_QEMU_X86 depends on MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER select HAVE_LINEAR_FRAMEBUFFER diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 41804e0..9ef8df0 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -8,11 +8,6 @@ endchoice -config BOARD_EMULATION_QEMU_X86 - bool - default y - depends on CPU_QEMU_X86 - source "src/mainboard/emulation/*/Kconfig" config MAINBOARD_VENDOR -- To view, visit https://review.coreboot.org/c/coreboot/+/39182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic16233e3d80bab62cc97fd075bdcca1780a6a2b5 Gerrit-Change-Number: 39182 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/emulation/Kconfig: Redefine BOARD_EMULATION_QEMU_X86
by Angel Pons (Code Review) 03 Mar '20

03 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39181 ) Change subject: mb/emulation/Kconfig: Redefine BOARD_EMULATION_QEMU_X86 ...................................................................... mb/emulation/Kconfig: Redefine BOARD_EMULATION_QEMU_X86 Use CPU_QEMU_X86 as it is selected by both Qemu x86 mainboards. Change-Id: I8d6bfbddeeb8f2c66c5ea7728a9919e7cda86e7e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/emulation/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/39181/1 diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 759b1de..41804e0 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -11,7 +11,7 @@ config BOARD_EMULATION_QEMU_X86 bool default y - depends on BOARD_EMULATION_QEMU_X86_I440FX || BOARD_EMULATION_QEMU_X86_Q35 + depends on CPU_QEMU_X86 source "src/mainboard/emulation/*/Kconfig" -- To view, visit https://review.coreboot.org/c/coreboot/+/39181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d6bfbddeeb8f2c66c5ea7728a9919e7cda86e7e Gerrit-Change-Number: 39181 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/Kconfig: Align ROM size options
by Angel Pons (Code Review) 03 Mar '20

03 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39180 ) Change subject: mb/Kconfig: Align ROM size options ...................................................................... mb/Kconfig: Align ROM size options Change-Id: I0160e72a8961f1aa34982f6348825708e7be9c40 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/Kconfig 1 file changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39180/1 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index df80e64..336474f 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -44,16 +44,16 @@ # TODO: No help text possible for choice fields? choice prompt "ROM chip size" - default COREBOOT_ROMSIZE_KB_64 if BOARD_ROMSIZE_KB_64 - default COREBOOT_ROMSIZE_KB_128 if BOARD_ROMSIZE_KB_128 - default COREBOOT_ROMSIZE_KB_256 if BOARD_ROMSIZE_KB_256 - default COREBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 - default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 - default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 - default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 - default COREBOOT_ROMSIZE_KB_5120 if BOARD_ROMSIZE_KB_5120 - default COREBOOT_ROMSIZE_KB_6144 if BOARD_ROMSIZE_KB_6144 - default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 + default COREBOOT_ROMSIZE_KB_64 if BOARD_ROMSIZE_KB_64 + default COREBOOT_ROMSIZE_KB_128 if BOARD_ROMSIZE_KB_128 + default COREBOOT_ROMSIZE_KB_256 if BOARD_ROMSIZE_KB_256 + default COREBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 + default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 + default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 + default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 + default COREBOOT_ROMSIZE_KB_5120 if BOARD_ROMSIZE_KB_5120 + default COREBOOT_ROMSIZE_KB_6144 if BOARD_ROMSIZE_KB_6144 + default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 default COREBOOT_ROMSIZE_KB_10240 if BOARD_ROMSIZE_KB_10240 default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 @@ -145,16 +145,16 @@ # Map the config names to an integer (KB). config COREBOOT_ROMSIZE_KB int - default 64 if COREBOOT_ROMSIZE_KB_64 - default 128 if COREBOOT_ROMSIZE_KB_128 - default 256 if COREBOOT_ROMSIZE_KB_256 - default 512 if COREBOOT_ROMSIZE_KB_512 - default 1024 if COREBOOT_ROMSIZE_KB_1024 - default 2048 if COREBOOT_ROMSIZE_KB_2048 - default 4096 if COREBOOT_ROMSIZE_KB_4096 - default 5120 if COREBOOT_ROMSIZE_KB_5120 - default 6144 if COREBOOT_ROMSIZE_KB_6144 - default 8192 if COREBOOT_ROMSIZE_KB_8192 + default 64 if COREBOOT_ROMSIZE_KB_64 + default 128 if COREBOOT_ROMSIZE_KB_128 + default 256 if COREBOOT_ROMSIZE_KB_256 + default 512 if COREBOOT_ROMSIZE_KB_512 + default 1024 if COREBOOT_ROMSIZE_KB_1024 + default 2048 if COREBOOT_ROMSIZE_KB_2048 + default 4096 if COREBOOT_ROMSIZE_KB_4096 + default 5120 if COREBOOT_ROMSIZE_KB_5120 + default 6144 if COREBOOT_ROMSIZE_KB_6144 + default 8192 if COREBOOT_ROMSIZE_KB_8192 default 10240 if COREBOOT_ROMSIZE_KB_10240 default 12288 if COREBOOT_ROMSIZE_KB_12288 default 16384 if COREBOOT_ROMSIZE_KB_16384 @@ -164,18 +164,18 @@ # Map the config names to a hex value (bytes). config ROM_SIZE hex - default 0x10000 if COREBOOT_ROMSIZE_KB_64 - default 0x20000 if COREBOOT_ROMSIZE_KB_128 - default 0x40000 if COREBOOT_ROMSIZE_KB_256 - default 0x80000 if COREBOOT_ROMSIZE_KB_512 - default 0x100000 if COREBOOT_ROMSIZE_KB_1024 - default 0x200000 if COREBOOT_ROMSIZE_KB_2048 - default 0x400000 if COREBOOT_ROMSIZE_KB_4096 - default 0x500000 if COREBOOT_ROMSIZE_KB_5120 - default 0x600000 if COREBOOT_ROMSIZE_KB_6144 - default 0x800000 if COREBOOT_ROMSIZE_KB_8192 - default 0xa00000 if COREBOOT_ROMSIZE_KB_10240 - default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 + default 0x10000 if COREBOOT_ROMSIZE_KB_64 + default 0x20000 if COREBOOT_ROMSIZE_KB_128 + default 0x40000 if COREBOOT_ROMSIZE_KB_256 + default 0x80000 if COREBOOT_ROMSIZE_KB_512 + default 0x100000 if COREBOOT_ROMSIZE_KB_1024 + default 0x200000 if COREBOOT_ROMSIZE_KB_2048 + default 0x400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x500000 if COREBOOT_ROMSIZE_KB_5120 + default 0x600000 if COREBOOT_ROMSIZE_KB_6144 + default 0x800000 if COREBOOT_ROMSIZE_KB_8192 + default 0xa00000 if COREBOOT_ROMSIZE_KB_10240 + default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 default 0x2000000 if COREBOOT_ROMSIZE_KB_32768 default 0x4000000 if COREBOOT_ROMSIZE_KB_65536 -- To view, visit https://review.coreboot.org/c/coreboot/+/39180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0160e72a8961f1aa34982f6348825708e7be9c40 Gerrit-Change-Number: 39180 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: util/ifdtool: add --output flag
by Marcello Sylvester Bauer (Code Review) 03 Mar '20

03 Mar '20

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38828 ) Change subject: util/ifdtool: add --output flag ...................................................................... util/ifdtool: add --output flag Add a optional commandline flag to define the filename of the resulting output file. If this flag is not defined, if will behave like before by creating a new file with a ".new" suffix. With this additional flag it is not necessary to move the output file at build-time, and the stdout print "Writing new image to <filename>" makes more sense for the build context. Change-Id: I824e94e93749f55c3576e4ee2f7804d855fefed2 Signed-off-by: Marcello Sylvester Bauer <sylv(a)sylv.io> --- M util/ifdtool/ifdtool.c 1 file changed, 30 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/38828/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 2bf2f4d..3cc5e15 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -854,17 +854,11 @@ static void write_image(const char *filename, char *image, int size) { - char new_filename[FILENAME_MAX]; // allow long file names int new_fd; - - // - 5: leave room for ".new\0" - strncpy(new_filename, filename, FILENAME_MAX - 5); - strncat(new_filename, ".new", FILENAME_MAX - strlen(filename)); - - printf("Writing new image to %s\n", new_filename); + printf("Writing new image to %s\n", filename); // Now write out new image - new_fd = open(new_filename, + new_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC | O_BINARY, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); if (new_fd < 0) { @@ -1429,6 +1423,7 @@ " -x | --extract: extract intel fd modules\n" " -i | --inject <region>:<module> inject file <module> into region <region>\n" " -n | --newlayout <filename> update regions using a flashrom layout file\n" + " -O | --output <filename> output filename\n" " -s | --spifreq <17|20|30|33|48|50> set the SPI frequency\n" " -D | --density <512|1|2|4|8|16|32|64> set chip density (512 in KByte, others in MByte)\n" " -C | --chip <0|1|2> select spi chip on which to operate\n" @@ -1460,6 +1455,7 @@ int mode_altmedisable = 0, altmedisable = 0; char *region_type_string = NULL, *region_fname = NULL; const char *layout_fname = NULL; + char *new_filename = NULL; int region_type = -1, inputfreq = 0; unsigned int new_density = 0; enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ; @@ -1470,6 +1466,7 @@ {"extract", 0, NULL, 'x'}, {"inject", 1, NULL, 'i'}, {"newlayout", 1, NULL, 'n'}, + {"output", 1, NULL, 'O'}, {"spifreq", 1, NULL, 's'}, {"density", 1, NULL, 'D'}, {"chip", 1, NULL, 'C'}, @@ -1484,7 +1481,7 @@ {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "df:D:C:M:xi:n:s:p:eluvth?", + while ((opt = getopt_long(argc, argv, "df:D:C:M:xi:n:O:s:p:eluvth?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -1543,6 +1540,14 @@ exit(EXIT_FAILURE); } break; + case 'O': + new_filename = strdup(optarg); + if (!new_filename) { + fprintf(stderr, "No output filename specified\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + break; case 'D': mode_density = 1; new_density = strtoul(optarg, NULL, 0); @@ -1731,6 +1736,14 @@ close(bios_fd); + // generate new filename + if (new_filename == NULL) { + new_filename = (char *) malloc((strlen(filename)) * sizeof(char)); + // - 5: leave room for ".new\0" + strcpy(new_filename, filename); + strcat(new_filename, ".new"); + } + check_ifd_version(image, size); if (mode_dump) @@ -1746,32 +1759,32 @@ validate_layout(image, size); if (mode_inject) - inject_region(filename, image, size, region_type, + inject_region(new_filename, image, size, region_type, region_fname); if (mode_newlayout) - new_layout(filename, image, size, layout_fname); + new_layout(new_filename, image, size, layout_fname); if (mode_spifreq) - set_spi_frequency(filename, image, size, spifreq); + set_spi_frequency(new_filename, image, size, spifreq); if (mode_density) - set_chipdensity(filename, image, size, new_density); + set_chipdensity(new_filename, image, size, new_density); if (mode_em100) - set_em100_mode(filename, image, size); + set_em100_mode(new_filename, image, size); if (mode_locked) - lock_descriptor(filename, image, size); + lock_descriptor(new_filename, image, size); if (mode_unlocked) - unlock_descriptor(filename, image, size); + unlock_descriptor(new_filename, image, size); if (mode_altmedisable) { fpsba_t *fpsba = find_fpsba(image, size); fmsba_t *fmsba = find_fmsba(image, size); fpsba_set_altmedisable(fpsba, fmsba, altmedisable); - write_image(filename, image, size); + write_image(new_filename, image, size); } free(image); -- To view, visit https://review.coreboot.org/c/coreboot/+/38828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I824e94e93749f55c3576e4ee2f7804d855fefed2 Gerrit-Change-Number: 38828 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylv(a)sylv.io> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: soc/broadwell: hook up smmstore
by Matt DeVillier (Code Review) 03 Mar '20

03 Mar '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39192 ) Change subject: soc/broadwell: hook up smmstore ...................................................................... soc/broadwell: hook up smmstore Adapted from implementation in sb/intel/common. Test: build/boot variants of google/{jecht, auron} with Tianocore and SMMSTORE enabled Change-Id: I4d2aaa80dad229a6c7b947d0edf8fb1174050ad0 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/broadwell/smihandler.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/39192/1 diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 5b04f79..2c38887 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -35,6 +35,7 @@ #include <soc/rcba.h> #include <soc/xhci.h> #include <drivers/intel/gma/i915_reg.h> +#include <smmstore.h> static u8 smm_initialized = 0; @@ -311,6 +312,26 @@ *ret = gsmi_exec(sub_command, param); } +static void southbridge_smi_store(void) +{ + u8 sub_command, ret; + em64t101_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(APM_CNT_SMMSTORE); + uint32_t reg_ebx; + + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* drivers/smmstore/smi.c */ + ret = smmstore_exec(sub_command, (void *)reg_ebx); + io_smi->rax = ret; +} + static void southbridge_smi_apmc(void) { u8 reg8; @@ -352,6 +373,10 @@ if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); break; + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + southbridge_smi_store(); + break; } mainboard_smi_apmc(reg8); -- To view, visit https://review.coreboot.org/c/coreboot/+/39192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d2aaa80dad229a6c7b947d0edf8fb1174050ad0 Gerrit-Change-Number: 39192 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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