Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31384
Change subject: README: Spell Web site with one space
......................................................................
README: Spell Web site with one space
Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M payloads/libpayload/README
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31384/1
diff --git a/payloads/libpayload/README b/payloads/libpayload/README
index fdf9b18..7348934 100644
--- a/payloads/libpayload/README
+++ b/payloads/libpayload/README
@@ -49,10 +49,10 @@
Please see the sample/ directory for details.
-Website and Mailing List
+Web site and Mailing List
------------------------
-The main website is https://www.coreboot.org/Libpayload.
+The main web site is https://www.coreboot.org/Libpayload.
For additional information, patches, and discussions, please join the
coreboot mailing list at https://www.coreboot.org/Mailinglist, where most
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Gerrit-Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6
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Mete Balci has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31821
Change subject: util/chromeos: Add unzip as a dependency
......................................................................
util/chromeos: Add unzip as a dependency
unzip might not be installed by default, so it is added as a
dependency in crosfirmware script.
Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc
Signed-off-by: Mete Balci <metebalci(a)gmail.com>
---
M util/chromeos/crosfirmware.sh
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31821/1
diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh
index 9d2ca84..0564106 100755
--- a/util/chromeos/crosfirmware.sh
+++ b/util/chromeos/crosfirmware.sh
@@ -37,6 +37,7 @@
exit_if_uninstalled "debugfs" "e2fsprogs"
exit_if_uninstalled "parted" "parted"
exit_if_uninstalled "curl" "curl"
+ exit_if_uninstalled "unzip" "unzip"
}
get_inventory()
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Patrick Georgi has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29045 )
Change subject: This patch fixes Klockwork issues due to the possibility of a NULL pointer being dereferenced
......................................................................
Abandoned
CB:30098 is a super set of this change
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9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39119 )
Change subject: mb/asrock/h110m: Explain why some SATA ports are empty
......................................................................
Patch Set 11:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1073
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1072
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1071
Please note: This test is under development and might not be accurate at all!
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Ravi kumar has uploaded a new patch set (#41) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/35499 )
Change subject: sc7180: Add QUPv3 FW load & config
......................................................................
sc7180: Add QUPv3 FW load & config
UART driver requires firmware loading
Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/25372/78https://review.coreboot.org/c/coreboot/+/27483/58
Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31
Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org>
---
M src/soc/qualcomm/sc7180/Makefile.inc
M src/soc/qualcomm/sc7180/bootblock.c
M src/soc/qualcomm/sc7180/include/soc/addressmap.h
A src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h
A src/soc/qualcomm/sc7180/include/soc/qupv3_config.h
A src/soc/qualcomm/sc7180/qcom_qup_se.c
A src/soc/qualcomm/sc7180/qupv3_config.c
7 files changed, 1,035 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35499/41
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9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38813 )
Change subject: soc/intel/gpio_defs: add a new macro for pad config
......................................................................
Patch Set 16:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1070
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1069
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1068
Please note: This test is under development and might not be accurate at all!
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39119 )
Change subject: mb/asrock/h110m: Explain why some SATA ports are empty
......................................................................
mb/asrock/h110m: Explain why some SATA ports are empty
Change-Id: Ib0a24fab22ee082367b82b3e8ee7383f1f02a4ad
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39119
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/mainboard/asrock/h110m/devicetree.cb
1 file changed, 5 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index fa94dd9..d42d91e 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -180,6 +180,11 @@
# SATA
register "EnableSata" = "1"
register "SataSalpSupport" = "1"
+ # SATA4 and SATA5 are located in the lower right corner of the board,
+ # but they are not populated. This is because the same PCB is used to
+ # make boards with better PCHs, which can have up to six SATA ports.
+ # However, the H110 PCH only has four SATA ports, which explains why
+ # two connectors are missing.
register "SataPortsEnable" = "{ \
[0] = 1, \
[1] = 1, \
@@ -190,8 +195,6 @@
[6] = 0, \
[7] = 0, \
}"
- # SATA4 and SATA5 are located in the lower right corner
- # of the board, but there is no connector for this
# PCH UART, SPI, I2C
register "SerialIoDevMode" = "{ \
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