Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Justin TerAvest, Rizwan Qureshi, Subrata Banik, Balaji Manigandan, Sooraj Govindan, Aamir Bohra, Patrick Rudolph, Martin Roth, Tim Wawrzynczak, Meera Ravindranath, Ronak Kanabar, Usha P, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39111
to look at the new patch set (#19).
Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support
......................................................................
soc/intel/tigerlake: Add Jasper lake GPIO support
Add gpio definition for Jasper Lake gpio controller.
Also created a separate file for JSL and TGL gpio keeping common asl file.
gpio_soc_defs.h must pass correct information/macro values to asl file
for code to work.
GPIO controller includes 4 gpio community and 10 groups. Patch adds
definition for all gpio within community and groups
Updated IRQ mapping for all gpios
TEST=Check if jslrvp and tglrvp code is compiling
Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
Signed-off-by: Usha P <usha.p(a)intel.com>
---
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/acpi/gpio.asl
A src/soc/intel/tigerlake/acpi/gpio_op.asl
M src/soc/intel/tigerlake/chip.h
A src/soc/intel/tigerlake/gpio_jsl.c
R src/soc/intel/tigerlake/gpio_tgl.c
M src/soc/intel/tigerlake/include/soc/gpio.h
M src/soc/intel/tigerlake/include/soc/gpio_defs.h
A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h
A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h
M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h
A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h
M src/soc/intel/tigerlake/include/soc/pmc.h
15 files changed, 1,784 insertions(+), 769 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39111/19
--
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Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2
Gerrit-Change-Number: 39111
Gerrit-PatchSet: 19
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
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Gerrit-MessageType: newpatchset
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39168 )
Change subject: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake
......................................................................
Patch Set 2: Code-Review+2
--
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Gerrit-Change-Id: I063f921832a4e4a45eb6978b6dbb37b1ac7dde7f
Gerrit-Change-Number: 39168
Gerrit-PatchSet: 2
Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com>
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Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>
Gerrit-Comment-Date: Tue, 03 Mar 2020 09:00:39 +0000
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Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Justin TerAvest, Rizwan Qureshi, Subrata Banik, Balaji Manigandan, Sooraj Govindan, Aamir Bohra, Patrick Rudolph, Martin Roth, Tim Wawrzynczak, Meera Ravindranath, Ronak Kanabar, Usha P, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39111
to look at the new patch set (#18).
Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support
......................................................................
soc/intel/tigerlake: Add Jasper lake GPIO support
Add gpio definition for Jasper Lake gpio controller.
Also created a separate file for JSL and TGL gpio keeping common asl file.
gpio_soc_defs.h must pass correct information/macro values to asl file
for code to work.
GPIO controller includes 4 gpio community and 10 groups. Patch adds
definition for all gpio within community and groups
Updated IRQ mapping for all gpios
TEST=Check if jslrvp and tglrvp code is compiling
Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
Signed-off-by: Usha P <usha.p(a)intel.com>
---
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/acpi/gpio.asl
A src/soc/intel/tigerlake/acpi/gpio_op.asl
M src/soc/intel/tigerlake/chip.h
A src/soc/intel/tigerlake/gpio_jsl.c
R src/soc/intel/tigerlake/gpio_tgl.c
M src/soc/intel/tigerlake/include/soc/gpio.h
M src/soc/intel/tigerlake/include/soc/gpio_defs.h
A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h
A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h
M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h
A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h
M src/soc/intel/tigerlake/include/soc/pmc.h
15 files changed, 1,784 insertions(+), 769 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39111/18
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2
Gerrit-Change-Number: 39111
Gerrit-PatchSet: 18
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Usha P <usha.p(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39135 )
Change subject: src/soc/tigerlake: Add memory configuration support for Jasper Lake
......................................................................
src/soc/tigerlake: Add memory configuration support for Jasper Lake
BUG=none
BRANCH=none
TEST=Build and verify boot of WaddleDoo.
Change-Id: I8de502d3f05d52b9dae34e3b013c6d5b1896fa85
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
---
M src/soc/intel/tigerlake/Makefile.inc
A src/soc/intel/tigerlake/include/soc/jsl_memcfg_init.h
A src/soc/intel/tigerlake/jsl_memcfg_init.c
3 files changed, 305 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/39135/1
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc
index 56119f5..c85f9dc 100644
--- a/src/soc/intel/tigerlake/Makefile.inc
+++ b/src/soc/intel/tigerlake/Makefile.inc
@@ -26,6 +26,7 @@
romstage-y += espi.c
romstage-y += gpio.c
romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += meminit_tgl.c
+romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += jsl_memcfg_init.c
romstage-y += reset.c
ramstage-y += acpi.c
diff --git a/src/soc/intel/tigerlake/include/soc/jsl_memcfg_init.h b/src/soc/intel/tigerlake/include/soc/jsl_memcfg_init.h
new file mode 100644
index 0000000..e04ef85
--- /dev/null
+++ b/src/soc/intel/tigerlake/include/soc/jsl_memcfg_init.h
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright Intel Corporation 2020.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_JASPERLAKE_MEMCFG_INIT_H_
+#define _SOC_JASPERLAKE_MEMCFG_INIT_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <fsp/soc_binding.h>
+
+/* Number of dq bits controlled per dqs */
+#define DQ_BITS_PER_DQS 8
+
+/* Number of memory DIMM slots available on Cannonlake board */
+#define NUM_DIMM_SLOT 4
+
+/*
+ * Number of memory packages, where a "package" represents a 64-bit solution.
+ */
+#define DDR_NUM_PACKAGES 2
+
+/* 64-bit Channel identification */
+enum {
+ DDR_CH0,
+ DDR_CH1,
+ DDR_NUM_CHANNELS
+};
+
+struct spd_by_pointer {
+ size_t spd_data_len;
+ uintptr_t spd_data_ptr;
+};
+
+enum mem_info_read_type {
+ NOT_EXISTING, /* No memory in this slot */
+ READ_SMBUS, /* Read on-module spd by SMBUS. */
+ READ_SPD_CBFS, /* Find spd file in CBFS. */
+ READ_SPD_MEMPTR /* Find spd data from pointer. */
+};
+
+struct spd_info {
+ enum mem_info_read_type read_type;
+ union spd_data_by {
+ /* To read on-module spd when read_type is READ_SMBUS. */
+ uint8_t spd_smbus_address;
+
+ /* To identify spd file when read_type is READ_SPD_CBFS. */
+ int spd_index;
+
+ /* To find spd data when read_type is READ_SPD_MEMPTR. */
+ struct spd_by_pointer spd_data_ptr_info;
+ } spd_spec;
+};
+
+/* Board-specific memory dq mapping information */
+struct jsl_mb_cfg {
+ /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
+ struct spd_info spd[NUM_DIMM_SLOT];
+
+ /*
+ * For each channel, there are 6 sets of DQ byte mappings,
+ * where each set has a package 0 and a package 1 value (package 0
+ * represents the first 64-bit lpddr4 chip combination, and package 1
+ * represents the second 64-bit lpddr4 chip combination).
+ * The first three sets are for CLK, CMD, and CTL.
+ * The fsp package actually expects 6 sets, even though the last 3 sets
+ * are not used in CNL.
+ * We let the meminit_lpddr4() routine take care of clearing the
+ * unused fields for the caller.
+ * Note that dq_map is only used by LPDDR; it does not need to be
+ * initialized for designs using DDR4.
+ */
+ uint8_t dq_map[DDR_NUM_CHANNELS][6][DDR_NUM_PACKAGES];
+
+ /*
+ * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a
+ * mapping of a dq bit on the CPU to the bit it's connected to on
+ * the memory part. The array index represents the dqs bit number
+ * on the memory part, and the values in the array represent which
+ * pin on the CPU that DRAM pin connects to.
+ * dqs_map is only used by LPDDR; same comments apply as for dq_map
+ * above.
+ */
+ uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS];
+
+ /*
+ * Rcomp resistor values. These values represent the resistance in
+ * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+ * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+ */
+ uint16_t rcomp_resistor[3];
+
+ /*
+ * Rcomp target values. These will typically be the following
+ * values for Cannon Lake : { 80, 40, 40, 40, 30 }
+ */
+ uint16_t rcomp_targets[5];
+
+ /*
+ * Indicates whether memory is interleaved.
+ * Set to 1 for an interleaved design,
+ * set to 0 for non-interleaved design.
+ */
+ uint8_t dq_pins_interleaved;
+
+ /*
+ * VREF_CA configuration.
+ * Set to 0 VREF_CA goes to both CH_A and CH_B,
+ * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
+ * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
+ */
+ uint8_t vref_ca_config;
+
+ /* Early Command Training Enabled */
+ uint8_t ect;
+
+ /* Board type */
+ uint8_t UserBd;
+};
+
+/*
+ * Initialize default memory configurations for CannonLake.
+ */
+void jasperlake_memcfg_init(FSP_M_CONFIG *mem_cfg,
+ const struct jsl_mb_cfg *jsl_cfg);
+
+#endif /* _SOC_JASPERLAKE_MEMCFG_INIT_H_ */
diff --git a/src/soc/intel/tigerlake/jsl_memcfg_init.c b/src/soc/intel/tigerlake/jsl_memcfg_init.c
new file mode 100644
index 0000000..c8e2c03
--- /dev/null
+++ b/src/soc/intel/tigerlake/jsl_memcfg_init.c
@@ -0,0 +1,165 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <assert.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/jsl_memcfg_init.h>
+#include <spd_bin.h>
+#include <string.h>
+
+static void meminit_memcfg(FSP_M_CONFIG *mem_cfg,
+ const struct jsl_mb_cfg *board_cfg)
+{
+ /*
+ * DqByteMapChx expects 12 bytes of data, but the last 6 bytes
+ * are unused, so client passes in the relevant values and
+ * we null out the rest of the data.
+ */
+ memset(&mem_cfg->DqByteMapCh0, 0, sizeof(mem_cfg->DqByteMapCh0));
+ memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[DDR_CH0],
+ sizeof(board_cfg->dq_map[DDR_CH0]));
+
+ memset(&mem_cfg->DqByteMapCh1, 0, sizeof(mem_cfg->DqByteMapCh1));
+ memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[DDR_CH1],
+ sizeof(board_cfg->dq_map[DDR_CH1]));
+
+ memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0],
+ sizeof(board_cfg->dqs_map[DDR_CH0]));
+ memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1],
+ sizeof(board_cfg->dqs_map[DDR_CH1]));
+
+ memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor,
+ sizeof(mem_cfg->RcompResistor));
+
+ /* Early cannonlake requires rcomp targets to be 0 */
+ memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets,
+ sizeof(mem_cfg->RcompTarget));
+
+ mem_cfg->UserBd = board_cfg->UserBd;
+
+}
+
+/*
+ * Initialize default memory settings using spd data contained in a buffer.
+ */
+static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, uint8_t mem_slot,
+ size_t spd_data_len, uintptr_t spd_data_ptr)
+{
+ static size_t last_set_spd_data_len = 0;
+
+ assert(spd_data_ptr != 0 && spd_data_len != 0);
+
+ if (last_set_spd_data_len != 0 &&
+ last_set_spd_data_len != spd_data_len)
+ die("spd data length disparity among slots");
+
+ mem_cfg->MemorySpdDataLen = spd_data_len;
+ last_set_spd_data_len = spd_data_len;
+
+ switch (mem_slot) {
+ case 0:
+ mem_cfg->MemorySpdPtr00 = spd_data_ptr;
+ break;
+ case 1:
+ mem_cfg->MemorySpdPtr01 = spd_data_ptr;
+ break;
+ case 2:
+ mem_cfg->MemorySpdPtr10 = spd_data_ptr;
+ break;
+ case 3:
+ mem_cfg->MemorySpdPtr11 = spd_data_ptr;
+ break;
+ default:
+ die("nonexistent memory slot");
+ }
+ printk(BIOS_INFO, "memory slot: %d configuration done.\n", mem_slot);
+}
+
+/*
+ * Initialize default memory settings using the spd file specified by
+ * spd_index. The spd_index is an index into the SPD_SOURCES array defined
+ * in spd/Makefile.inc.
+ */
+static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg,
+ int spd_index, uint8_t mem_slot)
+{
+ static size_t spd_data_len;
+ static uintptr_t spd_data_ptr;
+ static int last_spd_index;
+
+ assert(mem_slot < NUM_DIMM_SLOT);
+
+ if ((spd_data_ptr == 0) || (last_spd_index != spd_index)) {
+ struct region_device spd_rdev;
+
+ printk(BIOS_DEBUG, "SPD INDEX = %d\n", spd_index);
+
+ if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
+ die("spd.bin not found or incorrect index\n");
+
+ spd_data_len = region_device_sz(&spd_rdev);
+
+ /* Memory leak is ok since we have memory mapped boot media */
+ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
+
+ spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev);
+ last_spd_index = spd_index;
+ print_spd_info((unsigned char *)spd_data_ptr);
+ }
+
+ meminit_spd_data(mem_cfg, mem_slot, spd_data_len, spd_data_ptr);
+}
+
+/* Initialize onboard memory configurations for CannonLake */
+void jasperlake_memcfg_init(FSP_M_CONFIG *mem_cfg,
+ const struct jsl_mb_cfg *jsl_cfg)
+{
+ const struct spd_info *spdi;
+
+ /* Early Command Training Enabled */
+ mem_cfg->ECT = jsl_cfg->ect;
+ mem_cfg->DqPinsInterleaved = jsl_cfg->dq_pins_interleaved;
+ mem_cfg->CaVrefConfig = jsl_cfg->vref_ca_config;
+
+ for (int i = 0; i < NUM_DIMM_SLOT; i++) {
+ spdi = &(jsl_cfg->spd[i]);
+ switch (spdi->read_type) {
+ case NOT_EXISTING:
+ break;
+
+ case READ_SMBUS:
+ mem_cfg->SpdAddressTable[i] =
+ spdi->spd_spec.spd_smbus_address;
+ break;
+
+ case READ_SPD_CBFS:
+ mem_cfg->SpdAddressTable[i] = 0;
+ meminit_cbfs_spd_index(mem_cfg,
+ spdi->spd_spec.spd_index, i);
+ break;
+
+ case READ_SPD_MEMPTR:
+ meminit_spd_data(mem_cfg, i,
+ spdi->spd_spec.spd_data_ptr_info.spd_data_len,
+ spdi->spd_spec.spd_data_ptr_info.spd_data_ptr);
+ break;
+
+ default:
+ die("no valid way to read mem info");
+ }
+
+ meminit_memcfg(mem_cfg, jsl_cfg);
+ }
+}
--
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Gerrit-Branch: master
Gerrit-Change-Id: I8de502d3f05d52b9dae34e3b013c6d5b1896fa85
Gerrit-Change-Number: 39135
Gerrit-PatchSet: 1
Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com>
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Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39188 )
Change subject: payloads/ext/Makefile.inc: Fix SeaBIOS race condition
......................................................................
payloads/ext/Makefile.inc: Fix SeaBIOS race condition
For a very long time, SeaBIOS sometimes failed to build when using
multiple threads. This known problem has been haunting everyone for a
very long time. Until now.
Unlike most other payloads, building SeaBIOS results in two files: the
SeaBIOS payload itself and SeaVGABIOS. Each file has its own target, and
there's a third target called "seabios", which has the same recipe as
the SeaBIOS file, which calls `payloads/external/SeaBIOS/Makefile` with
a bunch of arguments. In addition, SeaVGABIOS depends on "seabios".
When executing serially, if the file of either SeaBIOS or SeaVGABIOS is
needed, the SeaBIOS Makefile will be run. This will generate both files,
so it is not necessary to run the Makefile more than once.
However, when using multiple threads, it can happen that one thread
wants to make the SeaBIOS file, while another one wants to make the
SeaVGABIOS file, which depends on "seabios". This implies that both
threads will execute the SeaBIOS Makefile at about the same time, only
to collide when performing git operations. Since git uses a lock file
when updating the index, one of the threads will fail to acquire the
lock with an error, which will ultimately cause the build to fail.
Whenever this happened, manually aborting with Ctrl-C made the build
process fail again because of the same error. The only way to get past
this problem, other than using one thread, was to let the unfinished
jobs complete. The thread that acquired the lock on the SeaBIOS git
repository would finish building SeaBIOS, so that target would not need
to be remade. When restarting the build, only the target that failed is
rebuilt, so it does not collide with any other thread.
To address this issue, make the SeaVGABIOS file target depend directly
on the SeaBIOS file instead, and remove the duplicate "seabios" target.
Change-Id: I251190d3bb27052ff474f3cd1a45022dab6fac31
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M payloads/external/Makefile.inc
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/39188/1
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
index b8af8c9..0a96aff 100644
--- a/payloads/external/Makefile.inc
+++ b/payloads/external/Makefile.inc
@@ -78,7 +78,7 @@
# SeaBIOS
SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1)
-payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG)
+payloads/external/SeaBIOS/seabios/out/bios.bin.elf: $(DOTCONFIG)
$(MAKE) -C payloads/external/SeaBIOS \
HOSTCC="$(HOSTCC)" \
CC=$(word $(SEABIOS_CC_OFFSET),$(CC_x86_32)) \
@@ -104,7 +104,7 @@
CONFIG_ENABLE_HSUART=$(CONFIG_ENABLE_HSUART) \
CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS)
-payloads/external/SeaBIOS/seabios/out/vgabios.bin: seabios
+payloads/external/SeaBIOS/seabios/out/vgabios.bin: payloads/external/SeaBIOS/seabios/out/bios.bin.elf
payloads/external/SeaBIOS/seabios/.config: payloads/external/SeaBIOS/seabios/out/bios.bin.elf
payloads/external/SeaBIOS/seabios/out/autoversion.h: payloads/external/SeaBIOS/seabios/out/bios.bin.elf
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I251190d3bb27052ff474f3cd1a45022dab6fac31
Gerrit-Change-Number: 39188
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange