coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Maulik V Vaghela (Code Review) 03 Mar '20

03 Mar '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Justin TerAvest, Rizwan Qureshi, Subrata Banik, Balaji Manigandan, Sooraj Govindan, Aamir Bohra, Patrick Rudolph, Martin Roth, Tim Wawrzynczak, Meera Ravindranath, Ronak Kanabar, Usha P, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39111 to look at the new patch set (#15). Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support ...................................................................... soc/intel/tigerlake: Add Jasper lake GPIO support Add gpio definition for Jasper Lake gpio controller. Also created a separate file for JSL and TGL gpio keeping common asl file. gpio_soc_defs.h must pass correct information/macro values to asl file for code to work. GPIO controller includes 4 gpio community and 10 groups. Patch adds definition for all gpio within community and groups Updated IRQ mapping for all gpios TEST=Check if jslrvp and tglrvp code is compiling Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/acpi/gpio.asl A src/soc/intel/tigerlake/acpi/gpio_op.asl M src/soc/intel/tigerlake/chip.h A src/soc/intel/tigerlake/gpio_jsl.c R src/soc/intel/tigerlake/gpio_tgl.c M src/soc/intel/tigerlake/include/soc/gpio.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h M src/soc/intel/tigerlake/include/soc/pmc.h 13 files changed, 1,404 insertions(+), 403 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39111/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/39111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Gerrit-Change-Number: 39111 Gerrit-PatchSet: 15 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Maulik V Vaghela (Code Review) 03 Mar '20

03 Mar '20

1 0

Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Maulik V Vaghela (Code Review) 03 Mar '20

03 Mar '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Justin TerAvest, Rizwan Qureshi, Subrata Banik, Balaji Manigandan, Sooraj Govindan, Aamir Bohra, Patrick Rudolph, Martin Roth, Tim Wawrzynczak, Meera Ravindranath, Ronak Kanabar, Usha P, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39111 to look at the new patch set (#14). Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support ...................................................................... soc/intel/tigerlake: Add Jasper lake GPIO support Add gpio definition for Jasper Lake gpio controller. Also created a separate file for JSL and TGL gpio keeping common asl file. gpio_soc_defs.h must pass correct information/macro values to asl file for code to work. GPIO controller includes 4 gpio community and 10 groups. Patch adds definition for all gpio within community and groups Updated IRQ mapping for all gpios TEST=Check if jslrvp and tglrvp code is compiling Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Usha P <usha.p(a)intel.com> --- A src/soc/intel/common/acpi/gpio_op.asl M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/chip.h A src/soc/intel/tigerlake/gpio_jsl.c R src/soc/intel/tigerlake/gpio_tgl.c M src/soc/intel/tigerlake/include/soc/gpio.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h M src/soc/intel/tigerlake/include/soc/pmc.h 13 files changed, 1,404 insertions(+), 403 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39111/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/39111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Gerrit-Change-Number: 39111 Gerrit-PatchSet: 14 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Subrata Banik (Code Review) 03 Mar '20

03 Mar '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39111 ) Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/c/coreboot/+/39111/13/src/soc/intel/common/acpi… File src/soc/intel/common/acpi/gpio_op.asl: https://review.coreboot.org/c/coreboot/+/39111/13/src/soc/intel/common/acpi… PS13, Line 1: /* this file might be good candidate of separate CL if you wish to do so? -- To view, visit https://review.coreboot.org/c/coreboot/+/39111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Gerrit-Change-Number: 39111 Gerrit-PatchSet: 13 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Mar 2020 04:37:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Subrata Banik (Code Review) 03 Mar '20

03 Mar '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39111 ) Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support ...................................................................... Patch Set 13: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Gerrit-Change-Number: 39111 Gerrit-PatchSet: 13 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Mar 2020 04:36:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Maulik V Vaghela (Code Review) 03 Mar '20

03 Mar '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39111 ) Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support ...................................................................... Patch Set 12: (5 comments) https://review.coreboot.org/c/coreboot/+/39111/12/src/soc/intel/common/acpi… File src/soc/intel/common/acpi/gpio_op.asl: https://review.coreboot.org/c/coreboot/+/39111/12/src/soc/intel/common/acpi… PS12, Line 4: Copyright (C) 2020 Intel Corporation. > Please use "Copyright 2020 The coreboot project Authors. […] Done I am updating copyright line, for SPDX license header can we push separate patch for all files? https://review.coreboot.org/c/coreboot/+/39111/12/src/soc/intel/common/acpi… PS12, Line 76: /* : * Set Pad mode : * Arg0 - GPIO Number : * Arg1 - Pad mode : * 0 = GPIO control pad : * 1 = Native Function 1 : * 2 = Native Function 2 : * 3 = Native Function 3 : */ : Method (GPMO, 2, Serialized) : { : OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) : Field (PREG, AnyAcc, NoLock, Preserve) : { : VAL0, 32 : } : Store (VAL0, Local0) : And (Not (GPIOPADMODE_MASK), Local0, Local0) : And (ShiftLeft (Arg1, GPIOPADMODE_SHIFT, Arg1), GPIOPADMODE_MASK, Arg1) : Or (Local0, Arg1, VAL0) : } : : /* : * Enable/Disable Tx buffer : * Arg0 - GPIO Number : * Arg1 - TxBuffer state : * 0 = Disable Tx Buffer : * 1 = Enable Tx Buffer : */ : Method (GTXE, 2, Serialized) : { : OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) : Field (PREG, AnyAcc, NoLock, Preserve) : { : VAL0, 32 : } : : If (LEqual (Arg1, 1)) { : And (Not (GPIOTXBUFDIS_MASK), VAL0, VAL0) : } ElseIf (LEqual (Arg1, 0)){ : Or (GPIOTXBUFDIS_MASK, VAL0, VAL0) : } : } : : /* : * Enable/Disable Rx buffer : * Arg0 - GPIO Number : * Arg1 - RxBuffer state : * 0 = Disable Rx Buffer : * 1 = Enable Rx Buffer : */ : Method (GRXE, 2, Serialized) : { : OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) : Field (PREG, AnyAcc, NoLock, Preserve) : { : VAL0, 32 : } : : If (LEqual (Arg1, 1)) { : And (Not (GPIORXBUFDIS_MASK), VAL0, VAL0) : } ElseIf (LEqual (Arg1, 0)){ : Or (GPIORXBUFDIS_MASK, VAL0, VAL0) : } : } > Looks like these got added when moving code into gpio_op.asl. […] Yes Furquan, we're planning to use it for camera related ASL files. https://review.coreboot.org/c/coreboot/+/39111/12/src/soc/intel/tigerlake/a… File src/soc/intel/tigerlake/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/39111/12/src/soc/intel/tigerlake/a… PS12, Line 122: rg0 >= GPP_B0 && Arg0 <= GPP_A24) > Actually all the ASL files in this CL seems to be written using legacy ASL. […] Since this file was copied from earlier project like icelake, it was in legacy asl format. I have updated it to use ASL 2.0. Ack and Done https://review.coreboot.org/c/coreboot/+/39111/12/src/soc/intel/tigerlake/a… PS12, Line 21: Device (GPIO) > Why was this device changed? This is going to break compatibility with Linux kernel driver for handl […] Done https://review.coreboot.org/c/coreboot/+/39111/12/src/soc/intel/tigerlake/a… PS12, Line 90: /* GPIO Community 4 */ > Here GPIO community 2 is removed for TGL. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Gerrit-Change-Number: 39111 Gerrit-PatchSet: 12 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Mar 2020 04:34:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Maulik V Vaghela (Code Review) 03 Mar '20

03 Mar '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Justin TerAvest, Rizwan Qureshi, Subrata Banik, Balaji Manigandan, Sooraj Govindan, Aamir Bohra, Patrick Rudolph, Martin Roth, Tim Wawrzynczak, Meera Ravindranath, Ronak Kanabar, Usha P, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39111 to look at the new patch set (#13). Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support ...................................................................... soc/intel/tigerlake: Add Jasper lake GPIO support Add gpio definition for Jasper Lake gpio controller. Also created a separate file for JSL and TGL gpio keeping common asl file. gpio_soc_defs.h must pass correct information/macro values to asl file for code to work. GPIO controller includes 4 gpio community and 10 groups. Patch adds definition for all gpio within community and groups Updated IRQ mapping for all gpios TEST=Check if jslrvp and tglrvp code is compiling Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Usha P <usha.p(a)intel.com> --- A src/soc/intel/common/acpi/gpio_op.asl M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/chip.h A src/soc/intel/tigerlake/gpio_jsl.c R src/soc/intel/tigerlake/gpio_tgl.c M src/soc/intel/tigerlake/include/soc/gpio.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h M src/soc/intel/tigerlake/include/soc/pmc.h 13 files changed, 1,404 insertions(+), 403 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39111/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/39111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Gerrit-Change-Number: 39111 Gerrit-PatchSet: 13 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 03 Mar '20

03 Mar '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Sridhar Siricilla, Rizwan Qureshi, Subrata Banik, Balaji Manigandan, Aamir Bohra, Patrick Rudolph, V Sowmya, Nico Huber, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#69). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs In CSE Firmware Custom SKU, CSE region is logically divided into 2 boot partitions. These boot partitions are represented by BP1, BP2. Using the CSE Firmware Custom SKU, CSE can boot from either BP1 or BP2. The CSE Firmware Custom SKU layout appears as below: ------------- -------------------- --------------------- |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 | DATA | ------------- -------------------- --------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows coreboot to set CSE to boot from required boot partition (either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - Provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. BUG=b:145809764 Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 466 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/69 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 69 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake
by caveh jalali (Code Review) 03 Mar '20

03 Mar '20

caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39168 ) Change subject: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/39168/1/src/vendorcode/intel/fsp/f… File src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h: PS1: could you please set the file permissions back to 644? -- To view, visit https://review.coreboot.org/c/coreboot/+/39168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I063f921832a4e4a45eb6978b6dbb37b1ac7dde7f Gerrit-Change-Number: 39168 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Tue, 03 Mar 2020 03:59:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/tigerlake: Correct FSP log interface
by Wonkyu Kim (Code Review) 02 Mar '20

02 Mar '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39167 ) Change subject: soc/tigerlake: Correct FSP log interface ...................................................................... soc/tigerlake: Correct FSP log interface BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 --- M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/39167/1 diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index ed6aa5a..043a257 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -61,7 +61,8 @@ /* UART Debug Log */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; + DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : \ + DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB; m_cfg->PcdIsaSerialUartBase = 0x0; m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/39167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 Gerrit-Change-Number: 39167 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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