coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

1 participants
3325 discussions

Change in coreboot[master]: mb/asrock/h110m: add libgfxinit support
by Maxim Polyakov (Code Review) 02 Mar '20

02 Mar '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39104 ) Change subject: mb/asrock/h110m: add libgfxinit support ...................................................................... Patch Set 11: (1 comment) Thanks for the review https://review.coreboot.org/c/coreboot/+/39104/10//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39104/10//COMMIT_MSG@7 PS10, Line 7: mb/asrock/h110m: add libgfxinit support > You should remove the "Analog" port in gma-mainboard.ads, as it does not exist. The board contains a VGA connector, but it doesn't work with libgfx. Should I remove this anyway? -- To view, visit https://review.coreboot.org/c/coreboot/+/39104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d87413f87d00986111ecb7b046423ff5eac1bf1 Gerrit-Change-Number: 39104 Gerrit-PatchSet: 11 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 02 Mar 2020 17:39:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/asrock/h110m: Explain why some SATA ports are empty
by Maxim Polyakov (Code Review) 02 Mar '20

02 Mar '20

Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39119 to look at the new patch set (#10). Change subject: mb/asrock/h110m: Explain why some SATA ports are empty ...................................................................... mb/asrock/h110m: Explain why some SATA ports are empty Change-Id: Ib0a24fab22ee082367b82b3e8ee7383f1f02a4ad Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/39119/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/39119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0a24fab22ee082367b82b3e8ee7383f1f02a4ad Gerrit-Change-Number: 39119 Gerrit-PatchSet: 10 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: md/kontron/mal10: Add COMe-mAL10 minimal support
by Maxim Polyakov (Code Review) 02 Mar '20

02 Mar '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39133 to look at the new patch set (#8). Change subject: md/kontron/mal10: Add COMe-mAL10 minimal support ...................................................................... md/kontron/mal10: Add COMe-mAL10 minimal support This patch adds minimal support for the Kontron COMe-mAL10 module with the Apollo Lake processor together with Kontron T10-TNI carrierboard. Working: - console (Kontron CPLD) - USB2/3 - Ethernet network - eMMC - SATA - PCIe ports - Video/DP (*) Not tested: - Video/LVDS TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) - SDIO - Documentation As the payload was used: - Tianocore (*)(**) - SeaBIOS (*) (*) Video works only in linux (**) Works only with Tianocore "UEFIPayload" payload edk2-stable201903-1569-g3e63a91 (**) Booting with the "CorebootPayload" crashes: https://pastebin.com/1h4Y5aZf Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A src/mainboard/kontron/mal10/Kconfig A src/mainboard/kontron/mal10/Kconfig.name A src/mainboard/kontron/mal10/Makefile.inc A src/mainboard/kontron/mal10/acpi/dptf.asl A src/mainboard/kontron/mal10/acpi_tables.c A src/mainboard/kontron/mal10/board_info.txt A src/mainboard/kontron/mal10/bootblock.c A src/mainboard/kontron/mal10/cmos.default A src/mainboard/kontron/mal10/cmos.layout A src/mainboard/kontron/mal10/data.vbt A src/mainboard/kontron/mal10/dsdt.asl A src/mainboard/kontron/mal10/gma-mainboard.ads A src/mainboard/kontron/mal10/gpio.h A src/mainboard/kontron/mal10/mainboard.c A src/mainboard/kontron/mal10/mal10.fmd A src/mainboard/kontron/mal10/ramstage.c A src/mainboard/kontron/mal10/romstage.c A src/mainboard/kontron/mal10/variants/baseboard/devicetree.cb A src/mainboard/kontron/mal10/variants/t10-tni/overridetree.cb 19 files changed, 1,210 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39133/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 8 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: util/amdfwtool: Clarify APOB NV requirements
by Marshall Dawson (Code Review) 02 Mar '20

02 Mar '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38690 ) Change subject: util/amdfwtool: Clarify APOB NV requirements ...................................................................... util/amdfwtool: Clarify APOB NV requirements Relocate the first size check. This was automatically continuing and not looking for the caller incorrectly passing a destination. New information indicates that the APOB_NV should always be present in the system. Augment the missing size check to inferring whether a missing size is valid, as in the case of older products, or truly missing when it's needed. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e --- M util/amdfwtool/amdfwtool.c 1 file changed, 25 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/38690/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index d5c63de..c41da58 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -808,6 +808,17 @@ return 0; } +static int find_bios_entry(amd_bios_type type) +{ + int i; + + for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) { + if (amd_bios_table[i].type == type) + return i; + } + return -1; +} + static void integrate_bios_firmwares(context *ctx, bios_directory_table *biosdir, bios_directory_table *biosdir2, @@ -817,6 +828,7 @@ ssize_t bytes; unsigned int i, count; int level; + int apob_idx; /* This function can create a primary table, a secondary table, or a * flattened table which contains all applicable types. These if-else @@ -843,9 +855,6 @@ fw_table[i].type != AMD_BIOS_L2_PTR && fw_table[i].type != AMD_BIOS_BIN)) continue; - /* APOB_NV needs a size, else no S3 and skip item */ - if (fw_table[i].type == AMD_BIOS_APOB_NV && !fw_table[i].size) - continue; /* BIOS Directory items may have additional requirements */ @@ -857,6 +866,19 @@ exit(1); } } + /* APOB_NV needs a size, else no choice but to skip the item */ + if (fw_table[i].type == AMD_BIOS_APOB_NV && !fw_table[i].size) { + /* Attempt to determine whether this is an error */ + apob_idx = find_bios_entry(AMD_BIOS_APOB); + if (apob_idx < 0 || !fw_table[apob_idx].dest) { + /* APOV NV not expected to be used */ + continue; + } else { + printf("Error: APOB NV must have a size\n"); + free(ctx->rom); + exit(1); + } + } /* APOB_DATA needs destination */ if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) { -- To view, visit https://review.coreboot.org/c/coreboot/+/38690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e Gerrit-Change-Number: 38690 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/amd/picasso: Add PCI ID for Dali xHCI
by Marshall Dawson (Code Review) 02 Mar '20

02 Mar '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38169 ) Change subject: soc/amd/picasso: Add PCI ID for Dali xHCI ...................................................................... soc/amd/picasso: Add PCI ID for Dali xHCI soc//picasso is intended to be forward-compatible with the Dali APU, a Family 17h Models 20h-2Fh product. Add the one new device ID it has. See PPR document #55772 (still NDA only) for more information. Change-Id: I7e9b90bb00ae6f4a121f10b1467d2ca398ac860c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/amd/picasso/usb.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/38169/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index bd5b3a5..52c6035 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -459,6 +459,7 @@ #define PCI_DEVICD_ID_AMD_PCO_ACP 0x15e2 #define PCI_DEVICE_ID_AMD_PCO_XHCI0 0x15e0 #define PCI_DEVICE_ID_AMD_PCO_XHCI1 0x15e1 +#define PCI_DEVICE_ID_AMD_DALI_XHCI 0x15e5 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index 80e960c..faea3c3 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -48,6 +48,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_PCO_XHCI0, PCI_DEVICE_ID_AMD_PCO_XHCI1, + PCI_DEVICE_ID_AMD_DALI_XHCI, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/38169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e9b90bb00ae6f4a121f10b1467d2ca398ac860c Gerrit-Change-Number: 38169 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

6 6

Change in ...coreboot[master]: x86/acpi_s3: Remove trailing dots from debug message
by Paul Menzel (Code Review) 02 Mar '20

02 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30806 Change subject: x86/acpi_s3: Remove trailing dots from debug message ...................................................................... x86/acpi_s3: Remove trailing dots from debug message The dot is not needed, as it is no sentence and followed by a line break. Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/arch/x86/acpi_s3.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30806/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ad9fe00..07c0332 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -34,10 +34,10 @@ { if (acpi_slp_type < 0) { if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume.\n"); + printk(BIOS_DEBUG, "S3 Resume\n"); acpi_slp_type = ACPI_S3; } else { - printk(BIOS_DEBUG, "Normal boot.\n"); + printk(BIOS_DEBUG, "Normal boot\n"); acpi_slp_type = ACPI_S0; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Gerrit-Change-Number: 30806 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: lint/lint-extended-007-checkpatch: Fix obsolete paths
by HAOUAS Elyes (Code Review) 02 Mar '20

02 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39171 ) Change subject: lint/lint-extended-007-checkpatch: Fix obsolete paths ...................................................................... lint/lint-extended-007-checkpatch: Fix obsolete paths Change-Id: I7a6ca083e79d285b8c596631f21ccdfe2777e20e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/lint/lint-extended-007-checkpatch 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/39171/1 diff --git a/util/lint/lint-extended-007-checkpatch b/util/lint/lint-extended-007-checkpatch index 4610b5e..c221d4a 100755 --- a/util/lint/lint-extended-007-checkpatch +++ b/util/lint/lint-extended-007-checkpatch @@ -21,9 +21,7 @@ src/drivers/dec src/drivers/gic src/drivers/ti \ src/ec/purism \ src/include/boot src/include/superio src/include/sys \ -src/mainboard/adlink src/mainboard/linutop \ -src/mainboard/purism src/mainboard/ti \ -src/soc/rdc \ +src/mainboard/adlink src/mainboard/purism src/mainboard/ti \ src/superio/acpi src/superio/common \ " -- To view, visit https://review.coreboot.org/c/coreboot/+/39171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a6ca083e79d285b8c596631f21ccdfe2777e20e Gerrit-Change-Number: 39171 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: libpayload: cbfs: fix infinite loop in cbfs_get_{handle,attr}
by Alexandre Rebert (Code Review) 02 Mar '20

02 Mar '20

Alexandre Rebert has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39177 ) Change subject: libpayload: cbfs: fix infinite loop in cbfs_get_{handle,attr} ...................................................................... libpayload: cbfs: fix infinite loop in cbfs_get_{handle,attr} cbfs_get_handle() and cbfs_get_attr() are both looping over elements to find a particular one. Each element header contains the element's length, which is used to compute the next element's offset. Invalid or corrupted CBFS files could lead to infinite loops where the offset would remain constant across iterations, due to 0-length elements or integer overflows in the computation of the next offset. This patch makes both functions more robust by adding a check that ensure offsets are strictly monotonic. Instead of infinite looping, the functions are now printing an ERROR and returning a NULL value. Change-Id: I440e82fa969b8c2aacc5800e7e26450c3b97c74a Signed-off-by: Alex Rebert <alexandre.rebert(a)gmail.com> Found-by: Mayhem --- M payloads/libpayload/libcbfs/cbfs_core.c 1 file changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/39177/1 diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index e94e1e7..54e5de8 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -212,9 +212,15 @@ } // Move to next file. - offset += ntohl(file.len) + ntohl(file.offset); - if (offset % CBFS_ALIGNMENT) - offset += CBFS_ALIGNMENT - (offset % CBFS_ALIGNMENT); + uint32_t new_offset = offset + ntohl(file.len) + ntohl(file.offset); + if (new_offset % CBFS_ALIGNMENT) + new_offset += CBFS_ALIGNMENT - (new_offset % CBFS_ALIGNMENT); + // Check that offset is strictly monotonic to prevent infinite loop + if(new_offset <= offset) { + ERROR("ERROR: corrupted CBFS file header at 0x%x.\n", offset); + break; + } + offset = new_offset; } media->close(media); LOG("WARNING: '%s' not found.\n", name); @@ -309,7 +315,14 @@ return NULL; } if (ntohl(attr.tag) != tag) { - offset += ntohl(attr.len); + uint32_t new_offset = offset + ntohl(attr.len); + // Check that offset is strictly monotonic to prevent infinite loop + if(new_offset <= offset) { + ERROR("ERROR: corrupted CBFS attribute at 0x%x.\n", offset); + m->close(m); + return NULL; + } + offset = new_offset; continue; } ret = m->map(m, offset, ntohl(attr.len)); -- To view, visit https://review.coreboot.org/c/coreboot/+/39177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I440e82fa969b8c2aacc5800e7e26450c3b97c74a Gerrit-Change-Number: 39177 Gerrit-PatchSet: 1 Gerrit-Owner: Alexandre Rebert <alexandre.rebert(a)gmail.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: lint/check_lint_tests: Fix obsolete paths
by HAOUAS Elyes (Code Review) 02 Mar '20

02 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39170 ) Change subject: lint/check_lint_tests: Fix obsolete paths ...................................................................... lint/check_lint_tests: Fix obsolete paths Change-Id: Ieac6e5ba0d425f873c3d4125d828224313017b69 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/lint/check_lint_tests 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/39170/1 diff --git a/util/lint/check_lint_tests b/util/lint/check_lint_tests index 6f6942d..6c050ee 100755 --- a/util/lint/check_lint_tests +++ b/util/lint/check_lint_tests @@ -6,7 +6,7 @@ #lint-stable-000-license-headers TESTFILE000a=src/arch/x86/thread.c -TESTFILE000b=src/arch/ppc64/misc.c +TESTFILE000b=src/arch/riscv/misc.c sed -i.bak 's/^[[:space:]]\*[[:space:]].*//' ${TESTFILE000a} sed -i.bak 's/^[[:space:]]\*[[:space:]]but WITHOUT ANY WARRANTY;//' ${TESTFILE000b} @@ -20,12 +20,10 @@ #lint-stable-005-board-status TESTFILE005a=src/mainboard/google/storm/board_info.txt -TESTFILE005b=src/mainboard/aaeon/pfm-540i_revb/board_info.txt -rm -f ${TESTFILE005a} -sed -i.bak 's/^Category:.*/Category: lint/' ${TESTFILE005b} +sed -i.bak 's/^Category:.*/Category: lint/' ${TESTFILE005a} #lint-stable-006-board-name -TESTFILE006=src/mainboard/amd/bettong/Kconfig.name +TESTFILE006=src/mainboard/ibase/mb899/Kconfig.name rm -f ${TESTFILE006} #lint-stable-008-kconfig -- To view, visit https://review.coreboot.org/c/coreboot/+/39170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieac6e5ba0d425f873c3d4125d828224313017b69 Gerrit-Change-Number: 39170 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google: Increase FW_MAIN_X paritition sizes to accomodate cse blobs
by Sridhar Siricilla (Code Review) 02 Mar '20

02 Mar '20

Sridhar Siricilla has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35405 ) Change subject: mb/google: Increase FW_MAIN_X paritition sizes to accomodate cse blobs ...................................................................... Abandoned For CSE FW Custom SKU, no FMD adjustments are required. -- To view, visit https://review.coreboot.org/c/coreboot/+/35405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67f459bfed00eb63b09170b1711ad334dd5ad891 Gerrit-Change-Number: 35405 Gerrit-PatchSet: 44 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: abandon

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2020