coreboot-gerrit March 2020

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Change in coreboot[master]: mb/google/octopus: support Elan touch panel(include USI pen) for Foob
by Tommie Lin (Code Review) 02 Mar '20

02 Mar '20

Tommie Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38823 ) Change subject: mb/google/octopus: support Elan touch panel(include USI pen) for Foob ...................................................................... mb/google/octopus: support Elan touch panel(include USI pen) for Foob BUG=None TEST=build bios and verify touch screen works fine Signed-off-by: Tommie Lin <tong.lin(a)bitland.corp-partner.google.com> Change-Id: Ibec3d08cc740e398a10a5c845181318724afc70a --- M src/mainboard/google/octopus/variants/foob/overridetree.cb 1 file changed, 11 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38823/1 diff --git a/src/mainboard/google/octopus/variants/foob/overridetree.cb b/src/mainboard/google/octopus/variants/foob/overridetree.cb index b131173..fea012b 100644 --- a/src/mainboard/google/octopus/variants/foob/overridetree.cb +++ b/src/mainboard/google/octopus/variants/foob/overridetree.cb @@ -134,16 +134,17 @@ end end # - I2C 6 device pci 17.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0001"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" device i2c 10 on end end chip drivers/i2c/hid -- To view, visit https://review.coreboot.org/c/coreboot/+/38823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibec3d08cc740e398a10a5c845181318724afc70a Gerrit-Change-Number: 38823 Gerrit-PatchSet: 1 Gerrit-Owner: Tommie Lin <tong.lin(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/var/jinlon: Disable EPS on some SKUs
by Rajat Jain (Code Review) 02 Mar '20

02 Mar '20

Rajat Jain has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39156 ) Change subject: mb/google/hatch/var/jinlon: Disable EPS on some SKUs ...................................................................... mb/google/hatch/var/jinlon: Disable EPS on some SKUs Disable EPS on the SKUs that do not have it. Change-Id: I7305097beea3484634933ab856fd084933868a10 Signed-off-by: Rajat Jain <rajatja(a)google.com> --- M src/mainboard/google/hatch/variants/jinlon/Makefile.inc A src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h A src/mainboard/google/hatch/variants/jinlon/mainboard.c 3 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/39156/1 diff --git a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc index c57d090..d38a577 100644 --- a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc +++ b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc @@ -25,4 +25,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += mainboard.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h new file mode 100644 index 0000000..1d45fcd --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __JINLON_SKU_H__ +#define __JINLON_SKU_H__ + +/* + * SKU definition taken from + * https://buganizer.corp.google.com/issues/145688887#comment16 + */ +enum { + JINLON_SKU_01 = 1, /* No LTE, No view-angle-manegement */ + JINLON_SKU_02 = 2, /* No LTE, view-angle-manegement */ + JINLON_SKU_21 = 21, /* LTE, No view-angle-manegement */ + JINLON_SKU_22 = 22, /* LTE, view-angle-manegement */ +}; + +#endif /* __JINLON_SKU_H__ */ diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c new file mode 100644 index 0000000..75ecdaf --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include <arch/acpi_device.h> +#include <baseboard/variants.h> +#include <bootstate.h> +#include <device/device.h> +#include <drivers/gfx/generic/chip.h> +#include <variant/sku.h> + +static bool eps_sku(uint32_t sku_id) +{ + /* + * Assume EPS SKU by default, helpful for testing on + * unprovisioned or development SKUs. + */ + if (sku_id == JINLON_SKU_01 || sku_id == JINLON_SKU_21) + return false; + else + return true; +} + +static void check_for_eps(uint32_t sku_id) +{ + struct device *gfx_dev; + + if (eps_sku(sku_id)) { + printk(BIOS_INFO, "SKU ID %u has EPS\n", sku_id); + return; + } + + gfx_dev = find_gfx_dev(); + if (!gfx_dev) { + printk(BIOS_ERR, + "Error! No EPS dev, view-angle-management won't work\n"); + return; + } + + printk(BIOS_INFO, + "SKU ID %u doesn't have EPS, disabling...\n", + sku_id); + gfx_dev->enabled = 0; +} + +void variant_devtree_update(void) +{ + uint32_t sku_id = get_board_sku(); + + /* Disable EPS on SKUs that do not support it */ + check_for_eps(sku_id); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7305097beea3484634933ab856fd084933868a10 Gerrit-Change-Number: 39156 Gerrit-PatchSet: 1 Gerrit-Owner: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/hatch/var/jinlon: Enable gfx/generic driver
by Rajat Jain (Code Review) 02 Mar '20

02 Mar '20

Rajat Jain has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39155 ) Change subject: mb/google/hatch/var/jinlon: Enable gfx/generic driver ...................................................................... mb/google/hatch/var/jinlon: Enable gfx/generic driver Enable the GFX device for Jinlon. Change-Id: I6ba90bf464e315ec364b6f35e7670924a2aba25a Signed-off-by: Rajat Jain <rajatja(a)google.com> --- M src/mainboard/google/hatch/Kconfig.name M src/mainboard/google/hatch/variants/jinlon/overridetree.cb 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/39155/1 diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 2427b12..fc3a66e 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -19,6 +19,7 @@ bool "-> Jinlon" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GFX_GENERIC config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index f3f6c3b..f7ca7d5 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -65,6 +65,17 @@ register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 02.0 on + chip drivers/gfx/generic + register "device_count" = "1" + register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E0)" + device generic 0 on end + end + end # Integrated Graphics Device device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/39155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ba90bf464e315ec364b6f35e7670924a2aba25a Gerrit-Change-Number: 39155 Gerrit-PatchSet: 1 Gerrit-Owner: Rajat Jain <rajatja(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: drivers/gfx/generic: Add support for gpio based EPS
by Rajat Jain (Code Review) 02 Mar '20

02 Mar '20

Rajat Jain has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39154 ) Change subject: drivers/gfx/generic: Add support for gpio based EPS ...................................................................... drivers/gfx/generic: Add support for gpio based EPS Add support to control EPS via a PCH gpio Change-Id: I6f570fd43e1649fb23255b0890e01086e34f844a Signed-off-by: Rajat Jain <rajatja(a)google.com> --- M src/drivers/gfx/generic/chip.h M src/drivers/gfx/generic/generic.c 2 files changed, 73 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/39154/1 diff --git a/src/drivers/gfx/generic/chip.h b/src/drivers/gfx/generic/chip.h index 5e855e3..ef7d9db 100644 --- a/src/drivers/gfx/generic/chip.h +++ b/src/drivers/gfx/generic/chip.h @@ -28,6 +28,12 @@ const char *enable_function; /* ACPI namespace path to privacy screen disable function */ const char *disable_function; + /* + * GPIO used for controlling the privacy screen. If provided, + * the gpio mechanism takes preference over the functions ptrs + * above, if any (GPIO functions override the function ptrs). + */ + struct acpi_gpio gpio; }; /* Config for an output device as defined in section A.5 of the ACPI spec */ @@ -53,4 +59,6 @@ struct drivers_gfx_generic_device_config device[5]; }; +extern struct device *find_gfx_dev(void); + #endif /* __DRIVERS_GFX_GENERIC_CHIP_H__ */ diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index 8488040..7b5ddc7 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -24,6 +24,11 @@ #define ACPI_DSM_PRIVACY_SCREEN_UUID "C7033113-8720-4CEB-9090-9D52B3E52D73" +#define ACPI_METHOD_EPS_PRESENT "EPSP" +#define ACPI_METHOD_EPS_STATE "EPSS" +#define ACPI_METHOD_EPS_ENABLE "EPSE" +#define ACPI_METHOD_EPS_DISABLE "EPSD" + static void privacy_screen_detect_cb(void *arg) { struct drivers_gfx_generic_privacy_screen_config *config = arg; @@ -62,6 +67,52 @@ privacy_screen_disable_cb, }; +static void privacy_gpio_acpigen(struct acpi_gpio *gpio) +{ + /* EPS Present */ + acpigen_write_method(ACPI_METHOD_EPS_PRESENT, 0); + acpigen_write_return_byte(1); + acpigen_pop_len(); + + /* EPS State */ + acpigen_write_method(ACPI_METHOD_EPS_STATE, 0); + acpigen_get_rx_gpio(gpio); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_pop_len(); + + /* EPS Enable */ + acpigen_write_method(ACPI_METHOD_EPS_ENABLE, 0); + acpigen_enable_tx_gpio(gpio); + acpigen_pop_len(); + + /* EPS Disable */ + acpigen_write_method(ACPI_METHOD_EPS_DISABLE, 0); + acpigen_disable_tx_gpio(gpio); + acpigen_pop_len(); +} + +static void gfx_fill_privacy_screen_dsm(struct + drivers_gfx_generic_privacy_screen_config *privacy) +{ + if (!privacy->enabled) + return; + + /* Populate ACPI methods, if EPS controlled via gpio */ + if (privacy->gpio.pin_count == 1) { + privacy_gpio_acpigen(&privacy->gpio); + privacy->detect_function = ACPI_METHOD_EPS_PRESENT; + privacy->status_function = ACPI_METHOD_EPS_STATE; + privacy->enable_function = ACPI_METHOD_EPS_ENABLE; + privacy->disable_function = ACPI_METHOD_EPS_DISABLE; + } + + acpigen_write_dsm(ACPI_DSM_PRIVACY_SCREEN_UUID, + privacy_screen_callbacks, + ARRAY_SIZE(privacy_screen_callbacks), + privacy); +} + static void gfx_fill_ssdt_generator(struct device *dev) { size_t i; @@ -69,7 +120,7 @@ const char *scope = acpi_device_scope(dev); - if (!scope) + if (!scope || !dev->enabled) return; acpigen_write_scope(scope); @@ -85,17 +136,9 @@ for (i = 0; i < config->device_count; i++) { acpigen_write_device(config->device[i].name); - acpigen_write_name_integer("_ADR", config->device[i].addr); acpigen_write_name_integer("_STA", 0xF); - - if (config->device[i].privacy.enabled) { - acpigen_write_dsm(ACPI_DSM_PRIVACY_SCREEN_UUID, - privacy_screen_callbacks, - ARRAY_SIZE(privacy_screen_callbacks), - &config->device[i].privacy); - } - + gfx_fill_privacy_screen_dsm(&config->device[i].privacy); acpigen_pop_len(); /* Device */ } acpigen_pop_len(); /* Scope */ @@ -117,7 +160,7 @@ { struct drivers_gfx_generic_config *config = dev->chip_info; - if (!config) + if (!config || !dev->enabled) return; dev->ops = &gfx_ops; @@ -127,3 +170,14 @@ CHIP_NAME("Generic Graphics Device") .enable_dev = gfx_enable }; + +struct device *find_gfx_dev(void) +{ + struct device *dev; + + for (dev = all_devices; dev; dev = dev->next) { + if (dev->chip_ops && dev->chip_ops == &drivers_gfx_generic_ops) + return dev; + } + return NULL; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f570fd43e1649fb23255b0890e01086e34f844a Gerrit-Change-Number: 39154 Gerrit-PatchSet: 1 Gerrit-Owner: Rajat Jain <rajatja(a)google.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: arch/x86/acpigen: Add new helper routines for XOR and get_rx_gpio
by Rajat Jain (Code Review) 02 Mar '20

02 Mar '20

Rajat Jain has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39145 ) Change subject: arch/x86/acpigen: Add new helper routines for XOR and get_rx_gpio ...................................................................... arch/x86/acpigen: Add new helper routines for XOR and get_rx_gpio Add new helper function in the acpigen library, that use the underlying soc routines. Change-Id: I8d65699d3c806007a50adcb51c5d84567ce451b7 Signed-off-by: Rajat Jain <rajatja(a)google.com> --- M Documentation/acpi/gpio.md M src/arch/x86/acpigen.c M src/arch/x86/include/arch/acpigen.h 3 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39145/1 diff --git a/Documentation/acpi/gpio.md b/Documentation/acpi/gpio.md index d42042f..b9acd96 100644 --- a/Documentation/acpi/gpio.md +++ b/Documentation/acpi/gpio.md @@ -73,6 +73,15 @@ functions internally. Thus, all the ACPI AML calling conventions for the platform functions apply to these helper functions as well. +3. Get Rx GPIO + int acpigen_get_rx_gpio(struct acpi_gpio gpio) + +This function takes as input, an struct acpi_gpio type and outputs +AML code to read the *logical* value of a gpio (after taking its +polarity into consideration), into the Local0 variable. It calls +the platform specific acpigen_soc_read_rx_gpio() to actually read +the rx gpio value. + ## Implementation Details ACPI library in coreboot will provide weak definitions for all the diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 72605bb..2dad00a 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1203,6 +1203,15 @@ acpigen_emit_byte(res); } +/* Xor (arg1, arg2, res) */ +void acpigen_write_xor(uint9_t arg1, uint8_t arg2, uint8_t res) +{ + acpigen_emit_byte(XOR_OP); + acpigen_emit_byte(arg1); + acpigen_emit_byte(arg2); + acpigen_emit_byte(res); +} + /* And (arg1, arg2, res) */ void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res) { @@ -1759,6 +1768,14 @@ return acpigen_soc_clear_tx_gpio(gpio->pins[0]); } +void acpigen_get_rx_gpio(struct acpi_gpio *gpio) +{ + acpigen_soc_read_rx_gpio(gpio->pins[0]); + + if (gpio->polarity == ACPI_GPIO_ACTIVE_LOW) + acpigen_write_xor(LOCAL0_OP, 1, LOCAL0_OP); +} + /* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, u16 range_min, u16 range_max, u16 translation, u16 length) diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 0807558..34c5197 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -361,6 +361,7 @@ void acpigen_write_store(void); void acpigen_write_store_ops(uint8_t src, uint8_t dst); void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res); +void acpigen_write_xor(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_not(uint8_t arg, uint8_t res); void acpigen_write_debug_string(const char *str); @@ -472,6 +473,14 @@ int acpigen_enable_tx_gpio(struct acpi_gpio *gpio); int acpigen_disable_tx_gpio(struct acpi_gpio *gpio); +/* + * Helper function for getting a RX GPIO value based on the GPIO polarity. + * The return value is stored in Local0 variable. + * This function ends up calling acpigen_soc_get_rx_gpio to make callbacks + * into SoC acpigen code + */ +void acpigen_get_rx_gpio(struct acpi_gpio *gpio); + /* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, u16 range_min, u16 range_max, u16 translation, u16 length); @@ -481,4 +490,5 @@ /* refer to ACPI 6.4.3.5.1 QWord Address Space Descriptor section for details */ void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/39145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d65699d3c806007a50adcb51c5d84567ce451b7 Gerrit-Change-Number: 39145 Gerrit-PatchSet: 1 Gerrit-Owner: Rajat Jain <rajatja(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Add Heads to payloads
by Patrick Rudolph (Code Review) 02 Mar '20

02 Mar '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39150 ) Change subject: Documentation: Add Heads to payloads ...................................................................... Documentation: Add Heads to payloads Add a small description about Heads. Change-Id: I2e768a640751fee1b1b5df4401205e24cde0607c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/payloads.md 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/39150/1 diff --git a/Documentation/payloads.md b/Documentation/payloads.md index b1eae61..eee841e 100644 --- a/Documentation/payloads.md +++ b/Documentation/payloads.md @@ -40,3 +40,15 @@ firmware project drivers that often reinvent the wheel) and the ability to define boot policy with familiar tools, no matter if those are shell scripts or compiled userland programs written in C, Go or other programming languages. + +## Heads + +[Heads] is a distribution that bundles coreboot, Linux, busybox and custom +tools to provide reproducible ROMs. [Heads] aims to provide a secure and +flexible boot environment for laptops and servers. +It supports features like measured boot, kexec, GPG, OTP, TLS, firmware +updates, but only works on a limited amount of mainboards. +For more details have a look at [heads-wiki]. + +[Heads]: https://github.com/osresearch/heads +[heads-wiki]: http://osresearch.net/ \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/39150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e768a640751fee1b1b5df4401205e24cde0607c Gerrit-Change-Number: 39150 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: Documentation: Tutorial me_cleaner on Lenovo devices
by Patrick Rudolph (Code Review) 02 Mar '20

02 Mar '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39129 ) Change subject: Documentation: Tutorial me_cleaner on Lenovo devices ...................................................................... Documentation: Tutorial me_cleaner on Lenovo devices Add a tutorial how to use ME cleaner, and give some basic steps to strip the ME. Tested on Lenovo X220 with stripped ME and found no issues: * Displayport * VGA * USB * Bluetooth * Wifi * Wifi-kill switch * libgfxinit * SATA * Audio * SD-card * Ethernet * Keyboard * Fn-Keys * Display brightness * S3 resume * Battery events * CPU temperature reporting * FAN managment * Stress test stable * Youtube videos over Wifi * stress -c 2 -m 1 -d 1 * glxgears Change-Id: I0b1d04f00b5dbb38cf04333f2b345749b740a375 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md M Documentation/mainboard/lenovo/Sandy_Bridge_series.md A Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg A Documentation/mainboard/lenovo/stripping_me.md 4 files changed, 154 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39129/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 126a8fb..413bf03 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -66,6 +66,7 @@ ## Lenovo - [Mainboard codenames](lenovo/codenames.md) +- [Stripping ME](lenovo/stripping_me.md) - [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md) - [R60](lenovo/r60.md) - [T4xx common](lenovo/t4xx_series.md) diff --git a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md index 0b833f5..cba9a06 100644 --- a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md @@ -33,9 +33,7 @@ usable by coreboot. * ROM chip size should be set to 8MiB. -```eval_rst -Please also have a look at :doc:`../../flash_tutorial/index`. -``` +Please also have a look at the [flashing tutorial] ## Flash layout There's one 8MiB flash which contains IFD, GBE, ME and BIOS regions. @@ -46,3 +44,27 @@ [fl]: flashlayout_Sandy_Bridge.svg +## Reducing Intel Managment Engine firmware size + +It is possible to reduce the Intel ME firmware size to free additional +space for the `bios` region. This is usually refered to as *cleaning the ME* or +*stripping the ME*. See general notes on [me_cleaner]. + +With the reduced Intel ME firmware the IFD, GbE and ME regions require +less than 128 KiB of space in the ROM. + +The modified flash layout needs to be written to IFD! +Have a look at the [ME tutorial] for more information. + +Tests on Lenovo X220 showed no issues with a stripped ME firmware. + + +**Modified flash layout:** + +![][fl2] + +[fl2]: flashlayout_Sandy_Bridge_stripped_me.svg + +[ME tutorial]: stripping_me.md +[me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md +[flashing tutorial]: ../../flash_tutorial/ext_power.md diff --git a/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg b/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg new file mode 100644 index 0000000..d8d8213 --- /dev/null +++ b/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg @@ -0,0 +1,74 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="9cm" height="8cm" viewBox="268 -156 168 158" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <g> + <g> + <rect style="fill: #ffffff" x="307.888" y="-152.131" width="49.1438" height="30.4667"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #ffffff" x="307.888" y="-152.131" width="49.1438" height="30.4667"/> + </g> + <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #ffffff" x="307.888" y="-152.131" width="49.1438" height="30.4667"/> + </g> + <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x="307.888" y="-152.131" width="49.1438" height="30.4667"/> + <text font-size="6.77323" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="332.46" y="-134.831"> + <tspan x="332.46" y="-134.831">IFD</tspan> + </text> + </g> + <g> + <g> + <rect style="fill: #ffffff" x="307.934" y="-56.9106" width="49.1438" height="56.1492"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 0.02; stroke: #ffffff" x="307.934" y="-56.9106" width="49.1438" height="56.1492"/> + </g> + <rect style="fill: none; fill-opacity:0; stroke-width: 0.02; stroke: #ffffff" x="307.934" y="-56.9106" width="49.1438" height="56.1492"/> + </g> + <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x="308.096" y="-57.559" width="49.1438" height="57.2839"/> + <text font-size="6.77323" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="332.182" y="-24.0245"> + <tspan x="332.182" y="-24.0245">BIOS</tspan> + </text> + <g> + <g> + <g> + <rect style="fill: #ffffff" x="308" y="-121.59" width="49.1438" height="30.4667"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #ffffff" x="308" y="-121.59" width="49.1438" height="30.4667"/> + </g> + <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #ffffff" x="308" y="-121.59" width="49.1438" height="30.4667"/> + </g> + <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x="308" y="-121.59" width="49.1438" height="30.4667"/> + <text font-size="6.77323" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="332.572" y="-104.29"> + <tspan x="332.572" y="-104.29">GBE</tspan> + </text> + </g> + <text font-size="7.15705" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="268.961" y="-148.674"> + <tspan x="268.961" y="-148.674">0x000000</tspan> + </text> + <text font-size="6.77323" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="269.152" y="-120.399"> + <tspan x="269.152" y="-120.399">0x001000</tspan> + </text> + <text font-size="6.77323" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="269.155" y="-90.6472"> + <tspan x="269.155" y="-90.6472">0x003000</tspan> + </text> + <text font-size="6.77323" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="269.461" y="-56.4289"> + <tspan x="269.461" y="-56.4289">0x020000</tspan> + </text> + <text font-size="6.77323" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="270.008" y="0.198407"> + <tspan x="270.008" y="0.198407">0x800000</tspan> + </text> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 380.877 -151.013 C 401.876,-151.013 379.377,-73.513 400.627,-72.513"/> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 381.377 -0.763268 C 395.238,-0.763268 387.016,-72.763 400.877,-72.763"/> + <text font-size="6.77323" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="406.127" y="-68.513"> + <tspan x="406.127" y="-68.513">Flash #0</tspan> + </text> + <g> + <g> + <g> + <rect style="fill: #ffffff" x="308.189" y="-90.5898" width="49.1438" height="33.4161"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #ffffff" x="308.189" y="-90.5898" width="49.1438" height="33.4161"/> + </g> + <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #ffffff" x="308.189" y="-90.5898" width="49.1438" height="33.4161"/> + </g> + <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x="308.189" y="-90.5898" width="49.1438" height="32.8215"/> + <text font-size="6.77323" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="331.572" y="-70.23"> + <tspan x="331.572" y="-70.23">ME</tspan> + </text> + </g> +</svg> diff --git a/Documentation/mainboard/lenovo/stripping_me.md b/Documentation/mainboard/lenovo/stripping_me.md new file mode 100644 index 0000000..00cb2e0 --- /dev/null +++ b/Documentation/mainboard/lenovo/stripping_me.md @@ -0,0 +1,54 @@ +# Tutorial reducing the Intel ME firmware size + +This tutorial is written for the Lenovo Intel Sandy Bridge/Ivy Bridge devices, +but applies to additional platforms with slightly differences. + +It is possible to reduce the Intel ME firmware size to free additional +space for the `bios` region. This is usually refered to as *cleaning the ME* or +*stripping the ME*. The ME is forced into a non-functional recovery state, +which sets the platform in an undefined state. +See general notes on [me_cleaner]. + +With the reduced Intel ME firmware the `ifd`, `gbe` and `me` regions require +less than 128 KiB of space in the ROM, which leaves the remaining for the +`bios` region. + +This tutorial will guide through the steps necessary. + +## Obtain a full ROM + +You need a full and working ROM with a full Intel ME firmware. + +## Running me_cleaner + +You need to run the me_cleaner on a full ROM, here called `fulldump.rom`: + +It will then generate 2 new files: +```console +./util/me_cleaner/me_cleaner.py -D patched_desciptor.bin -M stripped_me.bin fulldump.rom -t -r -S +``` +It will then generate 2 new files: +* a patched IFD called `patched_desciptor.bin` +* stripped Intel ME called `stripped_me.bin` + +The patched IFD has the `AltMeDisable` bit set and a modified flash layout. + +## Build coreboot + +1. Now include the two new files into coreboot's build system. +2. Make sure to also increase the CBFS size + * 0x7E0000 for a 8MiB ROM + * 0xBE0000 for a 12MiB ROM + * 0xFE0000 for a 16MiB ROM + +## Flashing the ROM + +As you have modified the layout you need to write the **full ROM** to flash. +Make sure to include all partitions into the ROM: +* IFD +* EC (might be unused) +* GbE (might be unused) +* ME +* BIOS + +[me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md -- To view, visit https://review.coreboot.org/c/coreboot/+/39129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1d04f00b5dbb38cf04333f2b345749b740a375 Gerrit-Change-Number: 39129 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: soc/intel/common: Add print_me_fw_version() to cse lib
by Sridhar Siricilla (Code Review) 02 Mar '20

02 Mar '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39010 ) Change subject: soc/intel/common: Add print_me_fw_version() to cse lib ...................................................................... soc/intel/common: Add print_me_fw_version() to cse lib Add print_me_fw_version() which queries and logs ME's Firmware version. TEST=Verified on hatch, soraka and bobba. Change-Id: I7567fac100b14dc207b7fc6060e7a064fb05caf6 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39010/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 5877d53..679143b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -756,6 +756,67 @@ return resp.status; } +void print_me_fw_version(void *unused) +{ + struct version { + uint16_t minor; + uint16_t major; + uint16_t build; + uint16_t hotfix; + } __packed; + + struct fw_ver_resp { + struct mkhi_hdr hdr; + struct version code; + struct version rec; + struct version fitc; + } __packed; + + const struct mkhi_hdr fw_ver_msg = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_GEN_GET_FW_VERSION, + }; + + struct fw_ver_resp resp; + size_t resp_size = sizeof(resp); + + /* Ignore if UART debugging is disabled */ + if (!CONFIG(CONSOLE_SERIAL)) + return; + + /* + * Ignore if ME Firmware SKU type is custom since + * print_boot_partition_info() logs RO(BP1) and RW(BP2) versions. + */ + if (cse_is_hfs3_fw_sku_custom()) + return; + + /* + * Prerequisites: + * 1) HFSTS1 Current Working State is Normal + * 2) HFSTS1 Current Operation Mode is Normal + * 3) It's after DRAM INIT DONE message (taken care of by calling it + * during ramstage + */ + if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal()) + goto fail; + + heci_reset(); + + if (!heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), &resp, &resp_size)) + goto fail; + + if (resp.hdr.result) + goto fail; + + printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, + resp.code.minor, resp.code.hotfix, resp.code.build); + return; + +fail: + printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); +} + #if ENV_RAMSTAGE static void update_sec_bar(struct device *dev) diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index c597a3f..dcdf81d 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -22,6 +22,7 @@ /* MKHI Command groups */ #define MKHI_GROUP_ID_CBM 0x0 #define MKHI_GROUP_ID_HMRFPO 0x5 +#define MKHI_GROUP_ID_GEN 0xff /* Global Reset Command ID */ #define MKHI_CBM_GLOBAL_RESET_REQ 0xb @@ -33,6 +34,9 @@ #define MKHI_HMRFPO_ENABLE 0x1 #define MKHI_HMRFPO_GET_STATUS 0x3 +/* Get Firmware Version Command Id */ +#define MKHI_GEN_GET_FW_VERSION 0x2 + /* ME Current Working States */ #define ME_HFS1_CWS_NORMAL 0x5 @@ -163,6 +167,11 @@ #define MKHI_HMRFPO_ENABLED 2 /* + * Queries and logs ME firmware version + */ +void print_me_fw_version(void *unused); + +/* * Checks current working operation state is normal or not. * Returns true if CSE's current working state is normal, otherwise false. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7567fac100b14dc207b7fc6060e7a064fb05caf6 Gerrit-Change-Number: 39010 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/apollolake: Display platform information
by Patrick Georgi (Code Review) 02 Mar '20

02 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38824 ) Change subject: soc/intel/apollolake: Display platform information ...................................................................... soc/intel/apollolake: Display platform information This patch includes the change required to display Apollo Lake platform information which reports CPU, MCH, PCH and IGD information in romstage. BUG=None TEST= 1. Boot to OS on Bobba board. 2. Verified below info from CPU Console log in romstage CPU: Intel(R) Celeron(R) N4000 CPU @ 1.10GHz CPU: ID 706a1, Geminilake B0, ucode: 00000031 CPU: AES supported, TXT NOT supported, VT supported MCH: device id 31f0 (rev 03) is Geminilake PCH: device id 3197 (rev 03) is Geminilake IGD: device id 3185 (rev 03) is Geminilake EU12 Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Signed-off-by: Usha P <usha.p(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38824 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/include/soc/romstage.h A src/soc/intel/apollolake/report_platform.c M src/soc/intel/apollolake/romstage.c 4 files changed, 173 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1fbdc91..b420dea 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -24,6 +24,7 @@ romstage-y += car.c romstage-y += ../../../cpu/intel/car/romstage.c romstage-y += romstage.c +romstage-y += report_platform.c romstage-y += gspi.c romstage-y += heci.c romstage-y += i2c.c diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h index da30de5..3466abe 100644 --- a/src/soc/intel/apollolake/include/soc/romstage.h +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -23,5 +23,6 @@ void set_max_freq(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void mainboard_save_dimm_info(void); +void report_platform_info(void); #endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/report_platform.c b/src/soc/intel/apollolake/report_platform.c new file mode 100644 index 0000000..6f4c74e --- /dev/null +++ b/src/soc/intel/apollolake/report_platform.c @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/name.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/mp_init.h> +#include <soc/romstage.h> +#include <soc/pci_devs.h> + +static struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_APOLLOLAKE_A0, "Apollolake A0" }, + { CPUID_APOLLOLAKE_B0, "Apollolake B0" }, + { CPUID_APOLLOLAKE_E0, "Apollolake E0" }, + { CPUID_GLK_A0, "Geminilake A0" }, + { CPUID_GLK_B0, "Geminilake B0" }, + { CPUID_GLK_R0, "Geminilake R0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DEVICE_ID_INTEL_GLK_NB, "Geminilake" }, + { PCI_DEVICE_ID_INTEL_APL_NB, "Apollolake" }, +}; + +static struct { + u16 lpcid; + const char *name; +} pch_table[] = { + { PCI_DEVICE_ID_INTEL_APL_LPC, "Apollolake" }, + { PCI_DEVICE_ID_INTEL_GLK_LPC, "Geminilake" }, + { PCI_DEVICE_ID_INTEL_GLK_ESPI, "Geminilake" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DEVICE_ID_INTEL_APL_IGD_HD_505, "Apollolake HD 505" }, + { PCI_DEVICE_ID_INTEL_APL_IGD_HD_500, "Aplollolake HD 500" }, + { PCI_DEVICE_ID_INTEL_GLK_IGD, "Geminilake" }, + { PCI_DEVICE_ID_INTEL_GLK_IGD_EU12, "Geminilake EU12" }, +}; + +static uint8_t get_dev_revision(pci_devfn_t dev) +{ + return pci_read_config8(dev, PCI_REVISION_ID); +} + +static uint16_t get_dev_id(pci_devfn_t dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} + +static void report_cpu_info(void) +{ + uint32_t i, cpu_id, cpu_feature_flag; + char cpu_name[49]; + msr_t microcode_ver; + const char *support = "Supported"; + const char *no_support = "Not Supported"; + const char *cpu_type = "Unknown"; + + fill_processor_name(cpu_name); + + microcode_ver.lo = 0; + microcode_ver.hi = 0; + wrmsr(IA32_BIOS_SIGN_ID, microcode_ver); + cpu_id = cpu_get_cpuid(); + microcode_ver = rdmsr(IA32_BIOS_SIGN_ID); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpu_id) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_INFO, "CPU: %s\n", cpu_name); + printk(BIOS_INFO, "CPU: ID %x, %s, ucode: %08x\n", cpu_id, cpu_type, microcode_ver.hi); + + cpu_feature_flag = cpu_get_feature_flags_ecx(); + printk(BIOS_INFO, "CPU: AES %s, TXT %s, VT %s\n", + (cpu_feature_flag & CPUID_AES) ? support : no_support, + (cpu_feature_flag & CPUID_SMX) ? support : no_support, + (cpu_feature_flag & CPUID_VMX) ? support : no_support); +} + +static void report_mch_info(void) +{ + uint32_t i; + pci_devfn_t dev = SA_DEV_ROOT; + uint16_t mchid = get_dev_id(dev); + uint8_t mch_revision = get_dev_revision(dev); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_INFO, "MCH: device id %04x (rev %02x) is %s\n", + mchid, mch_revision, mch_type); +} + +static void report_pch_info(void) +{ + uint32_t i; + pci_devfn_t dev = PCH_DEV_LPC; + uint16_t lpcid = get_dev_id(dev); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].lpcid == lpcid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_INFO, "PCH: device id %04x (rev %02x) is %s\n", + lpcid, get_dev_revision(dev), pch_type); +} + +static void report_igd_info(void) +{ + uint32_t i; + pci_devfn_t dev = SA_DEV_IGD; + uint16_t igdid = get_dev_id(dev); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_INFO, "IGD: device id %04x (rev %02x) is %s\n", + igdid, get_dev_revision(dev), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 258f4ff..13adeee 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -198,6 +198,7 @@ const void *new_var_data; soc_early_romstage_init(); + report_platform_info(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); -- To view, visit https://review.coreboot.org/c/coreboot/+/38824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Gerrit-Change-Number: 38824 Gerrit-PatchSet: 9 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/emulation/qemu-aarch64: Add ARM trusted firmware support
by Patrick Rudolph (Code Review) 02 Mar '20

02 Mar '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38535 ) Change subject: mb/emulation/qemu-aarch64: Add ARM trusted firmware support ...................................................................... mb/emulation/qemu-aarch64: Add ARM trusted firmware support Tested on qemu-system-aarch64: Fixes a hang and allows to boot into Linux userspace. Change-Id: I809742522240185431621cc4fd8b9c7deaf2bb54 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/emulation/qemu-aarch64/Kconfig M src/mainboard/emulation/qemu-aarch64/Makefile.inc M src/mainboard/emulation/qemu-aarch64/bootblock.c M src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h M src/mainboard/emulation/qemu-aarch64/mainboard.c M src/mainboard/emulation/qemu-aarch64/memlayout.ld 6 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/38535/1 diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index 895446d..0579b04 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -27,6 +27,7 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT select MISSING_BOARD_RESET + select ARM64_USE_ARM_TRUSTED_FIRMWARE config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-aarch64/Makefile.inc b/src/mainboard/emulation/qemu-aarch64/Makefile.inc index 4d5f2bd..b710f15 100644 --- a/src/mainboard/emulation/qemu-aarch64/Makefile.inc +++ b/src/mainboard/emulation/qemu-aarch64/Makefile.inc @@ -24,3 +24,5 @@ bootblock-y += bootblock_custom.S CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +BL31_MAKEARGS += PLAT=qemu ARM_ARCH_MAJOR=8 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" diff --git a/src/mainboard/emulation/qemu-aarch64/bootblock.c b/src/mainboard/emulation/qemu-aarch64/bootblock.c index 2c878b6..d4b3c6f 100644 --- a/src/mainboard/emulation/qemu-aarch64/bootblock.c +++ b/src/mainboard/emulation/qemu-aarch64/bootblock.c @@ -16,6 +16,8 @@ #include <bootblock_common.h> #include <symbols.h> +extern u8 _secram[], _esecram[]; + void bootblock_mainboard_init(void) { mmu_init(); @@ -27,5 +29,7 @@ mmu_config_range(_romstage, REGION_SIZE(romstage), MA_MEM | MA_S | MA_RW); mmu_config_range(_ramstage, REGION_SIZE(ramstage), MA_MEM | MA_S | MA_RW); + mmu_config_range(_secram, REGION_SIZE(secram), MA_MEM | MA_S | MA_RW); + mmu_enable(); } diff --git a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h index 6f0c802..7233863 100644 --- a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h @@ -23,6 +23,7 @@ * 0x0905_0000..0x0907_0000: SMMU (smmu-v3) * 0x0a00_0000..0x0a00_0200: MMIO (virtio) * 0x0c00_0000..0x0e00_0000: Platform bus + * 0x0e00_0000..0x0eff_ffff: Secure SRAM * 0x4000_0000..: RAM */ #define VIRT_UART_BASE 0x09000000 @@ -32,3 +33,4 @@ #define VIRT_SMMU_BASE 0x09050000 #define VIRT_MMIO_BASE 0x0a000000 #define VIRT_PLATFORM_BUS_BASE 0x0c000000 +#define VIRT_SECRAM_BASE 0xe000000 diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c index 5735455..7eaed5b 100644 --- a/src/mainboard/emulation/qemu-aarch64/mainboard.c +++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c @@ -10,6 +10,15 @@ #include <ramdetect.h> #include <symbols.h> #include <device/device.h> +#include <bootmem.h> +#include <console/console.h> + +extern u8 _secram[], _esecram[]; + +void bootmem_platform_add_ranges(void) +{ + bootmem_add_range((uintptr_t)_secram, REGION_SIZE(secram), BM_MEM_BL31); +} static void mainboard_enable(struct device *dev) { diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index cd86073..beb30a3 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -22,6 +22,7 @@ { REGION(flash, 0x00000000, CONFIG_ROM_SIZE, 8) + REGION(secram, 0xe000000, 0xf000000, 4096) DRAM_START(0x40000000) BOOTBLOCK(0x60010000, 64K) STACK(0x60020000, 62K) -- To view, visit https://review.coreboot.org/c/coreboot/+/38535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I809742522240185431621cc4fd8b9c7deaf2bb54 Gerrit-Change-Number: 38535 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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