coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/asrock/h110m: add libgfxinit support
by Angel Pons (Code Review) 03 Mar '20

03 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39104 ) Change subject: mb/asrock/h110m: add libgfxinit support ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/39104/10//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39104/10//COMMIT_MSG@7 PS10, Line 7: mb/asrock/h110m: add libgfxinit support > The board contains a VGA connector, but it doesn't work with libgfx. […] It probably doesn't work because it is wired through a DP-to-VGA converter. This means that some DPx port must be enabled. If you use `xrandr` on Linux (with the X server) the video outputs have a name. -- To view, visit https://review.coreboot.org/c/coreboot/+/39104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d87413f87d00986111ecb7b046423ff5eac1bf1 Gerrit-Change-Number: 39104 Gerrit-PatchSet: 11 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 02 Mar 2020 23:26:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572
by Angel Pons (Code Review) 03 Mar '20

03 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mainboard: Add Acer ES1-572 ...................................................................... Patch Set 4: (4 comments) > Patch Set 4: Code-Review+1 > > (4 comments) I'll take care of the comments someday. I would prefer to fix leaf blower syndrome first, though. https://review.coreboot.org/c/coreboot/+/38978/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38978/4//COMMIT_MSG@7 PS4, Line 7: mainboard > mb/acer: The "acer" folder is not there just yet (or at least it wasn't last time I checked), so the change has to add it. It's not a big deal. https://review.coreboot.org/c/coreboot/+/38978/4//COMMIT_MSG@19 PS4, Line 19: tianocore > TianoCore But its folder is named "tianocore" ? (I just can't stand the capitalized spelling) https://review.coreboot.org/c/coreboot/+/38978/4//COMMIT_MSG@19 PS4, Line 19: Linux > Which version? Honestly, I have no idea. Since my OCD loathes that question, I'll just put "Arch Linux", which has no version numbers >:) I mean, I don't want to have to keep updating that number while I wait for my executive function to recharge. https://review.coreboot.org/c/coreboot/+/38978/4//COMMIT_MSG@24 PS4, Line 24: need > needs? It's actually plural: (things that) are not working or need testing. -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Mar 2020 23:20:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add I2C driver
by Julius Werner (Code Review) 03 Mar '20

03 Mar '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36830 ) Change subject: sc7180: Add I2C driver ...................................................................... Patch Set 27: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61221ffff8afe5c7ede5abb9e194e242ab0274d8 Gerrit-Change-Number: 36830 Gerrit-PatchSet: 27 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 02 Mar 2020 23:06:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add UART support
by Julius Werner (Code Review) 03 Mar '20

03 Mar '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35500 ) Change subject: sc7180: Add UART support ...................................................................... Patch Set 40: Code-Review+2 (2 comments) https://review.coreboot.org/c/coreboot/+/35500/39/src/soc/qualcomm/sc7180/q… File src/soc/qualcomm/sc7180/qupv3_uart.c: https://review.coreboot.org/c/coreboot/+/35500/39/src/soc/qualcomm/sc7180/q… PS39, Line 157: #ifndef __PRE_RAM__ > This macro has been removed, so this #ifndef does nothing anymore. Just remove it. Done https://review.coreboot.org/c/coreboot/+/35500/39/src/soc/qualcomm/sc7180/q… PS39, Line 165: serial.regwidth = 4; > Should add a […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Gerrit-Change-Number: 35500 Gerrit-PatchSet: 40 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 02 Mar 2020 23:05:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add QUPv3 FW load & config
by Julius Werner (Code Review) 03 Mar '20

03 Mar '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35499 ) Change subject: sc7180: Add QUPv3 FW load & config ...................................................................... Patch Set 40: (9 comments) Please make sure you always address all comments -- we cannot submit patches unless they pass CI and all comments are resolved in Gerrit. (You can click on "Comment Threads" to easily see all still unresolved comments across all patch sets.) https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/b… File src/soc/qualcomm/sc7180/bootblock.c: https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/b… PS39, Line 20: #include <soc/qi2s.h> > > src/soc/qualcomm/sc7180/bootblock.c:20:10: fatal error: soc/qi2s.h: No such file or directory […] *ping* Still outstanding. https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/i… File src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h: https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/i… PS39, Line 471: int size); > Should fit on one 96 characters line. I'd say before the rest of the codebase is transitioned to 96 characters we shouldn't force new submissions to use it. https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/i… File src/soc/qualcomm/sc7180/include/soc/qupv3_config.h: https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/i… PS40, Line 54: #define QUPV3_UART_SRC_HZ 7372800 Again, this should also be used for where 7372800 appears in clock.c. You probably want to define it in <soc/clock.h>. https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/q… File src/soc/qualcomm/sc7180/qupv3_config.c: https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/q… PS39, Line 89: if (mode == GSI) { > In earlier versions the UARTs used 'mode = FIFO', but with this patch they'll also be MIXED. […] Looks like you did this? (Please make sure to always mark comments you addressed as "Done", Gerrit won't let us submit a patch until all comments are resolved.) https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/q… PS39, Line 174: qup_load_se_firmware > Merged two functions. Done https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/q… File src/soc/qualcomm/sc7180/qupv3_config.c: https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/q… PS40, Line 22: size_t fw_size; You don't need this, so you can just pass NULL to cbfs_boot_map_with_leak(). https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/q… PS40, Line 31: switch (protocol) { How about just const char * filename[] = { [SE_PROTOCOL_SPI] = "fallback/spi_fw", [SE_PROTOCOL_UART] = "fallback/uart_fw", [SE_PROTOCOL_I2C] = "fallback/i2c_fw", } if (fw_list[protocol] >= SE_PROTOCOL_MAX || !filename[protocol]) die(...); if (!fw_list[protocol]) { fw_list[protocol] = cbfs_boot_map_with_leak(filename[protocol], CBFS_TYPE_RAW, NULL); if (!fw_list[protocol]) die(...); } https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/q… PS40, Line 51: assert(protocol < SE_PROTOCOL_MAX); There are actually other protocols you defined that are not in this list (i.e. I3C). I think it would be best to just die() here. https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/q… PS40, Line 75: /* To maintain Div=4 for QcLib, configure clock to 7372800Hz for sc7180 */ nit: QcLib really shouldn't reconfigure any UART registers to begin with when being called from coreboot. It would be good if we could fix that from the QcLib side. -- To view, visit https://review.coreboot.org/c/coreboot/+/35499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Gerrit-Change-Number: 35499 Gerrit-PatchSet: 40 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-CC: Stephen Boyd <swboyd(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Mar 2020 23:04:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Signed-off-by: mirek190 <mirek190@gmail.com>
by Miroslaw Kocur (Code Review) 02 Mar '20

02 Mar '20

Miroslaw Kocur has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38909 ) Change subject: Signed-off-by: mirek190 <mirek190(a)gmail.com> ...................................................................... Signed-off-by: mirek190 <mirek190(a)gmail.com> Attempt to add a nwe device - etab_pro tablet based on GLK. Change-Id: I63b9129a419facbcd2ca4819ba5946c40d7d5498 --- A configs/config.glk_etab_pro M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/chromeos.fmd M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/octopus/variants/baseboard/gpio.c M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 10 files changed, 601 insertions(+), 364 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/38909/1 diff --git a/configs/config.glk_etab_pro b/configs/config.glk_etab_pro new file mode 100644 index 0000000..558e788 --- /dev/null +++ b/configs/config.glk_etab_pro @@ -0,0 +1,10 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_OCTOPUS=y +CONFIG_NEED_LBP2=y +CONFIG_LBP2_FMAP_NAME="SIGN_CSE" +CONFIG_LBP2_FROM_IFWI=y +CONFIG_NEED_IFWI=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_FMDFILE="src/mainboard/google/octopus/chromeos.fmd" +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/intel/GLK/etabpro/flashregion_1_bios.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/intel/GLK/etabpro/flashregion_0_flashdescriptor.bin" diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 3139716..f613b43 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -2,7 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS def_bool n select SOC_INTEL_GLK - select BOARD_ROMSIZE_KB_16384 + select BOARD_ROMSIZE_KB_8192 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 @@ -17,7 +17,6 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE - select MAINBOARD_HAS_CHROMEOS select SOC_ESPI select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 @@ -26,25 +25,11 @@ if BOARD_GOOGLE_BASEBOARD_OCTOPUS -config CHROMEOS_WIFI_SAR - bool - default y if CHROMEOS - select DSAR_ENABLE - select SAR_ENABLE - select USE_SAR - select GEO_SAR_ENABLE config BASEBOARD_OCTOPUS_LAPTOP def_bool n select SYSTEM_TYPE_LAPTOP -config CHROMEOS - bool - default y - select EC_GOOGLE_CHROMEEC_SWITCHES - select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN - select VBOOT_LID_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/octopus/chromeos.fmd b/src/mainboard/google/octopus/chromeos.fmd index 332465a..0eccc4d 100644 --- a/src/mainboard/google/octopus/chromeos.fmd +++ b/src/mainboard/google/octopus/chromeos.fmd @@ -1,56 +1,23 @@ -FLASH 16M { - WP_RO@0x0 0x400000 { - SI_DESC@0x0 0x1000 - IFWI@0x1000 0x1ff000 - RO_VPD(PRESERVE)@0x200000 0x4000 - RO_SECTION@0x204000 0x1fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - COREBOOT(CBFS)@0x1000 0x1f8000 - GBB@0x1f9000 0x3000 - } - } - MISC_RW@0x400000 0x30000 { - RW_PRESERVE(PRESERVE) { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x1000 +FLASH 8M { + SI_DESC 0x1000 + SI_BIOS { + IFWI 0x2ff000 + OBBP { + FMAP 0x1000 + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + RW_VAR_MRC_CACHE 0x1000 } + CONSOLE 0x20000 + COREBOOT(CBFS) + SIGN_CSE 0x2000 + BIOS_UNUSABLE 0x4000 } - RW_ELOG(PRESERVE)@0x21000 0x3000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x5000 - FPF_STATUS@0x2f000 0x1000 } - RW_SECTION_A@0x430000 0x480000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x46ffc0 - RW_FWID_A@0x47ffc0 0x40 + SI_DEVICEEXT 0x101000 { + DEVICE_EXTENSION 0x100000 + UNUSED_HOLE 0x1000 } - RW_SECTION_B@0x8b0000 0x480000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x46ffc0 - RW_FWID_B@0x47ffc0 0x40 - } - SMMSTORE(PRESERVE)@0xd30000 0x40000 - RW_LEGACY(CBFS)@0xd70000 0x1c0000 - BIOS_UNUSABLE@0xf30000 0x4f000 - DEVICE_EXTENSION@0xf7f000 0x80000 - # Currently, it is required that the BIOS region be a multiple of 8KiB. - # This is required so that the recovery mechanism can find SIGN_CSE - # region aligned to 4K at the center of BIOS region. Since the - # descriptor at the beginning uses 4K and BIOS starts at an offset of - # 4K, a hole of 4K is created towards the end of the flash to compensate - # for the size requirement of BIOS region. - # FIT tool thus creates descriptor with following regions: - # Descriptor --> 0 to 4K - # BIOS --> 4K to 0xf7f000 - # Device ext --> 0xf7f000 to 0xfff000 - UNUSED_HOLE@0xfff000 0x1000 } + diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 8f85070..e132f14 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -110,16 +110,16 @@ device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 off end # - NPK - device pci 02.0 on end # - Gen - device pci 03.0 on end # - Iunit + device pci 02.0 off end # - Gen + device pci 03.0 off end # - Iunit chip drivers/intel/wifi register "wake" = "GPE0A_CNVI_PME_STS" device pci 0c.0 on end # - CNVi end - device pci 0d.0 on end # - P2SB - device pci 0d.1 on end # - PMC - device pci 0d.2 on end # - Fast SPI - device pci 0d.3 on end # - Shared SRAM + device pci 0d.0 off end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 off end # - Fast SPI + device pci 0d.3 off end # - Shared SRAM device pci 0e.0 on chip drivers/generic/max98357a register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" @@ -128,18 +128,18 @@ end end # - Audio device pci 0f.0 on end # - Heci1 - device pci 0f.1 on end # - Heci2 - device pci 0f.2 on end # - Heci3 + device pci 0f.1 off end # - Heci2 + device pci 0f.2 off end # - Heci3 device pci 11.0 off end # - ISH - device pci 12.0 off end # - SATA + device pci 12.0 on end # - SATA device pci 13.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW3_11" device pci 00.0 on end end end # - PCIe-A 0 Onboard M2 Slot(Wifi) - device pci 13.1 off end # - PCIe-A 1 - device pci 13.2 off end # - PCIe-A 2 + device pci 13.1 on end # - PCIe-A 1 + device pci 13.2 on end # - PCIe-A 2 device pci 13.3 off end # - PCIe-A 3 device pci 14.0 off end # - PCIe-B 0 device pci 14.1 off end # - PCIe-B 1 @@ -231,19 +231,19 @@ end end end # - XHCI - device pci 15.1 on end # - XDCI + device pci 15.1 off end # - XDCI device pci 16.0 on end # - I2C 0 - device pci 16.1 off end # - I2C 1 - device pci 16.2 off end # - I2C 2 - device pci 16.3 off end # - I2C 3 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 device pci 17.0 on end # - I2C 4 device pci 17.1 on end # - I2C 5 device pci 17.2 on end # - I2C 6 - device pci 17.3 off end # - I2C 7 + device pci 17.3 on end # - I2C 7 device pci 18.0 on end # - UART 0 - device pci 18.1 off end # - UART 1 + device pci 18.1 on end # - UART 1 device pci 18.2 on end # - UART 2 - device pci 18.3 off end # - UART 3 + device pci 18.3 on end # - UART 3 device pci 19.0 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" @@ -252,11 +252,11 @@ device spi 0 on end end end # - GSPI 0 - device pci 19.1 off end # - SPI 1 + device pci 19.1 on end # - SPI 1 device pci 19.2 on end # - SPI 2 - device pci 1a.0 on end # - PWM + device pci 1a.0 off end # - PWM device pci 1c.0 on end # - eMMC - device pci 1e.0 off end # - SDIO + device pci 1e.0 on end # - SDIO device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 6f68522..ed4892e 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -25,267 +25,225 @@ */ static const struct pad_config gpio_table[] = { /* NORTHWEST COMMUNITY GPIOS */ - PAD_NC(GPIO_0, DN_20K), /* TCK -- debug header NC */ - PAD_NC(GPIO_1, DN_20K), /* TRST_B -- debug header NC */ - PAD_NC(GPIO_2, UP_20K), /* TMS -- debug header NC */ - PAD_NC(GPIO_3, UP_20K), /* TDI -- debug header NC */ - PAD_NC(GPIO_4, UP_20K), /* TDO -- debug header NC */ - PAD_NC(GPIO_5, UP_20K), /* JTAGX -- unused */ - PAD_NC(GPIO_6, UP_20K), /* CX_PREQ_B -- debug header NC */ - PAD_NC(GPIO_7, UP_20K), /* CX_PRDY_B -- debug header NC */ - PAD_NC(GPIO_8, DN_20K), /* TRACE_0_CLK_VNN -- debug header NC */ - PAD_NC(GPIO_9, DN_20K), /* TRACE_0_DATA0_VNN -- debug header NC */ - PAD_NC(GPIO_10, DN_20K), /* TRACE_0_DATA1_VNN -- debug header NC */ - PAD_NC(GPIO_11, DN_20K), /* TRACE_0_DATA2_VNN -- debug header NC */ - PAD_NC(GPIO_12, DN_20K), /* TRACE_0_DATA3_VNN -- debug header NC */ - PAD_NC(GPIO_13, DN_20K), /* TRACE_0_DATA4_VNN -- debug header NC */ - PAD_NC(GPIO_14, DN_20K), /* TRACE_0_DATA5_VNN -- debug header NC */ - PAD_NC(GPIO_15, DN_20K), /* TRACE_0_DATA6_VNN -- debug header NC */ - PAD_NC(GPIO_16, DN_20K), /* TRACE_0_DATA7_VNN -- debug header NC */ - PAD_NC(GPIO_17, UP_20K), /* DBG_PTI_CLK_1 -- debug header NC */ - PAD_NC(GPIO_18, UP_20K), /* DBG_PTI_DATA_8 -- debug header NC */ - PAD_NC(GPIO_19, UP_20K), /* DBG_PTI_DATA_9 -- debug header NC */ - PAD_NC(GPIO_20, UP_20K), /* DBG_PTI_DATA_10 -- debug header NC */ - PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */ - PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ - PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */ - PAD_NC(GPIO_24, UP_20K), /* TRACE_1_DATA6_VNN -- debug header NC */ - PAD_NC(GPIO_25, UP_20K), /* TRACE_1_DATA7_VNN -- debug header NC */ - PAD_NC(GPIO_26, DN_20K), /* TRACE_2_CLK_VNN -- debug header NC */ - PAD_NC(GPIO_27, DN_20K), /* TRACE_2_DATA0_VNN -- debug header NC */ - PAD_NC(GPIO_28, DN_20K), /* TRACE_2_DATA1_VNN 0-- debug header NC */ - PAD_NC(GPIO_29, DN_20K), /* TRACE_2_DATA2_VNN -- debug header NC */ - PAD_NC(GPIO_30, DN_20K), /* TRACE_2_DATA3_VNN -- debug header NC */ - PAD_NC(GPIO_31, DN_20K), /* TRACE_2_DATA4_VNN -- debug header NC */ - PAD_NC(GPIO_32, DN_20K), /* TRACE_2_DATA5_VNN -- debug header NC */ - PAD_NC(GPIO_33, DN_20K), /* TRACE_2_DATA6_VNN -- debug header NC */ - PAD_NC(GPIO_34, DN_20K), /* TRACE_2_DATA7_VNN -- debug header NC */ - PAD_NC(GPIO_35, UP_20K), /* TRACE_3_CLK_VNN -- debug header NC */ - PAD_NC(GPIO_36, UP_20K), /* TRACE_3_DATA0_VNN -- debug header NC */ - PAD_NC(GPIO_37, UP_20K), /* TRACE_3_DATA1_VNN -- debug header NC */ - PAD_NC(GPIO_38, UP_20K), /* TRACE_3_DATA2_VNN -- debug header NC */ - PAD_NC(GPIO_39, UP_20K), /* TRACE_3_DATA3_VNN -- unused */ - PAD_NC(GPIO_40, UP_20K), /* TRACE_3_DATA4_VNN -- unused */ - PAD_NC(GPIO_41, DN_20K), /* TRACE_3_DATA5_VNN -- unused */ - PAD_NC(GPIO_42, DN_20K), /* GP_INTD_DSI_TE1 -- unused */ - PAD_NC(GPIO_43, DN_20K), /* GP_INTD_DSI_TE2 -- debug header NC */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC0_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC1_B */ - PAD_NC(GPIO_46, DN_20K), /* DSI_I2C_SDA -- unused */ - PAD_NC(GPIO_47, DN_20K), /* DSI_I2C_SCL -- unused */ - - /* PMC stays active in suspend so disable standby for these pins */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, NONE, DEEP, NF1), /* PMC_I2C_SDA */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, NONE, DEEP, NF1), /* PMC_I2C_SCL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SCL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SCL */ - PAD_NC(GPIO_54, UP_20K), /* LPSS_I2C2_SDA -- unused */ - PAD_NC(GPIO_55, UP_20K), /* LPSS_I2C2_SCL -- unused */ - PAD_NC(GPIO_56, UP_20K), /* LPSS_I2C3_SDA -- debug header NC */ - PAD_NC(GPIO_57, UP_20K), /* LPSS_I2C2_SCL -- debug header NC */ - PAD_NC(GPIO_58, UP_20K), /* LPSS_I2C4_SDA -- unused */ - PAD_NC(GPIO_59, UP_20K), /* LPSS_I2C4_SCL -- unused */ - PAD_NC(GPIO_60, UP_20K), /* LPSS_UART0_RXD -- debug header NC */ - PAD_NC(GPIO_61, UP_20K), /* LPSS_UART0_TXD -- debug header NC */ - PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ - PAD_NC(GPIO_66, UP_20K), /* UART2-RTS_B -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ - PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */ - PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */ - PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */ - PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */ - PAD_NC(GPIO_72, DN_20K), /* PMC_SPI_TXD -- unused */ - PAD_NC(GPIO_73, DN_20K), /* PMC_SPI_CLK -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PROCHOT_B */ - PAD_NC(GPIO_211, UP_20K), /* EMMC_RST_B -- unused */ - PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* Touch Panel Int */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPI_APIC_IOS(GPIO_214, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* P_SENSOR_INT_L */ - + _PAD_CFG_STRUCT(GPIO_0, 0x44000700, 0x00c01000), // JTAG_TCK + _PAD_CFG_STRUCT(GPIO_1, 0x44000700, 0x00c01000), // JTAG_TRST_N + _PAD_CFG_STRUCT(GPIO_2, 0x44000700, 0x00c03000), // JTAG_TMS + _PAD_CFG_STRUCT(GPIO_3, 0x44000700, 0x00c03000), // JTAG_TDI + _PAD_CFG_STRUCT(GPIO_4, 0x44000700, 0x00c03000), // JTAG_TDO + _PAD_CFG_STRUCT(GPIO_5, 0x44000300, 0x00c3c000), // GPIO + _PAD_CFG_STRUCT(GPIO_6, 0x44000402, 0x00c3f300), // JTAG_PREQ_N + _PAD_CFG_STRUCT(GPIO_7, 0x44000402, 0x00c3f300), // JTAG_PRDY_N + _PAD_CFG_STRUCT(GPIO_8, 0x04000300, 0x0003c032), // GPIO + _PAD_CFG_STRUCT(GPIO_9, 0x04000300, 0x0003c033), // GPIO + _PAD_CFG_STRUCT(GPIO_10, 0x04000300, 0x0003c034), // GPIO + _PAD_CFG_STRUCT(GPIO_11, 0x04000300, 0x0003c035), // GPIO + _PAD_CFG_STRUCT(GPIO_12, 0x04000300, 0x0003c036), // GPIO + _PAD_CFG_STRUCT(GPIO_13, 0x44000300, 0x0003c037), // GPIO + _PAD_CFG_STRUCT(GPIO_14, 0x44000300, 0x0003c038), // GPIO + _PAD_CFG_STRUCT(GPIO_15, 0x44000300, 0x0003c039), // GPIO + _PAD_CFG_STRUCT(GPIO_16, 0x44000300, 0x0003c03a), // GPIO + _PAD_CFG_STRUCT(GPIO_17, 0x44000300, 0x0003c03b), // GPIO + _PAD_CFG_STRUCT(GPIO_18, 0x44000300, 0x0003c03c), // GPIO + _PAD_CFG_STRUCT(GPIO_19, 0x42100102, 0x0002733d), // GPIO + _PAD_CFG_STRUCT(GPIO_20, 0x44000300, 0x0003c03e), // GPIO + _PAD_CFG_STRUCT(GPIO_21, 0x44000802, 0x0000303f), // CNV_MFUART2_RXD + _PAD_CFG_STRUCT(GPIO_22, 0x44000800, 0x00027040), // CNV_MFUART2_TXD + _PAD_CFG_STRUCT(GPIO_23, 0x44000802, 0x00003041), // CNV_GNSS_PA_BLANKING + _PAD_CFG_STRUCT(GPIO_24, 0x44000300, 0x0003c042), // GPIO + _PAD_CFG_STRUCT(GPIO_25, 0x44000300, 0x0003c043), // GPIO + _PAD_CFG_STRUCT(GPIO_26, 0x42800102, 0x00027044), // GPIO + _PAD_CFG_STRUCT(GPIO_27, 0x44000201, 0x00003045), // GPIO + _PAD_CFG_STRUCT(GPIO_28, 0x44000201, 0x00003246), // GPIO + _PAD_CFG_STRUCT(GPIO_29, 0x44000102, 0x00023147), // GPIO + _PAD_CFG_STRUCT(GPIO_30, 0x40900102, 0x0003f048), // GPIO + _PAD_CFG_STRUCT(GPIO_31, 0x40800100, 0x0003f049), // GPIO + _PAD_CFG_STRUCT(GPIO_32, 0x44000100, 0x0003d24a), // GPIO + _PAD_CFG_STRUCT(GPIO_33, 0x40900102, 0x0003f04b), // GPIO + _PAD_CFG_STRUCT(GPIO_34, 0x44000201, 0x0003f34c), // GPIO + _PAD_CFG_STRUCT(GPIO_35, 0x44000201, 0x0003f34d), // GPIO + _PAD_CFG_STRUCT(GPIO_36, 0x44000300, 0x0003c34e), // GPIO + _PAD_CFG_STRUCT(GPIO_37, 0x44000300, 0x0003c04f), // GPIO + _PAD_CFG_STRUCT(GPIO_38, 0x42880102, 0x0003f350), // GPIO + _PAD_CFG_STRUCT(GPIO_39, 0x44000201, 0x0003f351), // GPIO + _PAD_CFG_STRUCT(GPIO_40, 0x44000201, 0x0003f352), // GPIO + _PAD_CFG_STRUCT(GPIO_41, 0x44000300, 0x0003c053), // GPIO + _PAD_CFG_STRUCT(GPIO_42, 0x44000700, 0x00001054), // MDSI_A_TE + _PAD_CFG_STRUCT(GPIO_43, 0x44000702, 0x00001055), // MDSI_C_TE + _PAD_CFG_STRUCT(GPIO_44, 0x44000402, 0x00003356), // USB2_OC0_N + _PAD_CFG_STRUCT(GPIO_45, 0x44000402, 0x00003357), // USB2_OC1_N + _PAD_CFG_STRUCT(GPIO_46, 0x44000300, 0x0003c058), // GPIO + _PAD_CFG_STRUCT(GPIO_47, 0x44000300, 0x0003c059), // GPIO + _PAD_CFG_STRUCT(GPIO_48, 0x44000402, 0x0003e75a), // PMC_I2C_SDA + _PAD_CFG_STRUCT(GPIO_49, 0x44000402, 0x0003e75b), // PMC_I2C_SCL + _PAD_CFG_STRUCT(GPIO_50, 0x44000402, 0x0002275c), // SIO_I2C0_SDA + _PAD_CFG_STRUCT(GPIO_51, 0x44000402, 0x0002275d), // SIO_I2C0_SCL + _PAD_CFG_STRUCT(GPIO_52, 0x44000300, 0x0003c05e), // GPIO + _PAD_CFG_STRUCT(GPIO_53, 0x44000300, 0x0003c05f), // GPIO + _PAD_CFG_STRUCT(GPIO_54, 0x44000300, 0x0003c060), // GPIO + _PAD_CFG_STRUCT(GPIO_55, 0x44000300, 0x0003c061), // GPIO + _PAD_CFG_STRUCT(GPIO_56, 0x44000300, 0x0003c062), // GPIO + _PAD_CFG_STRUCT(GPIO_57, 0x44000300, 0x0003c063), // GPIO + _PAD_CFG_STRUCT(GPIO_58, 0x44000402, 0x00022764), // SIO_I2C4_SDA + _PAD_CFG_STRUCT(GPIO_59, 0x44000402, 0x00022765), // SIO_I2C4_SCL + _PAD_CFG_STRUCT(GPIO_60, 0x44000300, 0x0003c066), // GPIO + _PAD_CFG_STRUCT(GPIO_61, 0x44000300, 0x00003067), // GPIO + _PAD_CFG_STRUCT(GPIO_62, 0x46880100, 0x0003c068), // GPIO + _PAD_CFG_STRUCT(GPIO_63, 0x44000300, 0x0003c069), // GPIO + _PAD_CFG_STRUCT(GPIO_64, 0x44000402, 0x0002336a), // SIO_UART2_RXD + _PAD_CFG_STRUCT(GPIO_65, 0x44000400, 0x0002336b), // SIO_UART2_TXD + _PAD_CFG_STRUCT(GPIO_66, 0x44000201, 0x0000336c), // GPIO + _PAD_CFG_STRUCT(GPIO_67, 0x44840102, 0x0002036d), // GPIO + _PAD_CFG_STRUCT(GPIO_68, 0x44000300, 0x0003c06e), // GPIO + _PAD_CFG_STRUCT(GPIO_69, 0x44000300, 0x0003c06f), // GPIO + _PAD_CFG_STRUCT(GPIO_70, 0x44000300, 0x0003c070), // GPIO + _PAD_CFG_STRUCT(GPIO_71, 0x44000300, 0x0003c071), // GPIO + _PAD_CFG_STRUCT(GPIO_72, 0x44000300, 0x0003c072), // GPIO + _PAD_CFG_STRUCT(GPIO_73, 0x44000201, 0x0003f373), // GPIO + _PAD_CFG_STRUCT(GPIO_74, 0x44000400, 0x0003f300), // THERMTRIP_N + _PAD_CFG_STRUCT(GPIO_75, 0x44000702, 0x00003000), // PROCHOT_N +// _PAD_CFG_STRUCT(GPIO_211, 0xffffffff, 0xffffffff), RESERVED + _PAD_CFG_STRUCT(GPIO_212, 0x44000102, 0x0001f375), // GPIO + _PAD_CFG_STRUCT(GPIO_213, 0x44000102, 0x0001d376), // GPIO + _PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x0001d377), // GPIO /* NORTH COMMUNITY GPIOS */ - - /* svid - unused */ - PAD_NC(GPIO_76, UP_20K),/* SVID Alert - unused */ - PAD_NC(GPIO_77, UP_20K),/* SVID Data - unused */ - PAD_NC(GPIO_78, UP_20K),/* SVID Clk - unused */ - - /* LPSS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_79, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* H1_SLAVE_SPI_CLK_R */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_80, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* H1_SLAVE_SPI_CS_L_R */ - PAD_NC(GPIO_81, DN_20K), /* GPIO_81_DEBUG -- debug header NC */ - PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */ - PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ - PAD_NC(GPIO_84, DN_20K), /* LPSS_SPI_2_CLK - unused */ - PAD_NC(GPIO_85, DN_20K), /* LPSS_SPI_2_FS0 - unused */ - PAD_NC(GPIO_86, DN_20K), /* LPSS_SPI_2_FS1 - unused */ - PAD_NC(GPIO_87, DN_20K), /* LPSS_SPI_2_FS2 - unused */ - PAD_NC(GPIO_88, DN_20K), /* LPSS_SPI_2_RXD - unused */ - PAD_NC(GPIO_89, DN_20K), /* LPSS_SPI_2_TXD - unused */ - - /* Fast SPI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN_R */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ - PAD_NC(GPIO_94, NATIVE),/* FST_SPI_IO2 - unused */ - PAD_NC(GPIO_95, NATIVE),/* FST_SPI_IO3 - unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ - - /* PMU Signals */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_98, NONE, DEEP, NF1),/* PMU_PLTRST_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */ - PAD_NC(GPIO_104, UP_20K),/* EMMC_DNX_PWR_EN_B - unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */ - PAD_NC(GPIO_108, NONE),/* PMU_SUSCLK -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD),/* SUS_STAT_B -- BT_DISABLE_L */ - - /* I2C5 - Audio */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SCL */ - - /* I2C6 - Trackpad */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SCL */ - - /* I2C7 - Touchscreen */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SCL */ - - /* PCIE_WAKE[0:3]_B */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ - PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ - PAD_NC(GPIO_118, UP_20K),/* PCIE_WAKE2_B -- unused */ - PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */ - - /* - * PCIE_CLKREQ[0:3]_B. For unused pins, follow the termination - * guideline for unused PCIE ports as described in PDG i.e. keep - * the pins in native mode and deploy the internal pull up. - */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ1_B -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ2_B -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ - - /* DDI[0:1] SDA and SCL -- unused */ - PAD_NC(GPIO_124, UP_20K),/* HV_DDI0_DDC_SDA -- unused */ - PAD_NC(GPIO_125, UP_20K),/* HV_DDI0_DDC_SCL -- unused */ - PAD_NC(GPIO_126, UP_20K),/* HV_DDI1_DDC_SDA -- unused */ - PAD_NC(GPIO_127, UP_20K),/* HV_DDI1_DDC_SCL -- unused */ - - /* Panel 0 control */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_VDDEN*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTEN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTCTL */ - - /* Hot plug detect. */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI0_HPD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_HPD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_EDP_HPD */ - - /* EC_AP_INT_ODL */ - PAD_CFG_GPI_APIC_LOW(GPIO_134, NONE, DEEP), - - PAD_CFG_GPI_IRQ_WAKE(GPIO_135, NONE, DEEP, LEVEL, INVERT),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ - // Also we may be able to use eSPI WAKE# Virtual Wire instead - PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ - PAD_NC(GPIO_142, UP_20K),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL(unused) */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_143, 1, DEEP, UP_20K, HIZCRx1, ENPU),/* GPIO_143 -- LTE_SAR_ODL */ - - /* GPIO_144 -- PEN_EJECT(wake) */ - PAD_CFG_GPI_SCI_HIGH_DEBEN(GPIO_144, UP_20K, DEEP, EDGE_SINGLE, - DEBOUNCE_256_RTC), - /* GPIO_145 -- PEN_EJECT(notifications) */ - PAD_CFG_GPI_GPIO_DRIVER(GPIO_145, UP_20K, DEEP), - PAD_NC(GPIO_146, UP_20K),/* GPIO_146 -- unused */ - - /* - * GPIO_154 - LPC_CLKRUN# has a native function for LPC but not for - * eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO - * and kept unconnected to allow S0ix entry. - */ - - /* AUDIO COMMUNITY GPIOS*/ - PAD_NC(GPIO_156, DN_20K), /* AVS_I2S0_MCLK -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_BCLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_WS_SYNC */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_SDI */ - PAD_NC(GPIO_160, DN_20K), /* AVS_I2S0_SDO -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */ - PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SDI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SD0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S1_MCLK */ - - /* Disable standby for GPIO_171 and GPIO_173 to support Wake on Voice */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_171, DN_20K, DEEP, NF1), /* AVS_M_CLK_A1 -- DMIC_CLK1 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_173, DN_20K, DEEP, NF1), /* AVS_M_DATA_1 -- DMIC_DATA */ - PAD_NC(GPIO_174, DN_20K), /* AVS_M_CLK_AB2 -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */ - - /* SCC COMMUNITY GPIOS */ - PAD_NC(GPIO_176, UP_20K), /* SMB_ALERTB -- unused */ - PAD_NC(GPIO_177, UP_20K), /* SMB_CLK -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_WLAN_L */ - - PAD_NC(GPIO_179, NONE), /* SDCARD_CLK -- unused */ - PAD_NC(GPIO_180, NONE), /* SDCARD_CMD -- unused */ - PAD_NC(GPIO_181, UP_20K), /* SDCARD_D0 -- unused */ - PAD_NC(GPIO_182, UP_20K), /* SDCARD_D1 -- unused */ - PAD_NC(GPIO_183, UP_20K), /* SDCARD_D2 -- unused */ - PAD_NC(GPIO_184, UP_20K), /* SDCARD_D3 -- unused */ - PAD_NC(GPIO_185, UP_20K), /* SDCARD_CMD -- unused */ - PAD_NC(GPIO_186, UP_20K), /* SDCARD_CD_N -- unused */ - PAD_NC(GPIO_187, NONE), /* SDCARD_LVL_WP -- unused */ - PAD_NC(GPIO_188, UP_20K), /* SDCARD_PWR_DWN_N -- unused */ - PAD_CFG_GPI(GPIO_189, NONE, DEEP), /* EC_IN_RW */ - PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ - - /* - * Disable standby state for these CNVI pins to allow wake on - * WiFI & Bluetooth. - */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNV_RGI_DT */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* CNV_RF_RESET_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D1 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D2 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D3 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D4 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D5 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D6 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D7 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_CMD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ - PAD_NC(GPIO_210, DN_20K), -}; + _PAD_CFG_STRUCT(GPIO_76, 0x44000400, 0x0003c000), // SVID0_ALERT_N + _PAD_CFG_STRUCT(GPIO_77, 0x44000400, 0x0003c000), // SVID0_DATA + _PAD_CFG_STRUCT(GPIO_78, 0x44000400, 0x0003c000), // SVID0_CLK + _PAD_CFG_STRUCT(GPIO_79, 0x44000400, 0x0003d232), // SIO_SPI_0_CLK + _PAD_CFG_STRUCT(GPIO_80, 0x44000400, 0x0003d233), // SIO_SPI_0_FS0 + _PAD_CFG_STRUCT(GPIO_81, 0x44000c02, 0x0003d034), // FST_SPI_CS2_N + _PAD_CFG_STRUCT(GPIO_82, 0x44000400, 0x0003d235), // SIO_SPI_0_RXD + _PAD_CFG_STRUCT(GPIO_83, 0x44000400, 0x0003d236), // SIO_SPI_0_TXD + _PAD_CFG_STRUCT(GPIO_84, 0x44000100, 0x00001037), // GPIO + _PAD_CFG_STRUCT(GPIO_85, 0x44000300, 0x00001038), // GPIO + _PAD_CFG_STRUCT(GPIO_86, 0x44000300, 0x00001039), // GPIO + _PAD_CFG_STRUCT(GPIO_87, 0x44000300, 0x0003c03a), // GPIO + _PAD_CFG_STRUCT(GPIO_88, 0x44000300, 0x0003c03b), // GPIO + _PAD_CFG_STRUCT(GPIO_89, 0x44000300, 0x0003c03c), // GPIO + _PAD_CFG_STRUCT(GPIO_90, 0x44000502, 0x00003c3d), // FST_SPI_CS0_N + _PAD_CFG_STRUCT(GPIO_91, 0x44000300, 0x0003fc3e), // GPIO + _PAD_CFG_STRUCT(GPIO_92, 0x44000500, 0x00003c3f), // FST_SPI_MOSI_IO + _PAD_CFG_STRUCT(GPIO_93, 0x44000502, 0x00003c40), // FST_SPI_MISO_IO + _PAD_CFG_STRUCT(GPIO_94, 0x44000502, 0x00003c41), // FST_SPI_IO2 + _PAD_CFG_STRUCT(GPIO_95, 0x44000502, 0x00003c42), // FST_SPI_IO3 + _PAD_CFG_STRUCT(GPIO_96, 0x44000500, 0x00003c43), // FST_SPI_CLK + _PAD_CFG_STRUCT(GPIO_97, 0x44000500, 0x00003c00), // FST_SPI_CLK_FB + _PAD_CFG_STRUCT(GPIO_98, 0x44000400, 0x0003c000), // PMU_PLTRST_N + _PAD_CFG_STRUCT(GPIO_99, 0x44000402, 0x0003f300), // PMU_PWRBTN_N + _PAD_CFG_STRUCT(GPIO_100, 0x44000400, 0x0003c000), // PMU_SLP_S0_N + _PAD_CFG_STRUCT(GPIO_101, 0x44000400, 0x0003c000), // PMU_SLP_S3_N + _PAD_CFG_STRUCT(GPIO_102, 0x44000400, 0x0003c000), // PMU_SLP_S4_N + _PAD_CFG_STRUCT(GPIO_103, 0x44000400, 0x0003c000), // SUSPWRDNACK + _PAD_CFG_STRUCT(GPIO_104, 0x44000700, 0x00003000), // EMMC_PWR_EN_N + _PAD_CFG_STRUCT(GPIO_105, 0x44000300, 0x0003c344), // GPIO + _PAD_CFG_STRUCT(GPIO_106, 0x44000402, 0x0003f300), // PMU_BATLOW_N + _PAD_CFG_STRUCT(GPIO_107, 0x44000400, 0x0003f300), // PMU_RSTBTN_N + _PAD_CFG_STRUCT(GPIO_108, 0x44000400, 0x0003c000), // PMU_SUSCLK + _PAD_CFG_STRUCT(GPIO_109, 0x44000400, 0x0003c000), // SUS_STAT_N + _PAD_CFG_STRUCT(GPIO_110, 0x44000402, 0x0003e745), // SIO_I2C5_SDA + _PAD_CFG_STRUCT(GPIO_111, 0x44000402, 0x0003e746), // SIO_I2C5_SCL + _PAD_CFG_STRUCT(GPIO_112, 0x44000300, 0x0003c047), // GPIO + _PAD_CFG_STRUCT(GPIO_113, 0x44000300, 0x0003c048), // GPIO + _PAD_CFG_STRUCT(GPIO_114, 0x44000402, 0x00022749), // SIO_I2C7_SDA + _PAD_CFG_STRUCT(GPIO_115, 0x44000402, 0x0002274a), // SIO_I2C7_SCL + _PAD_CFG_STRUCT(GPIO_116, 0x44000402, 0x0003f34b), // PCIE_WAKE0_N + _PAD_CFG_STRUCT(GPIO_117, 0x44000402, 0x0003f34c), // PCIE_WAKE1_N + _PAD_CFG_STRUCT(GPIO_118, 0x44000402, 0x0003f34d), // PCIE_WAKE2_N + _PAD_CFG_STRUCT(GPIO_119, 0x44000300, 0x0003c04e), // GPIO + _PAD_CFG_STRUCT(GPIO_120, 0x44000402, 0x0002334f), // PCIE_CLKREQ0_N + _PAD_CFG_STRUCT(GPIO_121, 0x44000402, 0x00023350), // PCIE_CLKREQ1_N + _PAD_CFG_STRUCT(GPIO_122, 0x44000400, 0x00023351), // PCIE_CLKREQ2_N + _PAD_CFG_STRUCT(GPIO_123, 0x44000300, 0x00020352), // GPIO + _PAD_CFG_STRUCT(GPIO_124, 0x44000402, 0x0001c353), // DDI0_DDC_SDA + _PAD_CFG_STRUCT(GPIO_125, 0x44000402, 0x0001c354), // DDI0_DDC_SCL + _PAD_CFG_STRUCT(GPIO_126, 0x44000300, 0x0003c055), // GPIO + _PAD_CFG_STRUCT(GPIO_127, 0x44000300, 0x0003c056), // GPIO + _PAD_CFG_STRUCT(GPIO_128, 0x44000400, 0x00005257), // PNL0_VDDEN + _PAD_CFG_STRUCT(GPIO_129, 0x44000400, 0x00005258), // PNL0_BKLTEN + _PAD_CFG_STRUCT(GPIO_130, 0x44000400, 0x00005259), // PNL0_BKLCTL + _PAD_CFG_STRUCT(GPIO_131, 0x44000402, 0x0002735a), // DDI0_HPD + _PAD_CFG_STRUCT(GPIO_132, 0x44000402, 0x0002735b), // DDI1_HPD + _PAD_CFG_STRUCT(GPIO_133, 0x44000400, 0x0002435c), // DDI2_HPD + _PAD_CFG_STRUCT(GPIO_134, 0x44000201, 0x0003f35d), // GPIO + _PAD_CFG_STRUCT(GPIO_135, 0x44000201, 0x0000325e), // GPIO + _PAD_CFG_STRUCT(GPIO_136, 0x44000300, 0x0003c05f), // GPIO + _PAD_CFG_STRUCT(GPIO_137, 0x44000300, 0x0003c060), // GPIO + _PAD_CFG_STRUCT(GPIO_138, 0x44000102, 0x00000061), // GPIO + _PAD_CFG_STRUCT(GPIO_139, 0x44000300, 0x0003c062), // GPIO + _PAD_CFG_STRUCT(GPIO_140, 0x44000100, 0x00001063), // GPIO + _PAD_CFG_STRUCT(GPIO_141, 0x44001400, 0x00020364), // SATA_DEVSLP1 + _PAD_CFG_STRUCT(GPIO_142, 0x44900102, 0x00023365), // GPIO + _PAD_CFG_STRUCT(GPIO_143, 0x44900102, 0x00020066), // GPIO + _PAD_CFG_STRUCT(GPIO_144, 0x44000201, 0x00001067), // GPIO + _PAD_CFG_STRUCT(GPIO_145, 0x44000201, 0x00001068), // GPIO + _PAD_CFG_STRUCT(GPIO_146, 0x44001400, 0x00001069), // n/a + _PAD_CFG_STRUCT(GPIO_147, 0x44000702, 0x0000336a), // LPC_SERIRQ + _PAD_CFG_STRUCT(GPIO_148, 0x44000700, 0x0002006b), // LPC_CLKOUT0 + _PAD_CFG_STRUCT(GPIO_149, 0x44000700, 0x0002006c), // LPC_CLKOUT1 + _PAD_CFG_STRUCT(GPIO_150, 0x44000702, 0x0002336d), // LPC_AD0 + _PAD_CFG_STRUCT(GPIO_151, 0x44000702, 0x0002336e), // LPC_AD1 + _PAD_CFG_STRUCT(GPIO_152, 0x44000702, 0x0002336f), // LPC_AD2 + _PAD_CFG_STRUCT(GPIO_153, 0x44000702, 0x00023370), // LPC_AD3 + _PAD_CFG_STRUCT(GPIO_154, 0x44000702, 0x00003071), // LPC_CLKRUN_N + _PAD_CFG_STRUCT(GPIO_155, 0x44000700, 0x00023372), // LPC_FRAME_N + /* Group Audio GPIOS */ + _PAD_CFG_STRUCT(GPIO_156, 0x42000100, 0x0003d200), // GPIO + _PAD_CFG_STRUCT(GPIO_157, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_158, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_159, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_160, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_161, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_162, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_163, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_164, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_165, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_166, 0x44000400, 0x00021200), // AVS_HDA_BCLK + _PAD_CFG_STRUCT(GPIO_167, 0x44000400, 0x00021200), // AVS_HDA_WS_SYNC + _PAD_CFG_STRUCT(GPIO_168, 0x44000400, 0x00020000), // AVS_HDA_SDI + _PAD_CFG_STRUCT(GPIO_169, 0x44000400, 0x00021200), // AVS_HDA_SDO + _PAD_CFG_STRUCT(GPIO_170, 0x44000402, 0x00021200), // AVS_HDA_RST_N + _PAD_CFG_STRUCT(GPIO_171, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_172, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_173, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_174, 0x44000201, 0x00003300), // GPIO + _PAD_CFG_STRUCT(GPIO_175, 0x44000100, 0x00001000), // GPIO + /* Group SCC GPIOS */ + _PAD_CFG_STRUCT(GPIO_176, 0x40800102, 0x0003f000), // GPIO + _PAD_CFG_STRUCT(GPIO_177, 0x44000102, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_178, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_187, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_179, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_180, 0x44000400, 0x00001200), // SDCARD_CLK_FB + _PAD_CFG_STRUCT(GPIO_181, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_182, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_183, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_184, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_185, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_186, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_188, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_210, 0x44000200, 0x0001f200), // GPIO + _PAD_CFG_STRUCT(GPIO_189, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_190, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_191, 0x44000400, 0x0003c000), // CNV_BRI_DT + _PAD_CFG_STRUCT(GPIO_192, 0x44000402, 0x0003f300), // CNV_BRI_RST + _PAD_CFG_STRUCT(GPIO_193, 0x44000400, 0x0003c000), // CNV_RGI_DT + _PAD_CFG_STRUCT(GPIO_194, 0x44000400, 0x0003f300), // CNV_RGI_RST + _PAD_CFG_STRUCT(GPIO_195, 0x44000400, 0x0003c000), // CNV_RF_RESET_N + _PAD_CFG_STRUCT(GPIO_196, 0x44000400, 0x0003c000), // XTAL_CLKREQ + _PAD_CFG_STRUCT(GPIO_197, 0x44000b00, 0x00001200), // n/a + _PAD_CFG_STRUCT(GPIO_198, 0x44000400, 0x0001d200), // EMMC_CLK + _PAD_CFG_STRUCT(GPIO_199, 0x44000500, 0x00001200), // EMMC_D0 + _PAD_CFG_STRUCT(GPIO_200, 0x44000402, 0x00023300), // EMMC_D1 + _PAD_CFG_STRUCT(GPIO_201, 0x44000402, 0x00023300), // EMMC_D2 + _PAD_CFG_STRUCT(GPIO_202, 0x44000402, 0x00023300), // EMMC_D3 + _PAD_CFG_STRUCT(GPIO_203, 0x44000402, 0x00023300), // EMMC_D4 + _PAD_CFG_STRUCT(GPIO_204, 0x44000402, 0x00023300), // EMMC_D5 + _PAD_CFG_STRUCT(GPIO_205, 0x44000402, 0x00023300), // EMMC_D6 + _PAD_CFG_STRUCT(GPIO_206, 0x44000402, 0x00023300), // EMMC_D7 + _PAD_CFG_STRUCT(GPIO_207, 0x44000402, 0x00023300), // EMMC_CMD + _PAD_CFG_STRUCT(GPIO_208, 0x44000402, 0x00023300), // EMMC_RCLK + _PAD_CFG_STRUCT(GPIO_209, 0x44000400, 0x0001d200), // EMMC_RST_N} +; const struct pad_config *__weak variant_base_gpio_table(size_t *num) { @@ -307,43 +265,41 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { - PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ + _PAD_CFG_STRUCT(GPIO_190, 0x44000300, 0x0003c000), /* PCH_WP_OD */ /* GSPI0_INT */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, - DISPUPD), /* H1_PCH_INT_ODL */ + _PAD_CFG_STRUCT(GPIO_63, 0x44000300, 0x0003c069), /* H1_PCH_INT_ODL */ /* GSPI0_CLK */ - PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ + _PAD_CFG_STRUCT(GPIO_79, 0x44000400, 0x0003d232), /* H1_SLAVE_SPI_CLK_R */ /* GSPI0_CS# */ - PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */ + _PAD_CFG_STRUCT(GPIO_80, 0x44000400, 0x0003d233), /* H1_SLAVE_SPI_CS_L_R */ /* GSPI0_MISO */ - PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */ + _PAD_CFG_STRUCT(GPIO_82, 0x44000400, 0x0003d235), /* H1_SLAVE_SPI_MISO */ /* GSPI0_MOSI */ - PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ + _PAD_CFG_STRUCT(GPIO_83, 0x44000400, 0x0003d236), /* H1_SLAVE_SPI_MOSI_R */ /* Enable power to wifi early in bootblock and de-assert PERST#. */ - PAD_CFG_GPO(GPIO_178, 0, DEEP), /* EN_PP3300_WLAN_L */ - PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ + _PAD_CFG_STRUCT(GPIO_178, 0x44000300, 0x0003c000), /* EN_PP3300_WLAN_L */ + _PAD_CFG_STRUCT(GPIO_164, 0x44000100, 0x00001000), /* WLAN_PE_RST */ /* * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak * pull-up for proper operation. Since there is no external pull present * on this platform, configure an internal weak pull-up. */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, - ENPU), /* ESPI_IO1 */ + _PAD_CFG_STRUCT(GPIO_151, 0x44000702, 0x0002336e), /* ESPI_IO1 */ /* GPIO_67 and GPIO_117 are in early_gpio_table and gpio_table. For variants * having LTE SKUs, these two GPIOs would be overridden to output high first * in the bootblock then be set to default state in gpio_table for non-LTE * SKUs and keep to output high for LTE SKUs in ramstage. */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ - PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ + _PAD_CFG_STRUCT(GPIO_67, 0x44840102, 0x0002036d), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + _PAD_CFG_STRUCT(GPIO_117, 0x44000402, 0x0003f34c),/* PCIE_WAKE1_B -- LTE_WAKE_L */ /* GPIO_161 is in early_gpio_table and gpio_table because LTE SKU needs * to override this pin to output low then high respectively in two * stages. */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ + _PAD_CFG_STRUCT(GPIO_161, 0x44000100, 0x00001000), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ }; const struct pad_config *__weak @@ -360,7 +316,7 @@ /* GPIO settings before entering slp_s5. */ static const struct pad_config sleep_s5_gpio_table[] = { /* BT_DISABLE_L */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 0, DEEP, NONE, Tx0RxDCRx1, SAME), + _PAD_CFG_STRUCT(GPIO_109, 0x44000400, 0x0003c000), }; const struct pad_config *__weak diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index efeab56..07d5129 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1036,6 +1036,7 @@ case PCI_DEVICE_ID_INTEL_HM170: case PCI_DEVICE_ID_INTEL_CM236: case PCI_DEVICE_ID_INTEL_APL_LPC: + case PCI_DEVICE_ID_INTEL_GLK: case PCI_DEVICE_ID_INTEL_DNV_LPC: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 321cf97..cc1d99e 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -45,6 +45,310 @@ * (if it's the first column, GPIO is the default, no matter the name) */ +static const char *const glk_group_northwest_names[] = { + "GPIO_0", "JTAG_TCK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_1", "JTAG_TRST_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_2", "JTAG_TMS", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_3", "JTAG_TDI", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_4", "JTAG_TDO", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_5", "JTAGX", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_6", "JTAG_PREQ_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_7", "JTAG_PRDY_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_8", "n/a", "n/a", "CNV_DEBUG_09", "CNV_DEBUG_00", "n/a", "n/a", + "GPIO_9", "n/a", "n/a", "CNV_DEBUG_10", "CNV_DEBUG_01", "n/a", "n/a", + "GPIO_10", "n/a", "n/a", "CNV_DEBUG_11", "CNV_DEBUG_02", "n/a", "n/a", + "GPIO_11", "n/a", "n/a", "CNV_DEBUG_12", "CNV_DEBUG_03", "n/a", "n/a", + "GPIO_12", "n/a", "n/a", "CNV_DEBUG_13", "CNV_DEBUG_04", "n/a", "n/a", + "GPIO_13", "n/a", "n/a", "CNV_DEBUG_14", "CNV_DEBUG_05", "n/a", "n/a", + "GPIO_14", "n/a", "n/a", "CNV_DEBUG_15", "CNV_DEBUG_06", "n/a", "n/a", + "GPIO_15", "n/a", "n/a", "CNV_DEBUG_16", "CNV_DEBUG_07", "n/a", "n/a", + "GPIO_16", "n/a", "n/a", "CNV_DEBUG_17", "CNV_DEBUG_08", "n/a", "n/a", + "GPIO_17", "n/a", "CNV_MFUART0_RXD", "CNV_DEBUG_00", "n/a", "n/a", "n/a", + "GPIO_18", "n/a", "CNV_MFUART0_TXD", "CNV_DEBUG_01", "n/a", "n/a", "n/a", + "GPIO_19", "n/a", "CNV_MFUART0_RTS_N", "CNV_DEBUG_02", "n/a", "n/a", "n/a", + "GPIO_20", "n/a", "CNV_MFUART0_CTS_N", "CNV_DEBUG_03", "n/a", "n/a", "n/a", + "GPIO_21", "n/a", "CNV_MFUART2_RXD", "CNV_DEBUG_04", "n/a", "n/a", "n/a", + "GPIO_22", "n/a", "CNV_MFUART2_TXD", "CNV_DEBUG_05", "n/a", "n/a", "n/a", + "GPIO_23", "n/a", "CNV_GNSS_PA_BLANKING", "CNV_DEBUG_06", "PMIC_STDBY", "n/a", "n/a", + "GPIO_24", "n/a", "CNV_GNSS_FTA", "CNV_DEBUG_07", "PMIC_PWRGOOD", "n/a", "n/a", + "GPIO_25", "n/a", "CNV_GNSS_SYSCK", "CNV_DEBUG_08", "PMIC_RESET_N", "n/a", "n/a", + "GPIO_26", "n/a", "SIO_UART1_RXD", "ISH_UART1_RXD", "CNV_BT_UART_RXD", "n/a", "n/a", + "GPIO_27", "n/a", "SIO_UART1_TXD", "ISH_UART1_TXD", "CNV_BT_UART_TXD", "n/a", "n/a", + "GPIO_28", "n/a", "SIO_UART1_RTS_N", "ISH_UART1_RTS_N", "CNV_BT_UART_RTS_N", "n/a", "n/a", + "GPIO_29", "n/a", "SIO_UART1_CTS_N", "ISH_UART1_CTS_N", "CNV_BT_UART_CTS_N", "n/a", "n/a", + "GPIO_30", "n/a", "SATA_GP0", "n/a", "n/a", "n/a", "n/a", + "GPIO_31", "n/a", "SATA_GP1", "n/a", "n/a", "n/a", "n/a", + "GPIO_32", "n/a", "SATA_DE_VSLP0", "n/a", "n/a", "n/a", "n/a", + "GPIO_33", "n/a", "SATA_DE_VSLP1", "SUSCLK1", "n/a", "n/a", "n/a", + "GPIO_34", "n/a", "SATA_LEDN", "SUSCLK2", "n/a", "n/a", "n/a", + "GPIO_35", "n/a", "n/a", "n/a", "SPKR", "n/a", "BSSB_CLK", + "GPIO_36", "n/a", "n/a", "CNV_BTEN", "n/a", "n/a", "BSSB_DI", + "GPIO_37", "n/a", "n/a", "CNV_GNEN", "n/a", "n/a", "n/a", + "GPIO_38", "n/a", "n/a", "CNV_WFEN", "n/a", "n/a", "n/a", + "GPIO_39", "n/a", "n/a", "CNV_WCEN", "n/a", "n/a", "n/a", + "GPIO_40", "n/a", "n/a", "CNVBT_HOST_WAKE_N", "n/a", "n/a", "n/a", + "GPIO_41", "n/a", "n/a", "CNV_GNSS_HOST_WAKE_N", "n/a", "n/a", "n/a", + "GPIO_42", "MDSI_A_TE", "PWM0", "n/a", "n/a", "n/a", "n/a", + "GPIO_43", "MDSI_C_TE", "PWM1", "n/a", "n/a", "n/a", "n/a", + "GPIO_44", "USB2_OC0_N", "PWM2", "n/a", "n/a", "n/a", "n/a", + "GPIO_45", "USB2_OC1_N", "PWM3", "n/a", "n/a", "n/a", "n/a", + "GPIO_46", "MIPI_I2C_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_47", "MIPI_I2C_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_48", "PMC_I2C_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_49", "PMC_I2C_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_50", "SIO_I2C0_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_51", "SIO_I2C0_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_52", "SIO_I2C1_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_53", "SIO_I2C1_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_54", "SIO_I2C2_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_55", "SIO_I2C2_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_56", "SIO_I2C3_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_57", "SIO_I2C3_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_58", "SIO_I2C4_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_59", "SIO_I2C4_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_60", "SIO_UART0_RXD", "ISH_UART0_RXD", "CNV_GNSS_UART_RXD", "n/a", "n/a", "n/a", + "GPIO_61", "SIO_UART0_TXD", "ISH_UART0_TXD", "CNV_GNSS_UART_TXD", "n/a", "n/a", "n/a", + "GPIO_62", "SIO_UART0_RTS_N", "ISH_UART0_RTS_N", "CNV_GNSS_UART_RTS_N", "n/a", "n/a", "n/a", + "GPIO_63", "SIO_UART0_CTS_N", "ISH_UART0_CTS_N", "CNV_GNSS_UART_CTS_N", "n/a", "n/a", "n/a", + "GPIO_64", "SIO_UART2_RXD", "ISH_UART2_RXD", "CNV_MFUART1_RXD", "n/a", "n/a", "n/a", + "GPIO_65", "SIO_UART2_TXD", "ISH_UART2_TXD", "CNV_MFUART1_TXD", "n/a", "n/a", "n/a", + "GPIO_66", "SIO_UART2_RTS_N", "ISH_UART2_RTS_N", "CNV_MFUART1_RTS_N", "n/a", "n/a", "n/a", + "GPIO_67", "SIO_UART2_CTS_N", "ISH_UART2_CTS_N", "CNV_MFUART1_CTS_N", "n/a", "n/a", "n/a", + "GPIO_68", "PMC_SPI_FS0", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_69", "PMC_SPI_FS1", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_70", "PMC_SPI_FS2", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_71", "PMC_SPI_RXD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_72", "PMC_SPI_TXD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_73", "PMC_SPI_CLK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_74", "THERMTRIP_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_75", "PROCHOT_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_211","EMMC_RST_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_212", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_213", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_214", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_northwest = { + .display = "------- GPIO Group NorthWest -------", + .pad_count = ARRAY_SIZE(glk_group_northwest_names) / 7, + .func_count = 7, + .pad_names = glk_group_northwest_names, +}; + +static const struct gpio_group *const glk_community_northwest_groups[] = { + &glk_group_northwest, +}; + +static const struct gpio_community glk_community_northwest = { + .name = "----- GPIO Community NorthWest -----", + .pcr_port_id = 0xc4, + .group_count = ARRAY_SIZE(glk_community_northwest_groups), + .groups = glk_community_northwest_groups, +}; + +static const char *const glk_group_north_names[] = { + "GPIO_76", "SVID0_ALERT_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_77", "SVID0_DATA", "n/a", "n/a", "n/a", "n/a", + "GPIO_78", "SVID0_CLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_79", "SIO_SPI_0_CLK", "ISH_SPI_0_CLK", "n/a", "n/a", "n/a", + "GPIO_80", "SIO_SPI_0_FS0", "ISH_SPI_0_FS0", "n/a", "n/a", "n/a", + "GPIO_81", "SIO_SPI_0_FS1", "ISH_SPI_0_FS1", "FST_SPI_CS2_N", "n/a", "n/a", + "GPIO_82", "SIO_SPI_0_RXD", "ISH_SPI_0_RXD", "n/a", "n/a", "n/a", + "GPIO_83", "SIO_SPI_0_TXD", "ISH_SPI_0_TXD", "n/a", "n/a", "n/a", + "GPIO_84", "SIO_SPI_2_CLK", "ISH_SPI_1_CLK", "TOUCH_SPI_CLK", "n/a", "n/a", + "GPIO_85", "SIO_SPI_2_FS0", "ISH_SPI_1_FS0", "TOUCH_SPI_FS0", "n/a", "n/a", + "GPIO_86", "SIO_SPI_2_FS1", "ISH_SPI_1_FS1", "TOUCH_SPI_D0", "n/a", "n/a", + "GPIO_87", "SIO_SPI_2_FS2", "n/a", "TOUCH_SPI_D1", "n/a", "n/a", + "GPIO_88", "SIO_SPI_2_RXD", "ISH_SPI_1_RXD", "TOUCH_SPI_D2", "n/a", "n/a", + "GPIO_89", "SIO_SPI_2_TXD", "ISH_SPI_0_TXD", "TOUCH_SPI_D3", "n/a", "n/a", + "GPIO_90", "FST_SPI_CS0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_91", "FST_SPI_CS1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_92", "FST_SPI_MOSI_IO0", "n/a", "n/a", "n/a", "n/a", + "GPIO_93", "FST_SPI_MISO_IO1", "n/a", "n/a", "n/a", "n/a", + "GPIO_94", "FST_SPI_IO2", "n/a", "n/a", "n/a", "n/a", + "GPIO_95", "FST_SPI_IO3", "n/a", "n/a", "n/a", "n/a", + "GPIO_96", "FST_SPI_CLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_97", "FST_SPI_CLK_FB", "n/a", "n/a", "n/a", "n/a", + "GPIO_98", "PMU_PLTRST_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_99", "PMU_PWRBTN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_100", "PMU_SLP_S0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_101", "PMU_SLP_S3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_102", "PMU_SLP_S4_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_103", "SUSPWRDNACK", "n/a", "n/a", "n/a", "n/a", + "GPIO_104", "EMMC_PWR_EN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_105", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_106", "PMU_BATLOW_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_107", "PMU_RSTBTN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_108", "PMU_SUSCLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_109", "SUS_STAT_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_110", "SIO_I2C5_SDA", "ISH_I2C0_SDA", "n/a", "n/a", "n/a", + "GPIO_111", "SIO_I2C5_SCL", "ISH_I2C0_SCL", "n/a", "n/a", "n/a", + "GPIO_112", "SIO_I2C6_SDA", "ISH_I2C1_SDA", "n/a", "n/a", "n/a", + "GPIO_113", "SIO_I2C6_SCL", "ISH_I2C1_ScL", "n/a", "n/a", "n/a", + "GPIO_114", "SIO_I2C7_SDA", "ISH_I2C2_SDA", "SUSCLK1", "n/a", "n/a", + "GPIO_115", "SIO_I2C7_SCL", "ISH_I2C2_SCL", "SUSCLK2", "n/a", "n/a", + "GPIO_116", "PCIE_WAKE0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_117", "PCIE_WAKE1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_118", "PCIE_WAKE2_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_119", "PCIE_WAKE3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_120", "PCIE_CLKREQ0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_121", "PCIE_CLKREQ1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_122", "PCIE_CLKREQ2_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_123", "PCIE_CLKREQ3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_124", "DDI0_DDC_SDA", "n/a", "n/a", "n/a", "n/a", + "GPIO_125", "DDI0_DDC_SCL", "n/a", "n/a", "n/a", "n/a", + "GPIO_126", "DDI1_DDC_SDA", "SIO_I2C5_SDA", "n/a", "n/a", "n/a", + "GPIO_127", "DDI1_DDC_SCL", "SIO_I2C5_SCL", "n/a", "n/a", "n/a", + "GPIO_128", "PNL0_VDDEN", "n/a", "n/a", "n/a", "n/a", + "GPIO_129", "PNL0_BKLTEN", "n/a", "n/a", "n/a", "n/a", + "GPIO_130", "PNL0_BKLCTL", "n/a", "n/a", "n/a", "n/a", + "GPIO_131", "DDI0_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_132", "DDI1_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_133", "DDI2_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_134", "n/a", "n/a", "n/a", "ISH_GPIO_10", "n/a", + "GPIO_135", "n/a", "n/a", "n/a", "ISH_GPIO_11", "n/a", + "GPIO_136", "n/a", "n/a", "n/a", "ISH_GPIO_12", "n/a", + "GPIO_137", "n/a", "n/a", "n/a", "ISH_GPIO_13", "n/a", + "GPIO_138", "n/a", "SIO_UART3_RXD", "ISH_UART0_RXD", "ISH_GPIO_14", "SATA_GP0", + "GPIO_139", "n/a", "SIO_UART3_TXD", "ISH_UART0_TXD", "ISH_GPIO_15", "SATA_GP1", + "GPIO_140", "n/a", "SIO_UART3_RTS_N", "ISH_UART0_RTS_N", "n/a", "SATA_DEVSLP0", + "GPIO_141", "n/a", "SIO_UART3_CTS_N", "ISH_UART0_CTS_N", "n/a", "SATA_DEVSLP1", + "GPIO_142", "n/a", "SIO_SPI_1_CLK", "ISH_SPI_0_CLK", "n/a", "SATA_LEDN", + "GPIO_143", "n/a", "SIO_SPI_1_FS0", "ISH_SPI_0_FS0", "JTAG2_TCK", "n/a", + "GPIO_144", "n/a", "SIO_SPI_1_FS1", "ISH_SPI_0_FS1", "PNL1_VDDEN", "n/a", + "GPIO_145", "n/a", "SIO_SPI_1_RXD", "ISH_SPI_0_RXD", "PNL1_BKLTEN", "n/a", + "GPIO_146", "n/a", "SIO_SPI_1_TXD", "ISH_SPI_0_TXD", "PNL1_BKLTCTL", "n/a", + "GPIO_147", "LPC_SERIRQ", "ESPI_RESET_N", "n/a", "n/a", "n/a", + "GPIO_148", "LPC_CLKOUT0", "ESPI_CLK", "n/a", "n/a", "n/a", + "GPIO_149", "LPC_CLKOUT1", "n/a", "n/a", "n/a", "n/a", + "GPIO_150", "LPC_AD0", "ESPI_IO_0", "n/a", "n/a", "n/a", + "GPIO_151", "LPC_AD1", "ESPI_IO_1", "n/a", "n/a", "n/a", + "GPIO_152", "LPC_AD2", "ESPI_IO_2", "n/a", "n/a", "n/a", + "GPIO_153", "LPC_AD3", "ESPI_IO_3", "n/a", "n/a", "n/a", + "GPIO_154", "LPC_CLKRUN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_155", "LPC_FRAME_N", "ESPI_CS_N", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_north = { + .display = "----- GPIO Group North -----", + .pad_count = ARRAY_SIZE(glk_group_north_names) / 6, + .func_count = 6, + .pad_names = glk_group_north_names, +}; + +static const struct gpio_group *const glk_community_north_groups[] = { + &glk_group_north, +}; + +static const struct gpio_community glk_community_north = { + .name = "--- GPIO Community North ---", + .pcr_port_id = 0xc5, + .group_count = ARRAY_SIZE(glk_community_north_groups), + .groups = glk_community_north_groups, +}; + +static const char *const glk_group_audio_names[] = { + "GPIO_156", "AVS_I2S0_MCLK", "n/a", "n/a", + "GPIO_157", "AVS_I2S0_BCLK", "n/a", "n/a", + "GPIO_158", "AVS_I2S0_WS_SYNC", "n/a", "n/a", + "GPIO_159", "AVS_I2S0_SDI", "n/a", "n/a", + "GPIO_160", "AVS_I2S0_SDO", "n/a", "n/a", + "GPIO_161", "AVS_I2S1_MCLK", "n/a", "n/a", + "GPIO_162", "AVS_I2S1_BCLK", "n/a", "CNV_BT_I2S_BCLK", + "GPIO_163", "AVS_I2S1_WS_SYNC", "n/a", "CNV_BT_I2S_WS_SYNC", + "GPIO_164", "AVS_I2S1_SDI", "n/a", "CNV_BT_I2S_SDI", + "GPIO_165", "AVS_I2S1_SDO", "n/a", "CNV_BT_I2S_SDO", + "GPIO_166", "AVS_HDA_BCLK", "AVS_I2S2_BCLK", "n/a", + "GPIO_167", "AVS_HDA_WS_SYNC", "AVS_I2S2_WS_SYNC", "n/a", + "GPIO_168", "AVS_HDA_SDI", "AVS_I2S2_SDI", "n/a", + "GPIO_169", "AVS_HDA_SDO", "AVS_I2S2_SDO", "n/a", + "GPIO_170", "AVS_HDA_RST_N", "AVS_I2S1_MCLK", "n/a", + "GPIO_171", "AVS_DMIC_CLK_A1", "n/a", "n/a", + "GPIO_172", "AVS_DMIC_CLK_B1", "n/a", "n/a", + "GPIO_173", "AVS_DMIC_DATA_1", "n/a", "n/a", + "GPIO_174", "AVS_DMIC_CLK_AB2", "n/a", "n/a", + "GPIO_175", "AVS_DMIC_DATA_2", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_audio = { + .display = "----- GPIO Group Audio -----", + .pad_count = ARRAY_SIZE(glk_group_audio_names) / 4, + .func_count = 4, + .pad_names = glk_group_audio_names, +}; + +static const struct gpio_group *const glk_community_audio_groups[] = { + &glk_group_audio, +}; + +static const struct gpio_community glk_community_audio = { + .name = "--- GPIO Community Audio ---", + .pcr_port_id = 0xc9, + .group_count = ARRAY_SIZE(glk_community_audio_groups), + .groups = glk_community_audio_groups, +}; + +static const char *const glk_group_scc_names[] = { + "GPIO_176", "SMB_ALERT_N", "n/a", "n/a", + "GPIO_177", "SMB_CLK", "SIO_I2C7_SCL", "n/a", + "GPIO_178", "SMB_DATA", "SIO_I2C7_SDA", "n/a", + "GPIO_187", "SDCARD_LVL_WP", "n/a", "n/a", + "GPIO_179", "SDCARD_CLK", "n/a", "n/a", + "GPIO_180", "SDCARD_CLK_FB", "n/a", "n/a", + "GPIO_181", "SDCARD_D0", "n/a", "n/a", + "GPIO_182", "SDCARD_D1", "n/a", "n/a", + "GPIO_183", "SDCARD_D2", "n/a", "n/a", + "GPIO_184", "SDCARD_D3", "n/a", "n/a", + "GPIO_185", "SDCARD_CMD", "n/a", "n/a", + "GPIO_186", "SDCARD_CD_N", "n/a", "n/a", + "GPIO_188", "SDCARD_PWR_DWN_N", "n/a", "n/a", + "GPIO_210", "n/a", "n/a", "n/a", + "GPIO_189", "OSC_CLK_OUT_0", "n/a", "n/a", + "GPIO_190", "OSC_CLK_OUT_1", "n/a", "n/a", + "GPIO_191", "CNV_BRI_DT", "n/a", "SIO_UART1_RTS_N", + "GPIO_192", "CNV_BRI_RST", "n/a", "SIO_UART1_RXD", + "GPIO_193", "CNV_RGI_DT", "n/a", "SIO_UART1_TXD", + "GPIO_194", "CNV_RGI_RST", "n/a", "SIO_UART1_CTS_N", + "GPIO_195", "CNV_RF_RESET_N", "n/a", "AVS_I2S1_WS_SYNC", + "GPIO_196", "XTAL_CLKREQ", "n/a", "AVS_I2S1_SDO", + "GPIO_197", "SDIO_CLK_FB", "n/a", "n/a", + "GPIO_198", "EMMC_CLK", "n/a", "n/a", + "GPIO_199", "EMMC_D0", "n/a", "n/a", + "GPIO_200", "EMMC_D1", "n/a", "n/a", + "GPIO_201", "EMMC_D2", "n/a", "n/a", + "GPIO_202", "EMMC_D3", "n/a", "n/a", + "GPIO_203", "EMMC_D4", "n/a", "n/a", + "GPIO_204", "EMMC_D5", "n/a", "n/a", + "GPIO_205", "EMMC_D6", "n/a", "n/a", + "GPIO_206", "EMMC_D7", "n/a", "n/a", + "GPIO_207", "EMMC_CMD", "n/a", "n/a", + "GPIO_208", "EMMC_RCLK", "n/a", "n/a", + "GPIO_209", "EMMC_RST_N", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_scc = { + .display = "----- GPIO Group SCC -----", + .pad_count = ARRAY_SIZE(glk_group_scc_names) / 4, + .func_count = 4, + .pad_names = glk_group_scc_names, +}; + +static const struct gpio_group *const glk_community_scc_groups[] = { + &glk_group_scc, +}; + +static const struct gpio_community glk_community_scc = { + .name = "--- GPIO Community SCC ---", + .pcr_port_id = 0xc8, + .group_count = ARRAY_SIZE(glk_community_scc_groups), + .groups = glk_community_scc_groups, +}; + +static const struct gpio_community *const glk_communities[] = { + &glk_community_northwest, &glk_community_north, + &glk_community_audio, &glk_community_scc, +}; + static const char *const apl_group_north_names[] = { "*GPIO_0", "n/a", "n/a", "n/a", "n/a", "n/a", "*GPIO_1", "n/a", "n/a", "n/a", "n/a", "n/a", @@ -2284,6 +2588,12 @@ communities = apl_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_GLK: + community_count = ARRAY_SIZE(glk_communities); + communities = glk_communities; + pad_stepping = 16; + pcr_init(sb); + break; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index de66811..4e8f76e 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -304,6 +304,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK, "Gemini Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" }, /* Intel GPUs */ @@ -399,6 +400,8 @@ "Intel(R) HD Graphics 530" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_530_2, "Intel(R) HD Graphics 530" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_605, + "Intel(R) UHD Graphics 605" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_1, "Intel(R) UHD Graphics 615" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_2, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 1c1841c..48d1198 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -263,8 +263,9 @@ #define PCI_DEVICE_ID_INTEL_BAYTRAIL 0x0f00 /* SOC Transaction Router */ #define PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC 0x0f1c #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31 -#define CPUID_BAYTRAIL 0x30670 +#define CPUID_BAYTRAIL 0x30670 +#define PCI_DEVICE_ID_INTEL_GLK 0x31e8 #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 #define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc @@ -342,6 +343,7 @@ #define PCI_DEVICE_ID_INTEL_HD_520 0x1916 #define PCI_DEVICE_ID_INTEL_HD_530_1 0x191B #define PCI_DEVICE_ID_INTEL_HD_530_2 0x1912 +#define PCI_DEVICE_ID_INTEL_UHD_605 0x3185 #define PCI_DEVICE_ID_INTEL_UHD_615_1 0x591C #define PCI_DEVICE_ID_INTEL_UHD_615_2 0x591E #define PCI_DEVICE_ID_INTEL_UHD_617 0x87C0 diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index ef6bb39..2dcdf25 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -122,6 +122,9 @@ case PCI_DEVICE_ID_INTEL_APL_LPC: p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0); break; + case PCI_DEVICE_ID_INTEL_GLK: + p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0); + break; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: -- To view, visit https://review.coreboot.org/c/coreboot/+/38909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63b9129a419facbcd2ca4819ba5946c40d7d5498 Gerrit-Change-Number: 38909 Gerrit-PatchSet: 1 Gerrit-Owner: Miroslaw Kocur <mirek190(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Furquan Shaikh (Code Review) 02 Mar '20

02 Mar '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39111 ) Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support ...................................................................... Patch Set 12: (3 comments) https://review.coreboot.org/c/coreboot/+/39111/12/src/soc/intel/common/acpi… File src/soc/intel/common/acpi/gpio_op.asl: https://review.coreboot.org/c/coreboot/+/39111/12/src/soc/intel/common/acpi… PS12, Line 76: /* : * Set Pad mode : * Arg0 - GPIO Number : * Arg1 - Pad mode : * 0 = GPIO control pad : * 1 = Native Function 1 : * 2 = Native Function 2 : * 3 = Native Function 3 : */ : Method (GPMO, 2, Serialized) : { : OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) : Field (PREG, AnyAcc, NoLock, Preserve) : { : VAL0, 32 : } : Store (VAL0, Local0) : And (Not (GPIOPADMODE_MASK), Local0, Local0) : And (ShiftLeft (Arg1, GPIOPADMODE_SHIFT, Arg1), GPIOPADMODE_MASK, Arg1) : Or (Local0, Arg1, VAL0) : } : : /* : * Enable/Disable Tx buffer : * Arg0 - GPIO Number : * Arg1 - TxBuffer state : * 0 = Disable Tx Buffer : * 1 = Enable Tx Buffer : */ : Method (GTXE, 2, Serialized) : { : OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) : Field (PREG, AnyAcc, NoLock, Preserve) : { : VAL0, 32 : } : : If (LEqual (Arg1, 1)) { : And (Not (GPIOTXBUFDIS_MASK), VAL0, VAL0) : } ElseIf (LEqual (Arg1, 0)){ : Or (GPIOTXBUFDIS_MASK, VAL0, VAL0) : } : } : : /* : * Enable/Disable Rx buffer : * Arg0 - GPIO Number : * Arg1 - RxBuffer state : * 0 = Disable Rx Buffer : * 1 = Enable Rx Buffer : */ : Method (GRXE, 2, Serialized) : { : OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) : Field (PREG, AnyAcc, NoLock, Preserve) : { : VAL0, 32 : } : : If (LEqual (Arg1, 1)) { : And (Not (GPIORXBUFDIS_MASK), VAL0, VAL0) : } ElseIf (LEqual (Arg1, 0)){ : Or (GPIORXBUFDIS_MASK, VAL0, VAL0) : } : } Looks like these got added when moving code into gpio_op.asl. Are these used anywhere? https://review.coreboot.org/c/coreboot/+/39111/12/src/soc/intel/tigerlake/a… File src/soc/intel/tigerlake/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/39111/12/src/soc/intel/tigerlake/a… PS12, Line 122: rg0 >= GPP_B0 && Arg0 <= GPP_A24) This was intentionally written in ACPI ASL2.0. Why does the CL move it back to old style? https://review.coreboot.org/c/coreboot/+/39111/12/src/soc/intel/tigerlake/a… PS12, Line 21: Device (GPIO) Why was this device changed? This is going to break compatibility with Linux kernel driver for handling the GPIO community blocks on TGL. -- To view, visit https://review.coreboot.org/c/coreboot/+/39111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Gerrit-Change-Number: 39111 Gerrit-PatchSet: 12 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Mar 2020 21:53:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake
by Srinidhi N Kaushik (Code Review) 02 Mar '20

02 Mar '20

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39168 ) Change subject: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I063f921832a4e4a45eb6978b6dbb37b1ac7dde7f Gerrit-Change-Number: 39168 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Mon, 02 Mar 2020 21:18:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton/uart.c: Clean up code
by Felix Singer (Code Review) 02 Mar '20

02 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37121 ) Change subject: soc/intel/denverton/uart.c: Clean up code ...................................................................... soc/intel/denverton/uart.c: Clean up code Since there is only one device ID used for UART, an array is not needed. Therefore, just save the device ID to the device variable. Change-Id: Icd325e1102a85cc175f6025519a47a1b64ee5b46 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/denverton_ns/uart.c 1 file changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/37121/1 diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index 28e0e2e..3b851ee 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -57,15 +57,10 @@ .enable = DEVICE_NOOP }; -static const unsigned short uart_ids[] = { - PCI_DEVICE_ID_INTEL_DENVERTON_HSUART, - 0 -}; - static const struct pci_driver uart_driver __pci_driver = { .ops = &uart_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = uart_ids + .device = PCI_DEVICE_ID_INTEL_DENVERTON_HSUART }; static void hide_hsuarts(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/37121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd325e1102a85cc175f6025519a47a1b64ee5b46 Gerrit-Change-Number: 37121 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton: Move PCI IDs to pci_ids.h
by Felix Singer (Code Review) 02 Mar '20

02 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37120 ) Change subject: soc/intel/denverton: Move PCI IDs to pci_ids.h ...................................................................... soc/intel/denverton: Move PCI IDs to pci_ids.h This patch moves the PCI ID definitions to pci_ids.h file and replaces every occurrence with the new names. The resulting binary doesn't differ from the one without this patch. Used documents: - Intel 337018 Change-Id: Ib7d2aae78c8877f3c9287d03b20a5620db293445 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/include/device/pci_ids.h M src/soc/intel/denverton_ns/csme_ie_kt.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/npk.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/denverton_ns/uart.c M src/soc/intel/denverton_ns/xhci.c 10 files changed, 45 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/37120/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 18d6f60..c7b87b0 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2675,6 +2675,40 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 +/* Intel Denverton (Atom C3000 family) */ +#define PCI_DEVICE_ID_INTEL_DENVERTON_SA 0x1980 +#define PCI_DEVICE_ID_INTEL_DENVERTONAD_SA 0x1995 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP0 0x19a4 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP1 0x19a5 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP2 0x19a6 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP3 0x19a7 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP4 0x19a8 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP5 0x19a9 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP6 0x19aa +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP7 0x19ab +#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS 0x19ac +#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1 0x19b2 +#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2 0x19c2 +#define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0 +#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_1 0x19d1 +#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_2 0x19d2 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_1 0x19d3 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_2 0x19d4 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT 0x19d5 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_3 0x19d6 +#define PCI_DEVICE_ID_INTEL_DENVERTON_HSUART 0x19d8 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_1 0x19e5 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_2 0x19e6 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT 0x19e8 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_3 0x19e9 +#define PCI_DEVICE_ID_INTEL_DENVERTON_EMMC 0x19db +#define PCI_DEVICE_ID_INTEL_DENVERTON_LPC 0x19dc +#define PCI_DEVICE_ID_INTEL_DENVERTON_P2SB 0x19dd +#define PCI_DEVICE_ID_INTEL_DENVERTON_PMC 0x19de +#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS_LEGACY 0x19df +#define PCI_DEVICE_ID_INTEL_DENVERTON_SPI 0x19e0 +#define PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB 0x19e1 + /* Intel LPC device ids */ #define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 #define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c index 5967840..2b730e9 100644 --- a/src/soc/intel/denverton_ns/csme_ie_kt.c +++ b/src/soc/intel/denverton_ns/csme_ie_kt.c @@ -77,8 +77,8 @@ }; static const unsigned short pci_device_ids[] = { - ME_MEKT_DEVID, /* DVN CSME KT */ - IE_MEKT_DEVID, /* DVN IE KT */ + PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT, + PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT, 0 }; diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index faa4d92..a300fd4 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -158,46 +158,4 @@ #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) -#define SA_DEVID 0x1980 -#define SA_DEVID_DNVAD 0x1995 -#define SOC_DEVID SA_DEVID -#define RAS_DEVID 0x19a1 -#define RCEC_DEVID 0x19a2 -#define VRP2_DEVID 0x19a3 -#define PCIE_PORT1_DEVID 0x19a4 -#define PCIE_PORT2_DEVID 0x19a5 -#define PCIE_PORT3_DEVID 0x19a6 -#define PCIE_PORT4_DEVID 0x19a7 -#define PCIE_PORT5_DEVID 0x19a8 -#define PCIE_PORT6_DEVID 0x19a9 -#define PCIE_PORT7_DEVID 0x19aa -#define PCIE_PORT8_DEVID 0x19ab -#define SMBUS2_DEVID 0x19ac -#define AHCI_DEVID 0x19b2 -#define AHCI2_DEVID 0x19c2 -#define XHCI_DEVID 0x19d0 -#define VRP0_DEVID 0x19d1 -#define VRP1_DEVID 0x19d2 -#define ME_HECI1_DEVID 0x19d3 -#define ME_HECI2_DEVID 0x19d4 -#define ME_IEDR_DEVID 0x19ea -#define ME_MEKT_DEVID 0x19d5 -#define ME_HECI3_DEVID 0x19d6 -#define HSUART_DEVID 0x19d8 -#define HSUART1_DEVID HSUART_DEVID -#define HSUART2_DEVID HSUART_DEVID -#define HSUART3_DEVID HSUART_DEVID -#define IE_HECI1_DEVID 0x19e5 -#define IE_HECI2_DEVID 0x19e6 -#define IE_IEDR_DEVID 0x19e7 -#define IE_MEKT_DEVID 0x19e8 -#define IE_HECI3_DEVID 0x19e9 -#define MMC_DEVID 0x19db -#define LPC_DEVID 0x19dc -#define P2SB_DEVID 0x19dd -#define PMC_DEVID 0x19de -#define SMBUS_DEVID 0x19df -#define SPI_DEVID 0x19e0 -#define NPK_DEVID 0x19e1 - #endif /* _DENVERTON_NS_PCI_DEVS_H_ */ diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 123fb24..6481cbe 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -324,7 +324,7 @@ static const struct pci_driver lpc_driver __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = LPC_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_LPC, }; static void finalize_chipset(void *unused) diff --git a/src/soc/intel/denverton_ns/npk.c b/src/soc/intel/denverton_ns/npk.c index 0404893..631aac7 100644 --- a/src/soc/intel/denverton_ns/npk.c +++ b/src/soc/intel/denverton_ns/npk.c @@ -46,5 +46,5 @@ static const struct pci_driver pch_pmc __pci_driver = { .ops = &pmc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = NPK_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB, }; diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 8b52087..cbb9a4e 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -113,5 +113,5 @@ static const struct pci_driver pch_pmc __pci_driver = { .ops = &pmc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PMC_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_PMC, }; diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index ddb8b02..d53d553 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -74,8 +74,8 @@ }; static const unsigned short pci_device_ids[] = { - AHCI_DEVID, /* DVN SATA AHCI */ - AHCI2_DEVID, /* DVN SATA2 AHCI */ + PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1, + PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2, 0 }; diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index 00d5228..50f25c0 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -345,8 +345,8 @@ /* IDs for System Agent device of Intel Denverton SoC */ static const unsigned short systemagent_ids[] = { - SA_DEVID, /* DVN System Agent */ - SA_DEVID_DNVAD, /* DVN-AD System Agent */ + PCI_DEVICE_ID_INTEL_DENVERTON_SA, + PCI_DEVICE_ID_INTEL_DENVERTONAD_SA, 0 }; diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index 50f8a29..28e0e2e 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -58,7 +58,7 @@ }; static const unsigned short uart_ids[] = { - HSUART_DEVID, /* HSUART 0/1/2 */ + PCI_DEVICE_ID_INTEL_DENVERTON_HSUART, 0 }; diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c index 0a4b3b1..a0ed6ba 100644 --- a/src/soc/intel/denverton_ns/xhci.c +++ b/src/soc/intel/denverton_ns/xhci.c @@ -47,5 +47,5 @@ static const struct pci_driver pch_usb_xhci __pci_driver = { .ops = &usb_xhci_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = XHCI_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_XHCI, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/37120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d2aae78c8877f3c9287d03b20a5620db293445 Gerrit-Change-Number: 37120 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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