coreboot-gerrit March 2020

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Change in coreboot[master]: soc/intel/apollolake: Fix flashconsole, again
by Angel Pons (Code Review) 02 Mar '20

02 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39164 ) Change subject: soc/intel/apollolake: Fix flashconsole, again ...................................................................... soc/intel/apollolake: Fix flashconsole, again This time, it failed to build if measured boot was not enabled. Fix this problem, and make sure flashconsole will not break like that again. Change-Id: I5f5ffd14a3225804524cb0c1518e3d99737e0a93 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A configs/config.google_octopus_spi_flash_console M src/soc/intel/apollolake/Makefile.inc 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39164/1 diff --git a/configs/config.google_octopus_spi_flash_console b/configs/config.google_octopus_spi_flash_console new file mode 100644 index 0000000..df8889b --- /dev/null +++ b/configs/config.google_octopus_spi_flash_console @@ -0,0 +1,4 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_OCTOPUS=y +CONFIG_CONSOLE_SPI_FLASH=y +# CONFIG_VBOOT_MEASURED_BOOT is not set diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1fbdc91..0d72bc8 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -77,7 +77,7 @@ postcar-y += heci.c postcar-y += reset.c postcar-y += uart.c -postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c +postcar-y += gspi.c verstage-y += car.c verstage-y += i2c.c -- To view, visit https://review.coreboot.org/c/coreboot/+/39164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f5ffd14a3225804524cb0c1518e3d99737e0a93 Gerrit-Change-Number: 39164 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Fix VBOOT
by Patrick Rudolph (Code Review) 02 Mar '20

02 Mar '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39160 ) Change subject: nb/intel/sandybridge: Fix VBOOT ...................................................................... nb/intel/sandybridge: Fix VBOOT The VBOOT code can be compiled but it asserts with: ASSERTION ERROR: file 'src/security/vboot/common.c', line 40 Start VBOOT in bootblock to fix the assertion. Tested on Lenovo X220: The assertion is gone, the platform boots again. Change-Id: I48365e911b4f43aecba3b1f950178b7ceed5b2e9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/Kconfig 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/39160/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 7a27d09..49d3272 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -24,7 +24,9 @@ if NORTHBRIDGE_INTEL_SANDYBRIDGE config VBOOT - select VBOOT_STARTS_IN_ROMSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE config USE_NATIVE_RAMINIT bool "Use native raminit" -- To view, visit https://review.coreboot.org/c/coreboot/+/39160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48365e911b4f43aecba3b1f950178b7ceed5b2e9 Gerrit-Change-Number: 39160 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: acpi: Bump FADT to revision 6
by Patrick Rudolph (Code Review) 02 Mar '20

02 Mar '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39157 ) Change subject: acpi: Bump FADT to revision 6 ...................................................................... acpi: Bump FADT to revision 6 Some of the revision 4 FADT fields were already updated to ACPI spec revision 6, but not all of them. In addition the advertised FADT revision was 3. Implement all fields as defined in version 6 and bump the advertised FADT revision to 6. Change-Id: I10c1e2517df41159ab9b04f763d3805ecba50ffa Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h 2 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/39157/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 6dab373..b9e896f 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1563,7 +1563,7 @@ { switch (table) { case FADT: - return ACPI_FADT_REV_ACPI_3_0; + return ACPI_FADT_REV_ACPI_6_0; case MADT: /* ACPI 3.0: 2, ACPI 4.0/5.0: 3, ACPI 6.2b/6.3: 5 */ return 2; case MCFG: diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 68475c1..6a67012 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -529,8 +529,8 @@ u32 flags; acpi_addr_t reset_reg; u8 reset_value; - u16 ARM_boot_arch; - u8 FADT_MinorVersion; + u16 ARM_boot_arch; /* Revision 6 only, Revision5: Must be zero */ + u8 FADT_MinorVersion; /* Revision 6 only, Revision5: Must be zero */ u32 x_firmware_ctl_l; u32 x_firmware_ctl_h; u32 x_dsdt_l; @@ -543,6 +543,11 @@ acpi_addr_t x_pm_tmr_blk; acpi_addr_t x_gpe0_blk; acpi_addr_t x_gpe1_blk; + /* Revision 5 */ + acpi_addr_t sleep_control_reg; + acpi_addr_t sleep_status_reg; + /* Revision 6 */ + u64 hypervisor_vendor_identity; } __packed acpi_fadt_t; /* FADT TABLE Revision values */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10c1e2517df41159ab9b04f763d3805ecba50ffa Gerrit-Change-Number: 39157 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/at24rf08c: Move opening bracket to line above
by Paul Menzel (Code Review) 02 Mar '20

02 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38392 ) Change subject: drivers/i2c/at24rf08c: Move opening bracket to line above ...................................................................... drivers/i2c/at24rf08c: Move opening bracket to line above Adhere to the coding style. Change-Id: Ia12a4ed6ab2fb2c9848a2688b41fcfa70ab001b0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/drivers/i2c/at24rf08c/at24rf08c.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/38392/1 diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index daf04a9..b1ea6fa 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -31,8 +31,7 @@ printk (BIOS_DEBUG, "Locking EEPROM RFID\n"); - for (i = 0; i < 8; i++) - { + for (i = 0; i < 8; i++) { /* After a register write AT24RF08C sometimes stops responding. Retry several times in case of failure. */ for (j = 0; j < 100; j++) -- To view, visit https://review.coreboot.org/c/coreboot/+/38392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia12a4ed6ab2fb2c9848a2688b41fcfa70ab001b0 Gerrit-Change-Number: 38392 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: drivers/i2c/at24rf08c: Correctly format short multi-line comments
by Paul Menzel (Code Review) 02 Mar '20

02 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38391 ) Change subject: drivers/i2c/at24rf08c: Correctly format short multi-line comments ...................................................................... drivers/i2c/at24rf08c: Correctly format short multi-line comments Change-Id: I84e09706aceae69671ce429d77e7874128468307 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/drivers/i2c/at24rf08c/at24rf08c.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/38391/1 diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index 102e0e8..daf04a9 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -25,7 +25,7 @@ return; /* Ensure that EEPROM/RFID chip is not accessible through RFID. - Need to do it only on 5c. */ + Need to do it only on 5c. */ if (dev->path.type != DEVICE_PATH_I2C || dev->path.i2c.device != 0x5c) return; @@ -34,8 +34,7 @@ for (i = 0; i < 8; i++) { /* After a register write AT24RF08C sometimes stops responding. - Retry several times in case of failure. - */ + Retry several times in case of failure. */ for (j = 0; j < 100; j++) if (smbus_write_byte(dev, i, 0x0f) >= 0) break; -- To view, visit https://review.coreboot.org/c/coreboot/+/38391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84e09706aceae69671ce429d77e7874128468307 Gerrit-Change-Number: 38391 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/octopus: support Elan touch panel(include USI pen) for Foob
by Tommie Lin (Code Review) 02 Mar '20

02 Mar '20

Tommie Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38823 ) Change subject: mb/google/octopus: support Elan touch panel(include USI pen) for Foob ...................................................................... mb/google/octopus: support Elan touch panel(include USI pen) for Foob BUG=None TEST=build bios and verify touch screen works fine Signed-off-by: Tommie Lin <tong.lin(a)bitland.corp-partner.google.com> Change-Id: Ibec3d08cc740e398a10a5c845181318724afc70a --- M src/mainboard/google/octopus/variants/foob/overridetree.cb 1 file changed, 11 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38823/1 diff --git a/src/mainboard/google/octopus/variants/foob/overridetree.cb b/src/mainboard/google/octopus/variants/foob/overridetree.cb index b131173..fea012b 100644 --- a/src/mainboard/google/octopus/variants/foob/overridetree.cb +++ b/src/mainboard/google/octopus/variants/foob/overridetree.cb @@ -134,16 +134,17 @@ end end # - I2C 6 device pci 17.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0001"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" device i2c 10 on end end chip drivers/i2c/hid -- To view, visit https://review.coreboot.org/c/coreboot/+/38823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibec3d08cc740e398a10a5c845181318724afc70a Gerrit-Change-Number: 38823 Gerrit-PatchSet: 1 Gerrit-Owner: Tommie Lin <tong.lin(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/var/jinlon: Disable EPS on some SKUs
by Rajat Jain (Code Review) 02 Mar '20

02 Mar '20

Rajat Jain has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39156 ) Change subject: mb/google/hatch/var/jinlon: Disable EPS on some SKUs ...................................................................... mb/google/hatch/var/jinlon: Disable EPS on some SKUs Disable EPS on the SKUs that do not have it. Change-Id: I7305097beea3484634933ab856fd084933868a10 Signed-off-by: Rajat Jain <rajatja(a)google.com> --- M src/mainboard/google/hatch/variants/jinlon/Makefile.inc A src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h A src/mainboard/google/hatch/variants/jinlon/mainboard.c 3 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/39156/1 diff --git a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc index c57d090..d38a577 100644 --- a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc +++ b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc @@ -25,4 +25,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += mainboard.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h new file mode 100644 index 0000000..1d45fcd --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __JINLON_SKU_H__ +#define __JINLON_SKU_H__ + +/* + * SKU definition taken from + * https://buganizer.corp.google.com/issues/145688887#comment16 + */ +enum { + JINLON_SKU_01 = 1, /* No LTE, No view-angle-manegement */ + JINLON_SKU_02 = 2, /* No LTE, view-angle-manegement */ + JINLON_SKU_21 = 21, /* LTE, No view-angle-manegement */ + JINLON_SKU_22 = 22, /* LTE, view-angle-manegement */ +}; + +#endif /* __JINLON_SKU_H__ */ diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c new file mode 100644 index 0000000..75ecdaf --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include <arch/acpi_device.h> +#include <baseboard/variants.h> +#include <bootstate.h> +#include <device/device.h> +#include <drivers/gfx/generic/chip.h> +#include <variant/sku.h> + +static bool eps_sku(uint32_t sku_id) +{ + /* + * Assume EPS SKU by default, helpful for testing on + * unprovisioned or development SKUs. + */ + if (sku_id == JINLON_SKU_01 || sku_id == JINLON_SKU_21) + return false; + else + return true; +} + +static void check_for_eps(uint32_t sku_id) +{ + struct device *gfx_dev; + + if (eps_sku(sku_id)) { + printk(BIOS_INFO, "SKU ID %u has EPS\n", sku_id); + return; + } + + gfx_dev = find_gfx_dev(); + if (!gfx_dev) { + printk(BIOS_ERR, + "Error! No EPS dev, view-angle-management won't work\n"); + return; + } + + printk(BIOS_INFO, + "SKU ID %u doesn't have EPS, disabling...\n", + sku_id); + gfx_dev->enabled = 0; +} + +void variant_devtree_update(void) +{ + uint32_t sku_id = get_board_sku(); + + /* Disable EPS on SKUs that do not support it */ + check_for_eps(sku_id); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7305097beea3484634933ab856fd084933868a10 Gerrit-Change-Number: 39156 Gerrit-PatchSet: 1 Gerrit-Owner: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/var/jinlon: Enable gfx/generic driver
by Rajat Jain (Code Review) 02 Mar '20

02 Mar '20

Rajat Jain has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39155 ) Change subject: mb/google/hatch/var/jinlon: Enable gfx/generic driver ...................................................................... mb/google/hatch/var/jinlon: Enable gfx/generic driver Enable the GFX device for Jinlon. Change-Id: I6ba90bf464e315ec364b6f35e7670924a2aba25a Signed-off-by: Rajat Jain <rajatja(a)google.com> --- M src/mainboard/google/hatch/Kconfig.name M src/mainboard/google/hatch/variants/jinlon/overridetree.cb 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/39155/1 diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 2427b12..fc3a66e 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -19,6 +19,7 @@ bool "-> Jinlon" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GFX_GENERIC config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index f3f6c3b..f7ca7d5 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -65,6 +65,17 @@ register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 02.0 on + chip drivers/gfx/generic + register "device_count" = "1" + register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E0)" + device generic 0 on end + end + end # Integrated Graphics Device device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/39155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ba90bf464e315ec364b6f35e7670924a2aba25a Gerrit-Change-Number: 39155 Gerrit-PatchSet: 1 Gerrit-Owner: Rajat Jain <rajatja(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/gfx/generic: Add support for gpio based EPS
by Rajat Jain (Code Review) 02 Mar '20

02 Mar '20

Rajat Jain has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39154 ) Change subject: drivers/gfx/generic: Add support for gpio based EPS ...................................................................... drivers/gfx/generic: Add support for gpio based EPS Add support to control EPS via a PCH gpio Change-Id: I6f570fd43e1649fb23255b0890e01086e34f844a Signed-off-by: Rajat Jain <rajatja(a)google.com> --- M src/drivers/gfx/generic/chip.h M src/drivers/gfx/generic/generic.c 2 files changed, 73 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/39154/1 diff --git a/src/drivers/gfx/generic/chip.h b/src/drivers/gfx/generic/chip.h index 5e855e3..ef7d9db 100644 --- a/src/drivers/gfx/generic/chip.h +++ b/src/drivers/gfx/generic/chip.h @@ -28,6 +28,12 @@ const char *enable_function; /* ACPI namespace path to privacy screen disable function */ const char *disable_function; + /* + * GPIO used for controlling the privacy screen. If provided, + * the gpio mechanism takes preference over the functions ptrs + * above, if any (GPIO functions override the function ptrs). + */ + struct acpi_gpio gpio; }; /* Config for an output device as defined in section A.5 of the ACPI spec */ @@ -53,4 +59,6 @@ struct drivers_gfx_generic_device_config device[5]; }; +extern struct device *find_gfx_dev(void); + #endif /* __DRIVERS_GFX_GENERIC_CHIP_H__ */ diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index 8488040..7b5ddc7 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -24,6 +24,11 @@ #define ACPI_DSM_PRIVACY_SCREEN_UUID "C7033113-8720-4CEB-9090-9D52B3E52D73" +#define ACPI_METHOD_EPS_PRESENT "EPSP" +#define ACPI_METHOD_EPS_STATE "EPSS" +#define ACPI_METHOD_EPS_ENABLE "EPSE" +#define ACPI_METHOD_EPS_DISABLE "EPSD" + static void privacy_screen_detect_cb(void *arg) { struct drivers_gfx_generic_privacy_screen_config *config = arg; @@ -62,6 +67,52 @@ privacy_screen_disable_cb, }; +static void privacy_gpio_acpigen(struct acpi_gpio *gpio) +{ + /* EPS Present */ + acpigen_write_method(ACPI_METHOD_EPS_PRESENT, 0); + acpigen_write_return_byte(1); + acpigen_pop_len(); + + /* EPS State */ + acpigen_write_method(ACPI_METHOD_EPS_STATE, 0); + acpigen_get_rx_gpio(gpio); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_pop_len(); + + /* EPS Enable */ + acpigen_write_method(ACPI_METHOD_EPS_ENABLE, 0); + acpigen_enable_tx_gpio(gpio); + acpigen_pop_len(); + + /* EPS Disable */ + acpigen_write_method(ACPI_METHOD_EPS_DISABLE, 0); + acpigen_disable_tx_gpio(gpio); + acpigen_pop_len(); +} + +static void gfx_fill_privacy_screen_dsm(struct + drivers_gfx_generic_privacy_screen_config *privacy) +{ + if (!privacy->enabled) + return; + + /* Populate ACPI methods, if EPS controlled via gpio */ + if (privacy->gpio.pin_count == 1) { + privacy_gpio_acpigen(&privacy->gpio); + privacy->detect_function = ACPI_METHOD_EPS_PRESENT; + privacy->status_function = ACPI_METHOD_EPS_STATE; + privacy->enable_function = ACPI_METHOD_EPS_ENABLE; + privacy->disable_function = ACPI_METHOD_EPS_DISABLE; + } + + acpigen_write_dsm(ACPI_DSM_PRIVACY_SCREEN_UUID, + privacy_screen_callbacks, + ARRAY_SIZE(privacy_screen_callbacks), + privacy); +} + static void gfx_fill_ssdt_generator(struct device *dev) { size_t i; @@ -69,7 +120,7 @@ const char *scope = acpi_device_scope(dev); - if (!scope) + if (!scope || !dev->enabled) return; acpigen_write_scope(scope); @@ -85,17 +136,9 @@ for (i = 0; i < config->device_count; i++) { acpigen_write_device(config->device[i].name); - acpigen_write_name_integer("_ADR", config->device[i].addr); acpigen_write_name_integer("_STA", 0xF); - - if (config->device[i].privacy.enabled) { - acpigen_write_dsm(ACPI_DSM_PRIVACY_SCREEN_UUID, - privacy_screen_callbacks, - ARRAY_SIZE(privacy_screen_callbacks), - &config->device[i].privacy); - } - + gfx_fill_privacy_screen_dsm(&config->device[i].privacy); acpigen_pop_len(); /* Device */ } acpigen_pop_len(); /* Scope */ @@ -117,7 +160,7 @@ { struct drivers_gfx_generic_config *config = dev->chip_info; - if (!config) + if (!config || !dev->enabled) return; dev->ops = &gfx_ops; @@ -127,3 +170,14 @@ CHIP_NAME("Generic Graphics Device") .enable_dev = gfx_enable }; + +struct device *find_gfx_dev(void) +{ + struct device *dev; + + for (dev = all_devices; dev; dev = dev->next) { + if (dev->chip_ops && dev->chip_ops == &drivers_gfx_generic_ops) + return dev; + } + return NULL; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f570fd43e1649fb23255b0890e01086e34f844a Gerrit-Change-Number: 39154 Gerrit-PatchSet: 1 Gerrit-Owner: Rajat Jain <rajatja(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/acpigen: Add new helper routines for XOR and get_rx_gpio
by Rajat Jain (Code Review) 02 Mar '20

02 Mar '20

Rajat Jain has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39145 ) Change subject: arch/x86/acpigen: Add new helper routines for XOR and get_rx_gpio ...................................................................... arch/x86/acpigen: Add new helper routines for XOR and get_rx_gpio Add new helper function in the acpigen library, that use the underlying soc routines. Change-Id: I8d65699d3c806007a50adcb51c5d84567ce451b7 Signed-off-by: Rajat Jain <rajatja(a)google.com> --- M Documentation/acpi/gpio.md M src/arch/x86/acpigen.c M src/arch/x86/include/arch/acpigen.h 3 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39145/1 diff --git a/Documentation/acpi/gpio.md b/Documentation/acpi/gpio.md index d42042f..b9acd96 100644 --- a/Documentation/acpi/gpio.md +++ b/Documentation/acpi/gpio.md @@ -73,6 +73,15 @@ functions internally. Thus, all the ACPI AML calling conventions for the platform functions apply to these helper functions as well. +3. Get Rx GPIO + int acpigen_get_rx_gpio(struct acpi_gpio gpio) + +This function takes as input, an struct acpi_gpio type and outputs +AML code to read the *logical* value of a gpio (after taking its +polarity into consideration), into the Local0 variable. It calls +the platform specific acpigen_soc_read_rx_gpio() to actually read +the rx gpio value. + ## Implementation Details ACPI library in coreboot will provide weak definitions for all the diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 72605bb..2dad00a 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1203,6 +1203,15 @@ acpigen_emit_byte(res); } +/* Xor (arg1, arg2, res) */ +void acpigen_write_xor(uint9_t arg1, uint8_t arg2, uint8_t res) +{ + acpigen_emit_byte(XOR_OP); + acpigen_emit_byte(arg1); + acpigen_emit_byte(arg2); + acpigen_emit_byte(res); +} + /* And (arg1, arg2, res) */ void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res) { @@ -1759,6 +1768,14 @@ return acpigen_soc_clear_tx_gpio(gpio->pins[0]); } +void acpigen_get_rx_gpio(struct acpi_gpio *gpio) +{ + acpigen_soc_read_rx_gpio(gpio->pins[0]); + + if (gpio->polarity == ACPI_GPIO_ACTIVE_LOW) + acpigen_write_xor(LOCAL0_OP, 1, LOCAL0_OP); +} + /* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, u16 range_min, u16 range_max, u16 translation, u16 length) diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 0807558..34c5197 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -361,6 +361,7 @@ void acpigen_write_store(void); void acpigen_write_store_ops(uint8_t src, uint8_t dst); void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res); +void acpigen_write_xor(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_not(uint8_t arg, uint8_t res); void acpigen_write_debug_string(const char *str); @@ -472,6 +473,14 @@ int acpigen_enable_tx_gpio(struct acpi_gpio *gpio); int acpigen_disable_tx_gpio(struct acpi_gpio *gpio); +/* + * Helper function for getting a RX GPIO value based on the GPIO polarity. + * The return value is stored in Local0 variable. + * This function ends up calling acpigen_soc_get_rx_gpio to make callbacks + * into SoC acpigen code + */ +void acpigen_get_rx_gpio(struct acpi_gpio *gpio); + /* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, u16 range_min, u16 range_max, u16 translation, u16 length); @@ -481,4 +490,5 @@ /* refer to ACPI 6.4.3.5.1 QWord Address Space Descriptor section for details */ void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/39145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d65699d3c806007a50adcb51c5d84567ce451b7 Gerrit-Change-Number: 39145 Gerrit-PatchSet: 1 Gerrit-Owner: Rajat Jain <rajatja(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2020