Change in coreboot[master]: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake
Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39169 )
Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ......................................................................
soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake
update SerialIoUartAutoFlow settings for Tiger Lake platform.
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879 --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39169/1
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index d22cde0..b24156c 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <assert.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -120,6 +121,8 @@
/* PCH UART selection for FSP Debug */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + ASSERT(CONFIG_UART_FOR_CONSOLE < ARRAY_SIZE(params->SerialIoUartAutoFlow)); + params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
/* SATA */ dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39169 )
Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39169/1/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39169/1/src/soc/intel/tigerlake/fsp... PS1, Line 124: ASSERT(CONFIG_UART_FOR_CONSOLE < ARRAY_SIZE(params->SerialIoUartAutoFlow)); Comparisons should place the constant on the right side of the test
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39169 )
Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ......................................................................
Patch Set 1: Code-Review+1
Hello Raj Astekar, Patrick Rudolph, Nick Vaccaro, Wonkyu Kim, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39169
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ......................................................................
soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake
update SerialIoUartAutoFlow settings for Tiger Lake platform.
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879 --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39169/2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39169 )
Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ......................................................................
Patch Set 2: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39169 )
Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39169/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39169/2//COMMIT_MSG@10 PS2, Line 10: Tested how?
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39169
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ......................................................................
soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake
update SerialIoUartAutoFlow settings for Tiger Lake platform.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879 --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39169/3
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39169 )
Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39169/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39169/2//COMMIT_MSG@10 PS2, Line 10:
Tested how?
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39169 )
Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ......................................................................
Patch Set 3: Code-Review+2
caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39169 )
Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ......................................................................
Patch Set 3: Code-Review+1
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39169 )
Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39169/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39169/3/src/soc/intel/tigerlake/fsp... PS3, Line 124: ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); something to investigate perhaps, it might be possible to make this a https://en.cppreference.com/w/c/language/_Static_assert
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39169 )
Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ......................................................................
soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake
update SerialIoUartAutoFlow settings for Tiger Lake platform.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39169 Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: caveh jalali caveh@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Srinidhi N Kaushik: Looks good to me, but someone else must approve caveh jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index fbc9f23..0587b88 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <assert.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -120,6 +121,8 @@
/* PCH UART selection for FSP Debug */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); + params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
/* SATA */ dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
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build bot (Jenkins) (Code Review) -
caveh jalali (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Srinidhi N Kaushik (Code Review)
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Wonkyu Kim (Code Review)