Srinidhi N Kaushik uploaded patch set #3 to this change.

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soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake

update SerialIoUartAutoFlow settings for Tiger Lake platform.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39169/3

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879
Gerrit-Change-Number: 39169
Gerrit-PatchSet: 3
Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro@google.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: Raj Astekar <raj.astekar@intel.com>
Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: newpatchset