coreboot-gerrit March 2020

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Change in coreboot[master]: mb/libretrend/lt1000: Add Libretrend LT1000 board support
by Michał Żygowski (Code Review) 06 Mar '20

06 Mar '20

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: mb/libretrend/lt1000: Add Libretrend LT1000 board support ...................................................................... Patch Set 15: > Patch Set 15: > > > Patch Set 15: > > > > > Patch Set 15: > > > > > > Board status available for review: https://review.coreboot.org/cgit/board-status.git/tree/libretrend/lt1000/4.… > > > > Thank you. As written in the other review, for commits not in the master branch, please add the source for your upload to the board status commit message. > > > > Looking at the data, the FspMemoryInit is *very* slow. > > > > + 950:calling FspMemoryInit 319,239 (193,169) > > + 951:returning from FspMemoryInit 17,456,411 (17,137,171) > > Hmm should I force push the board_status repository? > > The MemoryInit is horrible with Kaby Lake FSP. It is also very slow on Protectli FW6, but I think it is a matter of DDR4. DDR3 could be faster probably. Vendor BIOS also initializes the memory very slowly on both FW6 and LT1000, for reference, so I assumed it just has to be like that. -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Mar 2020 15:07:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/libretrend/lt1000: Add Libretrend LT1000 board support
by Michał Żygowski (Code Review) 06 Mar '20

06 Mar '20

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: mb/libretrend/lt1000: Add Libretrend LT1000 board support ...................................................................... Patch Set 15: > Patch Set 15: > > > Patch Set 15: > > > > Board status available for review: https://review.coreboot.org/cgit/board-status.git/tree/libretrend/lt1000/4.… > > Thank you. As written in the other review, for commits not in the master branch, please add the source for your upload to the board status commit message. > > Looking at the data, the FspMemoryInit is *very* slow. > > + 950:calling FspMemoryInit 319,239 (193,169) > + 951:returning from FspMemoryInit 17,456,411 (17,137,171) Hmm should I force push the board_status repository? The MemoryInit is horrible with Kaby Lake FSP. It is also very slow on Protectli FW6, but I think it is a matter of DDR4. DDR3 could be faster probably. -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Mar 2020 15:05:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/libretrend/lt1000: Add Libretrend LT1000 board support
by Paul Menzel (Code Review) 06 Mar '20

06 Mar '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: mb/libretrend/lt1000: Add Libretrend LT1000 board support ...................................................................... Patch Set 15: > Patch Set 15: > > Board status available for review: https://review.coreboot.org/cgit/board-status.git/tree/libretrend/lt1000/4.… Thank you. As written in the other review, for commits not in the master branch, please add the source for your upload to the board status commit message. Looking at the data, the FspMemoryInit is *very* slow. + 950:calling FspMemoryInit 319,239 (193,169) + 951:returning from FspMemoryInit 17,456,411 (17,137,171) -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Mar 2020 15:02:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/libretrend/lt1000: Add Libretrend LT1000 board support
by Michał Żygowski (Code Review) 06 Mar '20

06 Mar '20

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Change in coreboot[master]: mb/libretrend/lt1000: Add Libretrend LT1000 board support
by Michał Żygowski (Code Review) 06 Mar '20

06 Mar '20

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: mb/libretrend/lt1000: Add Libretrend LT1000 board support ...................................................................... Patch Set 15: (4 comments) https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… File Documentation/mainboard/libretrend/lt1000.jpg: PS13: > Hmm, my intention was to show as much as possible. […] Added some better quality image https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… File Documentation/mainboard/libretrend/lt1000.md: https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… PS13, Line 47: Fastboot > Thanks. I suggest to use *Fastboot (MRC cache)* then. Done https://review.coreboot.org/c/coreboot/+/30360/13/Documentation/mainboard/l… PS13, Line 62: - speakers and mic header > Thanks, maybe add that it works in GNU/Linux (version). Done https://review.coreboot.org/c/coreboot/+/30360/13/src/mainboard/libretrend/… File src/mainboard/libretrend/lt1000/acpi/mainboard.asl: https://review.coreboot.org/c/coreboot/+/30360/13/src/mainboard/libretrend/… PS13, Line 1: /* > Great, will remove it then. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Mar 2020 14:35:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/libretrend/lt1000: Add Libretrend LT1000 board support
by Michał Żygowski (Code Review) 06 Mar '20

06 Mar '20

Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Patrick Rudolph, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30360 to look at the new patch set (#15). Change subject: mb/libretrend/lt1000: Add Libretrend LT1000 board support ...................................................................... mb/libretrend/lt1000: Add Libretrend LT1000 board support Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/libretrend/lt1000.jpg A Documentation/mainboard/libretrend/lt1000.md M MAINTAINERS A configs/config.libretrend_lt1000 A src/mainboard/libretrend/Kconfig A src/mainboard/libretrend/Kconfig.name A src/mainboard/libretrend/lt1000/Kconfig A src/mainboard/libretrend/lt1000/Kconfig.name A src/mainboard/libretrend/lt1000/Makefile.inc A src/mainboard/libretrend/lt1000/acpi/ec.asl A src/mainboard/libretrend/lt1000/acpi/mainboard.asl A src/mainboard/libretrend/lt1000/acpi/superio.asl A src/mainboard/libretrend/lt1000/board_info.txt A src/mainboard/libretrend/lt1000/bootblock.c A src/mainboard/libretrend/lt1000/data.vbt A src/mainboard/libretrend/lt1000/devicetree.cb A src/mainboard/libretrend/lt1000/dsdt.asl A src/mainboard/libretrend/lt1000/gma-mainboard.ads A src/mainboard/libretrend/lt1000/gpio.h A src/mainboard/libretrend/lt1000/hda_verb.c A src/mainboard/libretrend/lt1000/ramstage.c A src/mainboard/libretrend/lt1000/romstage.c 23 files changed, 938 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/30360/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/smm: add Kconfig for TCO SMI
by Paul Menzel (Code Review) 06 Mar '20

06 Mar '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39326 ) Change subject: soc/intel/common/block/smm: add Kconfig for TCO SMI ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id22777e9573376e5a079a375400caa687bc41afb Gerrit-Change-Number: 39326 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Mar 2020 11:55:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/skylake_sp: update header files
by Jonathan Zhang (Code Review) 06 Mar '20

06 Mar '20

Hello Anjaneya "Reddy" Chagam, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39287 to review the following change. Change subject: vendorcode/intel/fsp/fsp2_0/skylake_sp: update header files ...................................................................... vendorcode/intel/fsp/fsp2_0/skylake_sp: update header files Added more definitions in FspmUpd.h. Added gpio_fsp.h file which has definitions needed by mainboard gpio header file, to set gpio configuration through FSP-M UPD. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Tested-by: johnny_lin(a)wiwynn.com Change-Id: I72727952685b5e453f4cde6c2e7e7fc7114c6884 --- M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/skylake_sp/gpio_fsp.h 2 files changed, 250 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/39287/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h index 80ca157..0de0fa1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h @@ -45,6 +45,51 @@ #define MAX_CHANNEL 6 /* Maximum Number of Memory Channels */ #define MAX_DIMM 2 /* Maximum Number of DIMMs per Channel */ +#define HIDE 1 +#define NOT_HIDE 0 + +#define IIO_BIFURCATE_AUTO 0xFF + +/* Ports 1D-1A, 2D-2A, 3D-3A */ +#define IIO_BIFURCATE_x4x4x4x4 0 +#define IIO_BIFURCATE_x4x4xxx8 1 +#define IIO_BIFURCATE_xxx8x4x4 2 +#define IIO_BIFURCATE_xxx8xxx8 3 +#define IIO_BIFURCATE_xxxxxx16 4 +#define IIO_BIFURCATE_xxxxxxxx 0xF + + +typedef enum { + IioPortA = 0, + IioPortB = 1, + IioPortC = 2, + IioPortD = 3 +} IIO_PORTS; + +/** + * Enums and Macro definitions needed for reference RVP and CRB + * table declarations +**/ +typedef enum { + Iio_Socket0 = 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 = 0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + /** IIO PCIe Ports **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/gpio_fsp.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/gpio_fsp.h new file mode 100644 index 0000000..be9d33f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/gpio_fsp.h @@ -0,0 +1,205 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _GPIO_FSP_H_ +#define _GPIO_FSP_H_ + +// +// Below defines are based on GPIO_CONFIG structure fields +// +#define GPIO_CONF_PAD_MODE_MASK 0xF +#define GPIO_CONF_PAD_MODE_BIT_POS 0 +#define GPIO_CONF_HOST_OWN_MASK 0x3 +#define GPIO_CONF_HOST_OWN_BIT_POS 0 +#define GPIO_CONF_DIR_MASK 0x7 +#define GPIO_CONF_DIR_BIT_POS 0 +#define GPIO_CONF_INV_MASK 0x18 +#define GPIO_CONF_INV_BIT_POS 3 +#define GPIO_CONF_OUTPUT_MASK 0x3 +#define GPIO_CONF_OUTPUT_BIT_POS 0 +#define GPIO_CONF_INT_ROUTE_MASK 0x1F +#define GPIO_CONF_INT_ROUTE_BIT_POS 0 +#define GPIO_CONF_INT_TRIG_MASK 0xE0 +#define GPIO_CONF_INT_TRIG_BIT_POS 5 +#define GPIO_CONF_RESET_MASK 0x7 +#define GPIO_CONF_RESET_BIT_POS 0 +#define GPIO_CONF_TERM_MASK 0x1F +#define GPIO_CONF_TERM_BIT_POS 0 +#define GPIO_CONF_PADTOL_MASK 0x60 +#define GPIO_CONF_PADTOL_BIT_POS 5 +#define GPIO_CONF_LOCK_MASK 0x7 +#define GPIO_CONF_LOCK_BIT_POS 0 +#define GPIO_CONF_RXRAW_MASK 0x3 +#define GPIO_CONF_RXRAW_BIT_POS 0 + +typedef enum { GpioHardwareDefault = 0x0 } GPIO_HARDWARE_DEFAULT; + +/// +/// GPIO Pad Mode +/// +typedef enum { + GpioPadModeGpio = 0x1, + GpioPadModeNative1 = 0x3, + GpioPadModeNative2 = 0x5, + GpioPadModeNative3 = 0x7, + GpioPadModeNative4 = 0x9 +} GPIO_PAD_MODE; + +/// +/// Host Software Pad Ownership modes +/// +typedef enum { + GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified + GpioHostOwnAcpi = 0x1, ///< Set HOST ownership to ACPI + GpioHostOwnGpio = 0x3 ///< Set HOST ownership to GPIO +} GPIO_HOSTSW_OWN; + +/// +/// GPIO Direction +/// +typedef enum { + GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified + GpioDirInOut = + (0x1 | (0x1 << 3)), ///< Set pad for both output and input + GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and + ///input with inversion + GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only + GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion + GpioDirOut = 0x5, ///< Set pad for output only + GpioDirNone = 0x7 ///< Disable both output and input +} GPIO_DIRECTION; + +/// +/// GPIO Output State +/// +typedef enum { + GpioOutDefault = 0x0, ///< Leave output value unmodified + GpioOutLow = 0x1, ///< Set output to low + GpioOutHigh = 0x3 ///< Set output to high +} GPIO_OUTPUT_STATE; + +/// +/// GPIO interrupt configuration +/// This setting is applicable only if GPIO is in input mode. +/// GPIO_INT_CONFIG allows to choose which interrupt is generated +/// (IOxAPIC/SCI/SMI/NMI) +/// and how it is triggered (edge or level). +/// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to +/// GpioIntBothEdgecan +/// to describe an interrupt e.g. GpioIntApic | GpioIntLevel +/// If GPIO is set to cause an SCI then also Gpe is enabled for this pad. +/// Not all GPIO are capable of generating an SMI or NMI interrupt +/// + +typedef enum { + GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified + GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation + GpioIntNmi = 0x3, ///< Enable NMI interrupt only + GpioIntSmi = 0x5, ///< Enable SMI interrupt only + GpioIntSci = 0x9, ///< Enable SCI interrupt only + GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only + GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered + GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of + ///edge depends on input inversion) + GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger + GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered +} GPIO_INT_CONFIG; + +/// +/// GPIO Power Configuration +/// GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified +/// Pad Register fields). +/// +typedef enum { + GpioResetDefault = 0x0, ///< Leave value of pad reset unmodified + GpioResetPwrGood = 0x1, ///< Powergood reset + GpioResetDeep = 0x3, ///< Deep GPIO Reset + GpioResetNormal = 0x5, ///< GPIO Reset + GpioResetResume = 0x7 ///< Resume Reset (applicable only for GPD group) +} GPIO_RESET_CONFIG; + +/// +/// GPIO Electrical Configuration +/// Set GPIO termination and Pad Tolerance (applicable only for some pads) +/// Field from GpioTermDefault to GpioTermNative can be OR'ed with +/// GpioTolerance1v8. +/// +typedef enum { + GpioTermDefault = 0x0, ///< Leave termination setting unmodified + GpioTermNone = 0x1, ///< none + GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down + GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down + GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up + GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up + GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up + GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up + GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up + GpioTermNative = 0x1F, ///< Native function controls pads termination + GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance + GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance +} GPIO_ELECTRICAL_CONFIG; + +/// +/// GPIO LockConfiguration +/// Set GPIO configuration lock and output state lock +/// GpioLockPadConfig and GpioLockOutputState can be OR'ed +/// +typedef enum { + GpioLockDefault = 0x0, ///< Leave lock setting unmodified + GpioPadConfigLock = 0x3, ///< Lock Pad Configuration + GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value +} GPIO_LOCK_CONFIG; + +/// +/// Other GPIO Configuration +/// GPIO_OTHER_CONFIG is used for less often settings and for future extensions +/// Supported settings: +/// - RX raw override to '1' - allows to override input value to '1' +/// This setting is applicable only if in input mode (both in GPIO and +/// native usage). +/// The override takes place at the internal pad state directly from buffer +/// and before the RXINV. +/// +typedef enum { + GpioRxRaw1Default = 0x0, ///< Use default input override value + GpioRxRaw1Dis = 0x1, ///< Don't override input + GpioRxRaw1En = 0x3 ///< Override input to '1' +} GPIO_OTHER_CONFIG; + +// +// Possible values of Pad Ownership +// +typedef enum { + GpioPadOwnHost = 0x0, + GpioPadOwnCsme = 0x1, + GpioPadOwnIsh = 0x2, +} GPIO_PAD_OWN; + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/39287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72727952685b5e453f4cde6c2e7e7fc7114c6884 Gerrit-Change-Number: 39287 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: Add support for OCP platform TiogaPass
by Jonathan Zhang (Code Review) 06 Mar '20

06 Mar '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38549 ) Change subject: Add support for OCP platform TiogaPass ...................................................................... Add support for OCP platform TiogaPass OCP platform Tiogapass is a 2 socket server platform based on Intel Skylake-SP SOC. The chipset includes Lewisburg PCH. Following ACPI tables are added: DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR This patchset was tested on a board. It booted with Linux kernel 4.16.0; lscpu command shows all 72 cpus; ifconfig command shows networking is up from Mellanox ConnectX-4 PCIe NIC card. Known issues: 1. MP init does not work reliably, this causes reboot stability, eg. some reboots does not boot up successfully. 2. c6 state is not supported. 3. "lspci -vvv" causes segmentation fault. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce --- A src/mainboard/ocp/Kconfig A src/mainboard/ocp/Kconfig.name A src/mainboard/ocp/tiogapass/Kconfig A src/mainboard/ocp/tiogapass/Kconfig.name A src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/acpi/platform.asl A src/mainboard/ocp/tiogapass/acpi_tables.c A src/mainboard/ocp/tiogapass/board_info.txt A src/mainboard/ocp/tiogapass/boardid.c A src/mainboard/ocp/tiogapass/devicetree.cb A src/mainboard/ocp/tiogapass/dsdt.asl A src/mainboard/ocp/tiogapass/emmc.h A src/mainboard/ocp/tiogapass/fadt.c A src/mainboard/ocp/tiogapass/ramstage.c A src/mainboard/ocp/tiogapass/romstage.c A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h A src/mainboard/ocp/tiogapass/tiogapass_boardid.h A src/mainboard/ocp/tiogapass/vboot-ro.fmd 19 files changed, 1,321 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/1 diff --git a/src/mainboard/ocp/Kconfig b/src/mainboard/ocp/Kconfig new file mode 100644 index 0000000..b748129 --- /dev/null +++ b/src/mainboard/ocp/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_OCP + +choice + prompt "Mainboard model" + +source "src/mainboard/ocp/*/Kconfig.name" + +endchoice + +source "src/mainboard/ocp/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Open Compute Project" + +endif # VENDOR_OCP diff --git a/src/mainboard/ocp/Kconfig.name b/src/mainboard/ocp/Kconfig.name new file mode 100644 index 0000000..f5d8d0a --- /dev/null +++ b/src/mainboard/ocp/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_OCP + bool "Open Compute Project" diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig new file mode 100644 index 0000000..b2517b0 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation. +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_OCP_TIOGAPASS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_TABLES + select SOC_INTEL_SKYLAKE_SP + select SKYLAKE_SP_SOC_PCH_H + select MAINBOARD_USES_FSP2_0 + select FSP_CAR + +config MAINBOARD_DIR + string + default "ocp/tiogapass" + +config MAINBOARD_PART_NUMBER + string + default "Tioga Pass" + +config MAINBOARD_FAMILY + string + default "OCP Tioga Pass" + +config MAINBOARD_VENDOR + string + default "OCP" + +config MAX_SOCKET + int + default 2 + +config FLIGHT_PLAN_TIMEOUT_US + int + default 10000000 + +endif # BOARD_OCP_TIOGAPASS diff --git a/src/mainboard/ocp/tiogapass/Kconfig.name b/src/mainboard/ocp/tiogapass/Kconfig.name new file mode 100644 index 0000000..0c57fd3 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_OCP_TIOGAPASS + bool "Tioga Pass" diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc new file mode 100644 index 0000000..b09b35e --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation. +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += boardid.c + +ramstage-y += ramstage.c +ramstage-y += boardid.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c + +CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ +CPPFLAGS_common += -I$(src)/soc/intel/skylake_sp/include +CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl new file mode 100644 index 0000000..5bbe4ae --- /dev/null +++ b/src/mainboard/ocp/tiogapass/acpi/platform.asl @@ -0,0 +1,382 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> + +Name (_S0, Package (0x04) // mandatory system state +{ + 0x00, 0x00, 0x00, 0x00 +}) + +Name (_S5, Package (0x04) // mandatory system state +{ + 0x07, 0x00, 0x00, 0x00 +}) + +/* The APM port can be used for generating software SMIs */ +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ +OperationRegion (DBG0, SystemIO, 0x80, 0x02) +Field (DBG0, ByteAcc, Lock, Preserve) +{ + IO80, 8, + IO81, 8 +} + +/* IO-Trap at 0x800. + * This is the ACPI->SMI communication interface. + */ +OperationRegion (IO_T, SystemIO, 0x800, 0x10) +Field (IO_T, ByteAcc, NoLock, Preserve) +{ + Offset (0x8), + TRP0, 8 /* IO-Trap at 0x808 */ +} + +OperationRegion (PSYS, SystemMemory, 0x6D081000, 0x0400) +Field (PSYS, ByteAcc, NoLock, Preserve) +{ + PLAT, 32, // Platform ID + + // IOAPIC + APC0, 1, // PCH IOAPIC Enable + AP00, 1, // PC00 IOAPIC Enable + AP01, 1, // PC01 IOAPIC Enable + AP02, 1, // PC02 IOAPIC Enable + AP03, 1, // PC03 IOAPIC Enable + AP04, 1, // PC04 IOAPIC Enable + AP05, 1, // PC05 IOAPIC Enable + AP06, 1, // PC06 IOAPIC Enable + AP07, 1, // PC07 IOAPIC Enable + AP08, 1, // PC08 IOAPIC Enable + AP09, 1, // PC09 IOAPIC Enable + AP10, 1, // PC10 IOAPIC Enable + AP11, 1, // PC11 IOAPIC Enable + AP12, 1, // PC12 IOAPIC Enable + AP13, 1, // PC13 IOAPIC Enable + AP14, 1, // PC14 IOAPIC Enable + AP15, 1, // PC15 IOAPIC Enable + AP16, 1, // PC16 IOAPIC Enable + AP17, 1, // PC17 IOAPIC Enable + AP18, 1, // PC18 IOAPIC Enable + AP19, 1, // PC19 IOAPIC Enable + AP20, 1, // PC20 IOAPIC Enable + AP21, 1, // PC21 IOAPIC Enable + AP22, 1, // PC22 IOAPIC Enable + AP23, 1, // PC23 IOAPIC Enable + RESA, 7, + SKOV, 1, // Override Socket APIC Id + RES0, 7, + + // Power Management + TPME, 1, + CSEN, 1, + C3EN, 1, + C6EN, 1, + C7EN, 1, + MWOS, 1, + PSEN, 1, + EMCA, 1, + HWAL, 2, + KPRS, 1, + MPRS, 1, + TSEN, 1, + FGTS, 1, + OSCX, 1, + RESX, 1, + + // RAS + CPHP, 8, + IIOP, 8, + IIOH, 64, + PRBM, 32, + P0ID, 32, + P1ID, 32, + P2ID, 32, + P3ID, 32, + P4ID, 32, + P5ID, 32, + P6ID, 32, + P7ID, 32, + P0BM, 64, + P1BM, 64, + P2BM, 64, + P3BM, 64, + P4BM, 64, + P5BM, 64, + P6BM, 64, + P7BM, 64, + MEBM, 16, + MEBC, 16, + CFMM, 32, + TSSY, 32, // TODO: This is TSSZ in system booted from production FW + M0BS, 64, + M1BS, 64, + M2BS, 64, + M3BS, 64, + M4BS, 64, + M5BS, 64, + M6BS, 64, + M7BS, 64, + M0RN, 64, + M1RN, 64, + M2RN, 64, + M3RN, 64, + M4RN, 64, + M5RN, 64, + M6RN, 64, + M7RN, 64, + SMI0, 32, + SMI1, 32, + SMI2, 32, + SMI3, 32, + SCI0, 32, + SCI1, 32, + SCI2, 32, + SCI3, 32, + MADD, 64, + CUU0, 128, + CUU1, 128, + CUU2, 128, + CUU3, 128, + CUU4, 128, + CUU5, 128, + CUU6, 128, + CUU7, 128, + CPSP, 8, + ME00, 128, + ME01, 128, + ME10, 128, + ME11, 128, + ME20, 128, + ME21, 128, + ME30, 128, + ME31, 128, + ME40, 128, + ME41, 128, + ME50, 128, + ME51, 128, + ME60, 128, + ME61, 128, + ME70, 128, + ME71, 128, + MESP, 16, + LDIR, 64, + PRID, 32, + AHPE, 8, + + // VTD + DHRD, 192, + ATSR, 192, + RHSA, 192, + + // SR-IOV + WSIC, 8, + WSIS, 16, + WSIB, 8, + WSID, 8, + WSIF, 8, + WSTS, 8, + WHEA, 8, + + // BIOS Guard + BGMA, 64, + BGMS, 8, + BGIO, 16, + BGIL, 8, + CNBS, 8, + + // USB3 + XHMD, 8, + SBV1, 8, + SBV2, 8, + + // HWPM + HWEN, 2, + ACEN, 1, + HWPI, 1, + RES1, 4, + + // IIO + BB00, 8, + BB01, 8, + BB02, 8, + BB03, 8, + BB04, 8, + BB05, 8, + BB06, 8, + BB07, 8, + BB08, 8, + BB09, 8, + BB10, 8, + BB11, 8, + BB12, 8, + BB13, 8, + BB14, 8, + BB15, 8, + BB16, 8, + BB17, 8, + BB18, 8, + BB19, 8, + BB20, 8, + BB21, 8, + BB22, 8, + BB23, 8, + BB24, 8, + BB25, 8, + BB26, 8, + BB27, 8, + BB28, 8, + BB29, 8, + BB30, 8, + BB31, 8, + BB32, 8, + BB33, 8, + BB34, 8, + BB35, 8, + BB36, 8, + BB37, 8, + BB38, 8, + BB39, 8, + BB40, 8, + BB41, 8, + BB42, 8, + BB43, 8, + BB44, 8, + BB45, 8, + BB46, 8, + BB47, 8, + SGEN, 8, + SG00, 8, + SG01, 8, + SG02, 8, + SG03, 8, + SG04, 8, + SG05, 8, + SG06, 8, + SG07, 8, + + // Performance + CLOD, 8, + + // XTU + XTUB, 32, + XTUS, 32, + XMBA, 32, + DDRF, 8, + RT3S, 8, + RTP0, 8, + RTP3, 8, + + // FPGA + FBB0, 8, + FBB1, 8, + FBB2, 8, + FBB3, 8, + FBB4, 8, + FBB5, 8, + FBB6, 8, + FBB7, 8, + FBL0, 8, + FBL1, 8, + FBL2, 8, + FBL3, 8, + FBL4, 8, + FBL5, 8, + FBL6, 8, + FBL7, 8, + P0FB, 8, + P1FB, 8, + P2FB, 8, + P3FB, 8, + P4FB, 8, + P5FB, 8, + P6FB, 8, + P7FB, 8, + FMB0, 32, + FMB1, 32, + FMB2, 32, + FMB3, 32, + FMB4, 32, + FMB5, 32, + FMB6, 32, + FMB7, 32, + FML0, 32, + FML1, 32, + FML2, 32, + FML3, 32, + FML4, 32, + FML5, 32, + FML6, 32, + FML7, 32, + FKPB, 32, + FKB0, 8, + FKB1, 8, + FKB2, 8, + FKB3, 8, + FKB4, 8, + FKB5, 8, + FKB6, 8, + FKB7, 8 +} + +/* SMI I/O Trap */ +Method (TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method (_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store (Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c new file mode 100644 index 0000000..93f659a --- /dev/null +++ b/src/mainboard/ocp/tiogapass/acpi_tables.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <types.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <cpu/x86/msr.h> + +#include <intelblocks/acpi.h> +#include <soc/acpi.h> +#include <soc/nvs.h> + +extern const unsigned char AmlCode[]; + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* TPM Present */ + gnvs->tpmp = 0; +} diff --git a/src/mainboard/ocp/tiogapass/board_info.txt b/src/mainboard/ocp/tiogapass/board_info.txt new file mode 100644 index 0000000..e86f78f --- /dev/null +++ b/src/mainboard/ocp/tiogapass/board_info.txt @@ -0,0 +1,5 @@ +Board name: TiogaPass +Category: server +ROM protocol: SPI +ROM socketed: yes +Release year: 2018 diff --git a/src/mainboard/ocp/tiogapass/boardid.c b/src/mainboard/ocp/tiogapass/boardid.c new file mode 100644 index 0000000..a0454cb --- /dev/null +++ b/src/mainboard/ocp/tiogapass/boardid.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> + +#include "tiogapass_boardid.h" + +uint8_t board_id(void) +{ + int id = BoardIdTiogaPass; + + printk(BIOS_SPEW, "Board ID: %#x.\n", id); + + return id; +} diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb new file mode 100644 index 0000000..7409f55 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -0,0 +1,92 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation. +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake_sp + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # configure device interrupt routing + register "ir00_routing" = "0x3210" # IR00, Dev31 + register "ir01_routing" = "0x3210" # IR01, Dev30 + register "ir02_routing" = "0x3210" # IR02, Dev29 + register "ir03_routing" = "0x3210" # IR03, Dev28 + register "ir04_routing" = "0x3210" # IR04, Dev27 + + # configure interrupt polarity control + register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow + register "ipc1" = "0x00000000" # IPC1 + register "ipc2" = "0x00000000" # IPC2 + register "ipc3" = "0x00000000" # IPC3 + + # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs + # FB production turbo_ratio_limit is 0x1f1f1f2022222325 + register "turbo_ratio_limit" = "0x1b1b1b1d20222325" + # FB production turbo_ratio_limit_cores is 0x1c1812100c080402 + register "turbo_ratio_limit_cores" = "0x1c1814100c080402" + + # configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL + register "pstate_req_ratio" = "0xa" + + # configure VTD + register "vtd_support" = "1" + register "coherency_support" = "1" + register "ats_support" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 04.0 on end # Intel Corporation Sky Lake-E CBDMA Registers + device pci 04.1 on end # Intel Corporation Sky Lake-E CBDMA Registers + device pci 04.2 on end # Intel Corporation Sky Lake-E CBDMA Registers + device pci 04.3 on end # Intel Corporation Sky Lake-E CBDMA Registers + device pci 04.4 on end # Intel Corporation Sky Lake-E CBDMA Registers + device pci 04.5 on end # Intel Corporation Sky Lake-E CBDMA Registers + device pci 04.6 on end # Intel Corporation Sky Lake-E CBDMA Registers + device pci 04.7 on end # Intel Corporation Sky Lake-E CBDMA Registers + device pci 05.0 on end # Intel Corporation Sky Lake-E MM/Vt-d Configuration Registers + device pci 05.2 on end # Intel Corporation Device 2025 + device pci 05.4 on end # Intel Corporation Device 2026 + device pci 08.0 on end # Intel Corporation Sky Lake-E Ubox Registers + device pci 08.1 on end # Intel Corporation Sky Lake-E Ubox Registers + device pci 08.2 on end # Intel Corporation Sky Lake-E Ubox Registers + device pci 11.0 on end # Intel Corporation C620 Series Chipset Family MROM 0 + device pci 11.1 on end # Intel Corporation C620 Series Chipset Family MROM 1 + device pci 11.5 on end # Intel Corporation C620 Series Chipset Family SSATA Controller [AHCI mode] + device pci 14.0 on end # Intel Corporation C620 Series Chipset Family USB 3.0 xHCI Controller +# device pci 14.2 on end # Intel Corporation C620 Series Chipset Family Thermal Subsystem + device pci 16.0 on end # Intel Corporation C620 Series Chipset Family MEI Controller #1 + device pci 16.1 on end # Intel Corporation C620 Series Chipset Family MEI Controller #2 + device pci 16.4 on end # Intel Corporation C620 Series Chipset Family MEI Controller #3 + device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode] + device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1 + device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5 + device pci 1f.0 on end # Intel Corporation C621 Series Chipset LPC/eSPI Controller + device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller + device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus + device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller + end +end diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl new file mode 100644 index 0000000..bf36ab9 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // platform ACPI tables + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/skylake_sp/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + // Xeon Skylake SP ACPI tables + Scope (\_SB) { + #include <soc/intel/skylake_sp/acpi/uncore.asl> + } +} diff --git a/src/mainboard/ocp/tiogapass/emmc.h b/src/mainboard/ocp/tiogapass/emmc.h new file mode 100644 index 0000000..5f5816b --- /dev/null +++ b/src/mainboard/ocp/tiogapass/emmc.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_EMMC_H +#define _MAINBOARD_EMMC_H + +#include <fsp/util.h> + +/* + * eMMC DLL structure for EMMC DLL registers settings + */ +typedef struct { + UINT32 TxCmdCntl; + UINT32 TxDataCntl1; + UINT32 TxDataCntl2; + UINT32 RxCmdDataCntl1; + UINT32 RxStrobeCntl; + UINT32 RxCmdDataCntl2; + UINT32 MasterSwCntl; +} BL_EMMC_DLL_CONFIG; + +typedef struct { + UINT16 Signature; + BL_EMMC_DLL_CONFIG eMMCDLLConfig; +} BL_EMMC_INFORMATION; + +#define DEFAULT_EMMC_DLL_SIGN 0x55aa + +#ifndef __ACPI__ +BL_EMMC_INFORMATION tiogapass_emmc_config[] = { + /* + * Default eMMC DLL configuration. + */ + {DEFAULT_EMMC_DLL_SIGN, + {0x00000508, 0x00000c11, 0x1c2a2a2a, 0x00191e27, 0x00000a0a, + 0x00010013, 0x00000001} } }; +#endif + +#endif /* _MAINBOARD_EMMC_H */ diff --git a/src/mainboard/ocp/tiogapass/fadt.c b/src/mainboard/ocp/tiogapass/fadt.c new file mode 100644 index 0000000..664034d --- /dev/null +++ b/src/mainboard/ocp/tiogapass/fadt.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/acpi.h> + +#include <soc/acpi.h> +#include <soc/soc_util.h> + +void motherboard_fill_fadt(acpi_fadt_t *fadt) +{ +// fadt->model = 1; + fadt->reserved = 0; + fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; +} diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c new file mode 100644 index 0000000..22a3fb3 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/api.h> +#include <soc/ramstage.h> +#include "emmc.h" + +static int get_emmc_dll_info(uint16_t signature, size_t num_of_entry, + BL_EMMC_INFORMATION **config) +{ + uint8_t entry; + + if ((signature == 0) || (num_of_entry == 0) || (*config == NULL)) + return 1; + + for (entry = 0; entry < num_of_entry; entry++) { + if ((*config)[entry].Signature == signature) { + *config = &(*config)[entry]; + return 0; + } + } + + return 1; +} + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + size_t num; + uint16_t emmc_dll_sign; + BL_EMMC_INFORMATION *emmc_config; + + /* Configure eMMC DLL PCD */ + emmc_dll_sign = DEFAULT_EMMC_DLL_SIGN; + num = ARRAY_SIZE(tiogapass_emmc_config); + emmc_config = tiogapass_emmc_config; + + if (get_emmc_dll_info(emmc_dll_sign, num, &emmc_config)) + die("eMMC DLL Configuration is invalid, please correct it!"); + + params->FspsConfig.PcdEMMCDLLConfigPtr = + (uint32_t)&emmc_config->eMMCDLLConfig; +} diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c new file mode 100644 index 0000000..af79de6 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "tiogapass_boardid.h" +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/soc_binding.h> +#include <FspmUpd.h> +#define PCH_SERVER_BIOS_FLAG 1 +#include "skxsp_tp_gpio.h" +#include "skxsp_tp_iio.h" + +void mainboard_config_gpios(FSPM_UPD * mupd); +void mainboard_config_iio(FSPM_UPD *mupd); +void mainboard_memory_init_params(FSPM_UPD *mupd); + +/* +* Configure GPIO depend on platform +*/ +void mainboard_config_gpios(FSPM_UPD *mupd) +{ + mupd->FspmConfig.GpioConfig.GpioTable = (UPD_GPIO_INIT_CONFIG *) tp_gpio_table; + mupd->FspmConfig.GpioConfig.NumberOfEntries = + sizeof(tp_gpio_table)/sizeof(UPD_GPIO_INIT_CONFIG); +} + +void mainboard_config_iio(FSPM_UPD *mupd) +{ + mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable = + (UPD_IIO_BIFURCATION_DATA_ENTRY *) tp_iio_bifur_table; + mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries = + sizeof(tp_iio_bifur_table)/sizeof(UPD_IIO_BIFURCATION_DATA_ENTRY); + + mupd->FspmConfig.IioPciConfig.ConfigurationTable = + (UPD_PCI_PORT_CONFIG *) tp_iio_pci_port_skt0; + mupd->FspmConfig.IioPciConfig.NumberOfEntries = + sizeof(tp_iio_pci_port_skt0)/sizeof(UPD_PCI_PORT_CONFIG); + + mupd->FspmConfig.PchPciConfig.PciPortConfig = + (UPD_PCH_PCIE_PORT *) tp_pch_pci_port_skt0; + mupd->FspmConfig.PchPciConfig.NumberOfEntries = + sizeof(tp_pch_pci_port_skt0)/sizeof(UPD_PCH_PCIE_PORT); + + mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00; + mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00; +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + mainboard_config_gpios(mupd); + mainboard_config_iio(mupd); +} diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h new file mode 100644 index 0000000..c6aa3f4 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h @@ -0,0 +1,301 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SKXSP_TP_GPIO_H +#define _SKXSP_TP_GPIO_H + +#include <FspmUpd.h> +#include <soc/gpio_fsp.h> +#include <soc/gpio_soc_defs.h> + +/** + * OCP TiogaPass Gpio Pad Configuration +**/ +static const UPD_GPIO_INIT_CONFIG tp_gpio_table[] = { + {GPIO_SKL_H_GPP_A0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N + {GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_1_LAD_0_ESPI_IO_0 + {GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_2_LAD_1_ESPI_IO_1 + {GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_3_LAD_2_ESPI_IO_2 + {GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_4_LAD_3_ESPI_IO_3 + {GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N + {GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N + {GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N + {GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_8_FM_LPC_CLKRUN_N + {GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK + {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_10_CLKOUT_LPC1 + {GPIO_SKL_H_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_11_FM_LPC_PME_N + {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N + {GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK + {GPIO_SKL_H_GPP_A14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_14_ESPI_RESET_N + {GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_15_SUSACK_N + {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_16_CLKOUT_LPC2 + {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_17 + {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_18 +// {GPIO_SKL_H_GPP_A19, {} }, //GPP_A_19, controlled by ME + {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_20 + {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_21 + {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_22 + {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_23 + + {GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_0_CORE_VID_0 + {GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_1_CORE_VID_1 + {GPIO_SKL_H_GPP_B2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_2_VRALERT_N + {GPIO_SKL_H_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_3_CPU_GP2 + {GPIO_SKL_H_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_4_CPU_GP3 + {GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_5_SRCCLKREQ0_N + {GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_6_SRCCLKREQ1_N + {GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_7_SRCCLKREQ2_N + {GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_8_SRCCLKREQ3_N + {GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_9_SRCCLKREQ4_N + {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_10_SRCCLKREQ5_N + {GPIO_SKL_H_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_11 + {GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_12_GLB_RST_WARN_N + {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_13_RST_PLTRST_N + {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR + {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_15 + {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_16 + {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_17 + {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_18 + {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_19 + {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_20 + {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_21 + {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_22 + {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N + +// {GPIO_SKL_H_GPP_C0, {} }, //GPP_C_0_SMBCLK, controlled by ME +// {GPIO_SKL_H_GPP_C1, {} }, //GPP_C_1_SMBDATA, controlled by ME + {GPIO_SKL_H_GPP_C2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_2_SMBALERT_N +// {GPIO_SKL_H_GPP_C3, {} }, //GPP_C_3_SML0CLK_IE, controlled by ME +// {GPIO_SKL_H_GPP_C4, {} }, //GPP_C_4_SML0DATA_IE, controlled by ME + {GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPP_C_5_SML0ALERT_IE_N +// {GPIO_SKL_H_GPP_C6, {} }, //GPP_C_6_SML1CLK_IE, controlled by ME +// {GPIO_SKL_H_GPP_C7, {} }, //GPP_C_7_SML1DATA_IE, controlled by ME + {GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_8 + {GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_9 + {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_10 + {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_11 + {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_12 + {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_13 + {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_14 + {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_15 + {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_16 + {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_17 + {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_18 + {GPIO_SKL_H_GPP_C19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_19 +// {GPIO_SKL_H_GPP_C20, {} }, //GPP_C_20, controlled by ME + {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_21 + {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_22 + {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_23 + + {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_0 + {GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_1 + {GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_2 + {GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_3 + {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_4 + {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_5 + {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_6 + {GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_7 + {GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_8 + {GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_9_SSATA_DEVSLP3 + {GPIO_SKL_H_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_10_SSATA_DEVSLP4 + {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_11_SSATA_DEVSLP5 + {GPIO_SKL_H_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_12_SSATA_SDATAOUT1 + {GPIO_SKL_H_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_13_SML0BLCK_IE + {GPIO_SKL_H_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_14_SML0BDATA_IE + {GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_15_SSATA_SDATAOUT0 + {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_16_SML0BALERT_IE_N + {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_17 + {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_18 + {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock} }, //GPP_D_19 + {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_20_TP_PCH_GPP_D_20 + {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_21_IE_URAT_RX + {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_22_IE_URAT_TX + {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_23 + + {GPIO_SKL_H_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_0_SATAXPCIE0_SATAGP0 + {GPIO_SKL_H_GPP_E1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_1_SATAXPCIE1_SATAGP1 + {GPIO_SKL_H_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_2_SATAXPCIE2_SATAGP2 + {GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_3_CPU_GP0 + {GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_4_SATA_DEVSLP0 + {GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_5_SATA_DEVSLP1 + {GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_6_SATA_DEVSLP2 + {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_7_CPU_GP1 + {GPIO_SKL_H_GPP_E8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_8_SATA_LED_N + {GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_9_USB2_OC0_N + {GPIO_SKL_H_GPP_E10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_10_USB2_OC1_N + {GPIO_SKL_H_GPP_E11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_11_USB2_OC2_N + {GPIO_SKL_H_GPP_E12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_12_USB2_OC3_N + + {GPIO_SKL_H_GPP_F0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_0_SATAXPCIE3_SATAGP3 + {GPIO_SKL_H_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_1_SATAXPCIE4_SATAGP4 + {GPIO_SKL_H_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_2_SATAXPCIE5_SATAGP5 + {GPIO_SKL_H_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_3_SATAXPCIE6_SATAGP6 + {GPIO_SKL_H_GPP_F4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_4_SATAXPCIE7_SATAGP7 + {GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_5_SATA_DEVSLP3 + {GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_6_SATA_DEVSLP4 + {GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_7_SATA_DEVSLP5 + {GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_8_SATA_DEVSLP6 + {GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_9_SATA_DEVSLP7 + {GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_10_SATA_SCLOCK + {GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_11_SATA_SLOAD + {GPIO_SKL_H_GPP_F12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_12_SATA_SDATAOUT1 + {GPIO_SKL_H_GPP_F13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_13_SATA_SDATAOUT0 + {GPIO_SKL_H_GPP_F14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_14_SSATA_LED_N + {GPIO_SKL_H_GPP_F15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_15_USB2_OC4_N + {GPIO_SKL_H_GPP_F16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_16_USB2_OC5_N + {GPIO_SKL_H_GPP_F17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_17_USB2_OC6_N + {GPIO_SKL_H_GPP_F18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_18_USB2_OC7_N + {GPIO_SKL_H_GPP_F19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_19_LAN_SMBCLK + {GPIO_SKL_H_GPP_F20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_20_LAN_SMBDATA + {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_21_LAN_SMBALERT_N + {GPIO_SKL_H_GPP_F22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_22_SSATA_SCLOCK + {GPIO_SKL_H_GPP_F23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_23_SSATA_SLOAD + + {GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_0_FANTACH0_FANTACH0IE + {GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_1_FANTACH1_FANTACH1IE + {GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_2_FANTACH2_FANTACH2IE + {GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_3_FANTACH3_FANTACH3IE + {GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_4_FANTACH4_FANTACH4IE + {GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_5_FANTACH5_FANTACH5IE + {GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_6_FANTACH6_FANTACH6IE + {GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_7_FANTACH7_FANTACH7IE + {GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_8_FANPWM0_FANPWM0IE + {GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_9_FANPWM1_FANPWM1IE + {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_10_FANPWM2_FANPWM2IE + {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_11_FANPWM3_FANPWM3IE + {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_12 + {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_13 + {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_14 + {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_15 + {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_16 + {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_17_ADR_COMPLETE + {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_18_FM_NMI_EVENT_N + {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_19_FM_SMI_ACTIVE_N +// {GPIO_SKL_H_GPP_G20, {} }, //GPP_G_20_SSATA_DEVSLP0, controlled by ME + {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_21_SSATA_DEVSLP1 + {GPIO_SKL_H_GPP_G22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_22_SSATA_DEVSLP2 + {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_23_SSATAXPCIE0_SSATAGP0 + + {GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_0_SRCCLKREQ6_N + {GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_1_SRCCLKREQ7_N + {GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_2_SRCCLKREQ8_N + {GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_3_SRCCLKREQ9_N + {GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_4_SRCCLKREQ10_N +// {GPIO_SKL_H_GPP_H5, {} }, //GPP_H_5_SRCCLKREQ11_N + {GPIO_SKL_H_GPP_H6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_6_SRCCLKREQ12_N + {GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_7_SRCCLKREQ13_N + {GPIO_SKL_H_GPP_H8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_8_SRCCLKREQ14_N + {GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_9_SRCCLKREQ15_N +// {GPIO_SKL_H_GPP_H10, {} }, //GPP_H_10_SML2CLK_IE +// {GPIO_SKL_H_GPP_H11, {} }, //GPP_H_11_SML2DATA_IE + {GPIO_SKL_H_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_12_SML2ALERT_N_IE +// {GPIO_SKL_H_GPP_H13, {} }, //GPP_H_13_SML3CLK_IE +// {GPIO_SKL_H_GPP_H14, {} }, //GPP_H_14_SML3DATA_IE + {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_15_SML3ALERT_N_IE +// {GPIO_SKL_H_GPP_H16, {} }, //GPP_H_16_SML4CLK_IE +// {GPIO_SKL_H_GPP_H17, {} }, //GPP_H_17_SML4DATA_IE + {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_18_SML4ALERT_N_IE + {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_19_SSATAXPCIE1_SSATAGP1 + {GPIO_SKL_H_GPP_H20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_20_SSATAXPCIE2_SSATAGP2 + {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_21_SSATAXPCIE3_SSATAGP3 + {GPIO_SKL_H_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_22_SSATAXPCIE4_SSATAGP4 + {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_23_SSATAXPCIE5_SSATAGP5 + + {GPIO_SKL_H_GPP_I0, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_0_GBE_TDO + {GPIO_SKL_H_GPP_I1, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_1_GBE_TCK + {GPIO_SKL_H_GPP_I2, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_2_GBE_TMS + {GPIO_SKL_H_GPP_I3, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_3_GBE_TDI + {GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_4_DO_RESET_IN_N + {GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_5_DO_RESET_OUT_N + {GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_6_RESET_DONE + {GPIO_SKL_H_GPP_I7, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_7_JTAG_GBE_TRST_N + {GPIO_SKL_H_GPP_I8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_8_GBE_PCI_DIS + {GPIO_SKL_H_GPP_I9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_9_GBE_LAN_DIS + {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_10 + + {GPIO_SKL_H_GPP_J0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_0_LAN_LED_P0_0 + {GPIO_SKL_H_GPP_J1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_1_LAN_LED_P0_1 + {GPIO_SKL_H_GPP_J2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_2_LAN_LED_P1_0 + {GPIO_SKL_H_GPP_J3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_3_LAN_LED_P1_1 + {GPIO_SKL_H_GPP_J4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_4_LAN_LED_P2_0 + {GPIO_SKL_H_GPP_J5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_5_LAN_LED_P2_1 + {GPIO_SKL_H_GPP_J6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_6_LAN_LED_P3_0 + {GPIO_SKL_H_GPP_J7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_7_LAN_LED_P3_1 + {GPIO_SKL_H_GPP_J8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_8_LAN_I2C_SCL_MDC_P0 + {GPIO_SKL_H_GPP_J9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0 + {GPIO_SKL_H_GPP_J10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_10_LAN_I2C_SCL_MDC_P1 + {GPIO_SKL_H_GPP_J11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1 + {GPIO_SKL_H_GPP_J12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_12_LAN_I2C_SCL_MDC_P2 + {GPIO_SKL_H_GPP_J13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2 + {GPIO_SKL_H_GPP_J14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_14_LAN_I2C_SCL_MDC_P3 + {GPIO_SKL_H_GPP_J15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3 + {GPIO_SKL_H_GPP_J16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_16_LAN_SDP_P0_0 + {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_17_LAN_SDP_P0_1 + {GPIO_SKL_H_GPP_J18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_18_LAN_SDP_P1_0 + {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_19_LAN_SDP_P1_1 + {GPIO_SKL_H_GPP_J20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_20_LAN_SDP_P2_0 + {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_21_LAN_SDP_P2_1 + {GPIO_SKL_H_GPP_J22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_22_LAN_SDP_P3_0 + {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_23_LAN_SDP_P3_1 + + {GPIO_SKL_H_GPP_K0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_0_LAN_NCSI_CLK_IN + {GPIO_SKL_H_GPP_K1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_1_LAN_NCSI_TXD0 + {GPIO_SKL_H_GPP_K2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_2_LAN_NCSI_TXD1 + {GPIO_SKL_H_GPP_K3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_3_LAN_NCSI_TX_EN + {GPIO_SKL_H_GPP_K4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_4_LAN_NCSI_CRS_DV + {GPIO_SKL_H_GPP_K5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_5_LAN_NCSI_RXD0 + {GPIO_SKL_H_GPP_K6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_6_LAN_NCSI_RXD1 + {GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_7 + {GPIO_SKL_H_GPP_K8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_8_LAN_NCSI_ARB_IN + {GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_9_LAN_NCSI_ARB_OUT + {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_10_PE_RST_N + + {GPIO_SKL_H_GPP_L2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_2_TESTCH0_D0 + {GPIO_SKL_H_GPP_L3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_3_TESTCH0_D1 + {GPIO_SKL_H_GPP_L4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_4_TESTCH0_D2 + {GPIO_SKL_H_GPP_L5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_5_TESTCH0_D3 + {GPIO_SKL_H_GPP_L6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_6_TESTCH0_D4 + {GPIO_SKL_H_GPP_L7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_7_TESTCH0_D5 + {GPIO_SKL_H_GPP_L8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_8_TESTCH0_D6 + {GPIO_SKL_H_GPP_L9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_9_TESTCH0_D7 + {GPIO_SKL_H_GPP_L10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_10_TESTCH0_CLK + {GPIO_SKL_H_GPP_L11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_11_TESTCH1_D0 + {GPIO_SKL_H_GPP_L12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_12_TESTCH1_D1 + {GPIO_SKL_H_GPP_L13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_13_TESTCH1_D2 + {GPIO_SKL_H_GPP_L14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_14_TESTCH1_D3 + {GPIO_SKL_H_GPP_L15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_15_TESTCH1_D4 + {GPIO_SKL_H_GPP_L16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_16_TESTCH1_D5 + {GPIO_SKL_H_GPP_L17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_17_TESTCH1_D6 + {GPIO_SKL_H_GPP_L18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_18_TESTCH1_D7 + {GPIO_SKL_H_GPP_L19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_19_TESTCH1_CLK + + {GPIO_SKL_H_GPD0, {} }, //GPD_0, controlled by ME + {GPIO_SKL_H_GPD1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_1_ACPRESENT + {GPIO_SKL_H_GPD2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_2_GBE_WAKE_N + {GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_3_PWRBTNB_N + {GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_4_SLP_S3B + {GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_5_SLP_S4B + {GPIO_SKL_H_GPD6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_6_SLPA_N + {GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_7 + {GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD + {GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_9 + {GPIO_SKL_H_GPD10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_10_FM_SLPS5_N + {GPIO_SKL_H_GPD11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_11_GBEPHY +}; + +#endif diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h new file mode 100644 index 0000000..ac0fe99 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SKXSP_TP_IIO_H +#define _SKXSP_TP_IIO_H + +#include <FspmUpd.h> +#include <soc/pci_devs.h> + +/** + * Standard Tioga Pass Iio Bifurcation Table + * This is SS 2x16 config. As documented in OCP TP spec, there are + * 3 configs. SS 2x16 is the most common. + * TODO: figure out config through board SKU ID and through PCIe + * config GPIO setting (SLT_CFG0 / SLT_CFG1). +**/ +static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = { + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, /* 1A x16 */ + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, /* 2A x16 */ + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, /* 3A x16 */ + { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ + { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxxxx }, /* no IOU0 */ + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxxxx }, /* no IOU1 */ + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, /* 3A x8, 3C x8 */ + { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ + { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ +}; + +/** + * Standard Tioga Pass Iio PCIe Port Table +**/ +static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = { + // PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd | NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride + { PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 }, + { PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 }, + { PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 }, + { PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 }, + { PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 }, + { PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 }, + { PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 }, + { PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 }, + { PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 }, + { PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 }, + { PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 }, + { PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 }, +}; + +/** + * Standard Tioga Pass PCH PCIe Port Table +**/ +static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0[] = { + //PortIndex ; ForceEnable ; PortLinkSpeed + { 0x00, 0x01, PcieAuto }, + { 0x04, 0x01, PcieAuto }, + { 0x05, 0x01, PcieAuto }, +}; + +#endif // end of _SKXSP_TP_IIO_H diff --git a/src/mainboard/ocp/tiogapass/tiogapass_boardid.h b/src/mainboard/ocp/tiogapass/tiogapass_boardid.h new file mode 100644 index 0000000..39dc7b3 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/tiogapass_boardid.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef TIOGAPASS_MAINBOARD_BOARD_H +#define TIOGAPASS_MAINBOARD_BOARD_H + +#include <stdint.h> + +#define BoardIdTiogaPass 0x52 + +uint8_t board_id(void); + +#endif /* MAINBOARD_BOARD_H */ diff --git a/src/mainboard/ocp/tiogapass/vboot-ro.fmd b/src/mainboard/ocp/tiogapass/vboot-ro.fmd new file mode 100644 index 0000000..30551fe --- /dev/null +++ b/src/mainboard/ocp/tiogapass/vboot-ro.fmd @@ -0,0 +1,23 @@ +FLASH 32M { + # ME takes 16MB. + SI_ALL@0x0 0x1000000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0xfff000 + } + SI_BIOS@0x1000000 0x1000000 { + MISC_RW@0x0 0x20000 { + RW_MRC_CACHE@0x0 0x10000 + RW_VPD(PRESERVE)@0x010000 0x4000 + } + WP_RO@0x020000 0xfe0000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0xfdc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0xfd7000 + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce Gerrit-Change-Number: 38549 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

10 68

Change in coreboot[master]: ec/google/chromeec: Fix dev ops for chromeec
by Furquan Shaikh (Code Review) 06 Mar '20

06 Mar '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39321 ) Change subject: ec/google/chromeec: Fix dev ops for chromeec ...................................................................... ec/google/chromeec: Fix dev ops for chromeec CB:38541 ("ec/google/chromeec: Add SSDT generator for ChromeOS EC") added a new device_operations structure for chromeec for handling ACPI SSDT generation. However, this resulted in the original device_operations which handled lpc read resources to be skipped. This change fixes the above regression by combining the device operations for reading resources and ACPI SSDT generation into a single structure and retains the old logic for enabling of pnp devices. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I3a242f4b15603f957e0e81d121e5766fccf3c28d --- M src/ec/google/chromeec/Makefile.inc M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h D src/ec/google/chromeec/ec_chip.c M src/ec/google/chromeec/ec_lpc.c 5 files changed, 12 insertions(+), 261 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39321/1 diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 2833c87..590b131 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -28,7 +28,7 @@ verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_chip.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_acpi.c ramstage-$(CONFIG_VBOOT) += vboot_storage.c smm-$(CONFIG_VBOOT) += vboot_storage.c diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 81e68d0..3faa297 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1525,28 +1525,3 @@ return 1; } - -#if CONFIG(HAVE_ACPI_TABLES) && !DEVTREE_EARLY -static struct device_operations ec_chromeec_ops = { - .acpi_name = google_chromeec_acpi_name, - .acpi_fill_ssdt_generator = google_chromeec_fill_ssdt_generator, -}; -#endif - -/* ec_lpc, ec_spi, or ec_i2c can override this */ -__weak void google_ec_enable_extra(struct device *dev) -{ -} - -static void google_chromeec_enable(struct device *dev) -{ -#if CONFIG(HAVE_ACPI_TABLES) && !DEVTREE_EARLY - dev->ops = &ec_chromeec_ops; -#endif - google_ec_enable_extra(dev); -} - -struct chip_operations ec_google_chromeec_ops = { - CHIP_NAME("Google Chrome EC") - .enable_dev = google_chromeec_enable -}; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f13b510..699d7c2 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -350,9 +350,4 @@ #endif /* HAVE_ACPI_TABLES */ -/* - * Allows bus-specific EC code to perform actions when the device is enabled. - */ -void google_ec_enable_extra(struct device *dev); - #endif /* _EC_GOOGLE_CHROMEEC_EC_H */ diff --git a/src/ec/google/chromeec/ec_chip.c b/src/ec/google/chromeec/ec_chip.c deleted file mode 100644 index db78bdb..0000000 --- a/src/ec/google/chromeec/ec_chip.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2020 The coreboot project Authors. - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#include <arch/acpi.h> -#include <arch/acpi_device.h> -#include <arch/acpigen.h> -#include <console/console.h> -#include <drivers/usb/acpi/chip.h> -#include <stdlib.h> - -#include "chip.h" -#include "ec.h" -#include "ec_commands.h" - -#define GOOGLE_CHROMEEC_USBC_DEVICE_HID "GOOG0014" -#define GOOGLE_CHROMEEC_USBC_DEVICE_NAME "USBC" - -const char *google_chromeec_acpi_name(const struct device *dev) -{ - return "EC0"; -} - -static const char *power_role_to_str(enum ec_pd_power_role_caps power_role) -{ - switch (power_role) { - case EC_PD_POWER_ROLE_SOURCE: - return "source"; - case EC_PD_POWER_ROLE_SINK: - return "sink"; - case EC_PD_POWER_ROLE_DUAL: - return "dual"; - default: - return "unknown"; - } -} - -static const char *try_power_role_to_str(enum ec_pd_try_power_role_caps try_power_role) -{ - switch (try_power_role) { - case EC_PD_TRY_POWER_ROLE_NONE: - /* - * This should never get returned; if there is no try-power role for a device, - * then the try-power-role field is not added to the DSD. Thus, this is just - * for completeness. - */ - return "none"; - case EC_PD_TRY_POWER_ROLE_SINK: - return "sink"; - case EC_PD_TRY_POWER_ROLE_SOURCE: - return "source"; - default: - return "unknown"; - } -} - -static const char *data_role_to_str(enum ec_pd_data_role_caps data_role) -{ - switch (data_role) { - case EC_PD_DATA_ROLE_DFP: - return "host"; - case EC_PD_DATA_ROLE_UFP: - return "device"; - case EC_PD_DATA_ROLE_DUAL: - return "dual"; - default: - return "unknown"; - } -} - -/* - * Apparently these are supposed to be uppercase, in contrast to the other - * lowercase fields. - */ -static const char *port_location_to_str(enum ec_pd_port_location port_location) -{ - switch (port_location) { - case EC_PD_PORT_LOCATION_LEFT: - return "LEFT"; - case EC_PD_PORT_LOCATION_RIGHT: - return "RIGHT"; - case EC_PD_PORT_LOCATION_BACK: - return "BACK"; - case EC_PD_PORT_LOCATION_FRONT: - return "FRONT"; - case EC_PD_PORT_LOCATION_LEFT_FRONT: - return "LEFT_FRONT"; - case EC_PD_PORT_LOCATION_LEFT_BACK: - return "LEFT_BACK"; - case EC_PD_PORT_LOCATION_RIGHT_FRONT: - return "RIGHT_FRONT"; - case EC_PD_PORT_LOCATION_RIGHT_BACK: - return "RIGHT_BACK"; - case EC_PD_PORT_LOCATION_BACK_LEFT: - return "BACK_LEFT"; - case EC_PD_PORT_LOCATION_BACK_RIGHT: - return "BACK_RIGHT"; - case EC_PD_PORT_LOCATION_UNKNOWN: /* intentional fallthrough */ - default: - return "UNKNOWN"; - } -} - -/* Add port capabilities as DP properties */ -static void add_port_caps(struct acpi_dp *dsd, const struct usb_pd_port_caps *port_caps) -{ - acpi_dp_add_string(dsd, "power-role", power_role_to_str(port_caps->power_role_cap)); - - if (port_caps->try_power_role_cap != EC_PD_TRY_POWER_ROLE_NONE) - acpi_dp_add_string(dsd, "try-power-role", - try_power_role_to_str(port_caps->try_power_role_cap)); - - acpi_dp_add_string(dsd, "data-role", data_role_to_str(port_caps->data_role_cap)); - acpi_dp_add_string(dsd, "port-location", port_location_to_str( - port_caps->port_location)); -} - -/* - * Helper for fill_ssdt_generator. This adds references to the USB - * port objects so that the consumer of this information can know - * whether the port supports USB2 and/or USB3. - */ -static void add_usb_port_references(struct acpi_dp *dsd, int port_number) -{ - static const char usb2_port[] = "usb2-port"; - static const char usb3_port[] = "usb3-port"; - struct device *port = NULL; - const char *path; - const char *usb_port_type; - struct drivers_usb_acpi_config *config; - - /* - * Unfortunately, the acpi_dp_* API doesn't write out the data immediately, thus we need - * different storage areas for all of the strings, so strdup() is used for that. It is - * safe to use strdup() here, because the strings are generated at build-time and are - * guaranteed to be NUL-terminated (they come from the devicetree). - */ - while ((port = dev_find_path(port, DEVICE_PATH_USB)) != NULL) { - if (!port->enabled || port->path.type != DEVICE_PATH_USB) - continue; - - /* Looking for USB 2 & 3 port devices only */ - if (port->path.usb.port_type == 2) - usb_port_type = usb2_port; - else if (port->path.usb.port_type == 3) - usb_port_type = usb3_port; - else - continue; - - config = port->chip_info; - - /* - * Look at only USB Type-C ports, making sure they match the - * port number we're looking for (the 'token' field in 'group'). - * Also note that 'port_number' is 0-based, whereas the 'token' - * field is 1-based. - */ - if ((config->type != UPC_TYPE_C_USB2_ONLY) && - (config->type != UPC_TYPE_C_USB2_SS_SWITCH) && - (config->type != UPC_TYPE_C_USB2_SS)) - continue; - - if (config->group.token != (port_number + 1)) - continue; - - path = acpi_device_path(port); - if (path) { - path = strdup(path); - if (!path) - continue; - - acpi_dp_add_reference(dsd, usb_port_type, path); - } - } -} - -static void fill_ssdt_typec_device(struct device *dev) -{ - struct usb_pd_port_caps port_caps; - char con_name[] = "CONx"; - struct acpi_dp *dsd; - int num_ports; - int rv; - int i; - - rv = google_chromeec_get_num_pd_ports(&num_ports); - if (rv) - return; - - acpigen_write_device(GOOGLE_CHROMEEC_USBC_DEVICE_NAME); - acpigen_write_name_string("_HID", GOOGLE_CHROMEEC_USBC_DEVICE_HID); - acpigen_write_name_string("_DDN", "ChromeOS EC Embedded Controller " - "USB Type-C Control"); - - for (i = 0; i < num_ports; ++i) { - rv = google_chromeec_get_pd_port_caps(i, &port_caps); - if (rv) - continue; - - con_name[3] = (char)i + '0'; - acpigen_write_device(con_name); - acpigen_write_name_integer("_ADR", i); - - /* _DSD, Device-Specific Data */ - dsd = acpi_dp_new_table("_DSD"); - - acpi_dp_add_integer(dsd, "port-number", i); - add_port_caps(dsd, &port_caps); - add_usb_port_references(dsd, i); - - acpi_dp_write(dsd); - acpigen_pop_len(); /* Device CONx */ - } - - acpigen_pop_len(); /* Device GOOGLE_CHROMEEC_USBC_DEVICE_NAME */ -} - -void google_chromeec_fill_ssdt_generator(struct device *dev) -{ - /* Reference the existing device's scope */ - acpigen_write_scope(acpi_device_path(dev)); - fill_ssdt_typec_device(dev); - acpigen_pop_len(); /* Scope */ -} diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 9afb1fd..ab0e3cd 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -451,18 +451,27 @@ .init = lpc_ec_init, .read_resources = lpc_ec_read_resources, .enable_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP + .set_resources = DEVICE_NOOP, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = google_chromeec_acpi_name, + .acpi_fill_ssdt_generator = google_chromeec_fill_ssdt_generator, +#endif }; static struct pnp_info pnp_dev_info[] = { { NULL, 0, 0, 0, } }; -void google_ec_enable_extra(struct device *dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } +struct chip_operations ec_google_chromeec_ops = { + CHIP_NAME("Google Chrome EC") + .enable_dev = enable_dev, +}; + static int google_chromeec_data_ready(u16 port) { return google_chromeec_status_check(port, EC_LPC_CMDR_DATA, -- To view, visit https://review.coreboot.org/c/coreboot/+/39321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a242f4b15603f957e0e81d121e5766fccf3c28d Gerrit-Change-Number: 39321 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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