Change in coreboot[master]: soc/intel/braswell: Generate microcode binaries from tree

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39320 )

Change subject: soc/intel/braswell: Generate microcode binaries from tree
......................................................................

soc/intel/braswell: Generate microcode binaries from tree

Automatically add microcode binaries from intel-microcode 3rdparty
respository for Braswell processors using Makefile.

Signed-off-by: Michał Żygowski 
Change-Id: Iec57e4d5cd63b9bccc869bf178053f1c99b81b9d
---
M src/soc/intel/braswell/Kconfig
M src/soc/intel/braswell/Makefile.inc
2 files changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/39320/1

diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 5b6a923..a437db2 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -15,7 +15,6 @@
    select BOOT_DEVICE_SUPPORTS_WRITES
    select CACHE_MRC_SETTINGS
    select SUPPORT_CPU_UCODE_IN_CBFS
-	select MICROCODE_BLOB_NOT_IN_BLOB_REPO
    select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
    select HAVE_SMI_HANDLER
    select NO_FIXED_XIP_ROM_SIZE
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index d2626e8..5923e39 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -68,6 +68,8 @@

CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)

+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-4c-*)
+
 ifneq ($(CONFIG_VGA_BIOS_FILE),)
 #we will assume that the vbios names will remain as they are now: vgabios.bin and vgabios_c0.bin
 BRASWELL_C0_VBIOS= $(subst .bin,_c0.bin,$(call strip_quotes,$(CONFIG_VGA_BIOS_FILE)))

[Michał Żygowski (Code Review)]

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39320 )

Change subject: soc/intel/braswell: Generate microcode binaries from tree
......................................................................

Patch Set 1:

Is there any particular reason why Braswell did not get the Makefile ucode integration?

[Matt DeVillier (Code Review)]

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39320 )

Change subject: soc/intel/braswell: Generate microcode binaries from tree
......................................................................

Patch Set 1:
> Patch Set 1:
>
> Is there any particular reason why Braswell did not get the Makefile ucode integration?

probably because Intel's repo is bafflingly incomplete. I only see 0406c4 supported; 0406c3 appears missing, and building without it would brick a lot of devices (at least a lot of google/cyan variants)

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39320 )

Change subject: soc/intel/braswell: Generate microcode binaries from tree
......................................................................

Patch Set 1: Code-Review+1

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39320 )

Change subject: soc/intel/braswell: Generate microcode binaries from tree
......................................................................

Patch Set 1: Code-Review+2
> Patch Set 1:
> > Patch Set 1:
> >
> > Is there any particular reason why Braswell did not get the Makefile ucode integration?
>
> probably because Intel's repo is bafflingly incomplete. I only see 0406c4 supported; 0406c3 appears missing, and building without it would brick a lot of devices (at least a lot of google/cyan variants)

I do see 0406c3 in the repo. 0406c2 and 046c1 are missing but those probably are preproduction revisions.

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39320 )

Change subject: soc/intel/braswell: Generate microcode binaries from tree
......................................................................

Patch Set 1: Code-Review+2
> Patch Set 1: Code-Review+2
> > Patch Set 1:
> > > Patch Set 1:
> > >
> > > Is there any particular reason why Braswell did not get the Makefile ucode integration?
> >
> > probably because Intel's repo is bafflingly incomplete. I only see 0406c4 supported; 0406c3 appears missing, and building without it would brick a lot of devices (at least a lot of google/cyan variants)
>
> I do see 0406c3 in the repo. 0406c2 and 046c1 are missing but those probably are preproduction revisions.

406C3: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=263875
406C4: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=263876

[Matt DeVillier (Code Review)]

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39320 )

Change subject: soc/intel/braswell: Generate microcode binaries from tree
......................................................................

Patch Set 1: Code-Review+2
> Patch Set 1: Code-Review+2
>
> I do see 0406c3 in the repo. 0406c2 and 046c1 are missing but those probably are preproduction revisions.

huh, I did a `ls 06-4c-*` and only 06-4c-04 showed, but just retried and they are both there. very odd.

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39320 )

Change subject: soc/intel/braswell: Generate microcode binaries from tree
......................................................................

soc/intel/braswell: Generate microcode binaries from tree

Automatically add microcode binaries from intel-microcode 3rdparty
respository for Braswell processors using Makefile.

Signed-off-by: Michał Żygowski 
Change-Id: Iec57e4d5cd63b9bccc869bf178053f1c99b81b9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39320
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
Reviewed-by: Angel Pons 
Reviewed-by: Matt DeVillier 
---
M src/soc/intel/braswell/Kconfig
M src/soc/intel/braswell/Makefile.inc
2 files changed, 2 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Matt DeVillier: Looks good to me, approved
  Arthur Heymans: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 5b6a923..a437db2 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -15,7 +15,6 @@
    select BOOT_DEVICE_SUPPORTS_WRITES
    select CACHE_MRC_SETTINGS
    select SUPPORT_CPU_UCODE_IN_CBFS
-	select MICROCODE_BLOB_NOT_IN_BLOB_REPO
    select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
    select HAVE_SMI_HANDLER
    select NO_FIXED_XIP_ROM_SIZE
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index d2626e8..5923e39 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -68,6 +68,8 @@

CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)

+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-4c-*)
+
 ifneq ($(CONFIG_VGA_BIOS_FILE),)
 #we will assume that the vbios names will remain as they are now: vgabios.bin and vgabios_c0.bin
 BRASWELL_C0_VBIOS= $(subst .bin,_c0.bin,$(call strip_quotes,$(CONFIG_VGA_BIOS_FILE)))

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39320 )

Change subject: soc/intel/braswell: Generate microcode binaries from tree
......................................................................

Patch Set 2:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1173
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1172
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1171

Please note: This test is under development and might not be accurate at all!