New subject: Change in coreboot[master]: soc/mediatek/mt8183: do TX tracking for DRAM DVFS feature

30 Dec 2019

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37996 )
Change subject: soc/mediatek/mt8183: add TX tracking for DRAM DVFS
......................................................................
soc/mediatek/mt8183: add TX tracking for DRAM DVFS
use dqs osc to tracking the TX window for DVFS
BUG=b:none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: Idcf9213a488e795df3faf64b03588cfe55cb2f81
Signed-off-by: Huayang Duan huayang.duan@mediatek.com
---
M src/soc/mediatek/mt8183/dramc_pi_basic_api.c
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
M src/soc/mediatek/mt8183/emi.c
M src/soc/mediatek/mt8183/include/soc/dramc_register.h
4 files changed, 296 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/37996/1

diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
index 1eb86f4..c609128 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
@@ -419,6 +419,51 @@
    }
 }
+extern const u8 freq_shuffle[DRAM_DFS_SHUFFLE_MAX];
+extern const u8 freq_shuffle_emcp[DRAM_DFS_SHUFFLE_MAX];
+extern const u32 frequency_table[LP4X_DDRFREQ_MAX];
+
+static void dramc_hw_dqs_osc(u8 chn)
+{
+	u32 freq_shu0, freq_shu1, freq_shu2;
+	const u8 *freq_tbl;
+
+	if (CONFIG_MT8183_DRAM_EMCP)
+		freq_tbl = freq_shuffle_emcp;
+	else
+		freq_tbl = freq_shuffle;
+
+ 	dramc_dbg("%s %d called!\n", __func__, __LINE__);
+
+	freq_shu0 = frequency_table[freq_tbl[0]];
+	freq_shu1 = frequency_table[freq_tbl[1]];
+	freq_shu2 = frequency_table[freq_tbl[2]];
+
+	SET32_BITFIELDS(&ch[chn].ao.rk[2].dqsosc, RK2_DQSOSC_FREQ_RATIO_TX_0, (freq_shu1*8/freq_shu0));
+	SET32_BITFIELDS(&ch[chn].ao.rk[2].dqsosc, RK2_DQSOSC_FREQ_RATIO_TX_1, (freq_shu2*8/freq_shu0));
+	SET32_BITFIELDS(&ch[chn].ao.rk[2].dqsosc, RK2_DQSOSC_FREQ_RATIO_TX_3, (freq_shu0*8/freq_shu1));
+	SET32_BITFIELDS(&ch[chn].ao.rk[2].dqsosc, RK2_DQSOSC_FREQ_RATIO_TX_4, (freq_shu2*8/freq_shu1));
+	SET32_BITFIELDS(&ch[chn].ao.rk[2].dummy_rd_bk, RK2_DUMMY_RD_BK_FREQ_RATIO_TX_6, (freq_shu0*8/freq_shu2));
+	SET32_BITFIELDS(&ch[chn].ao.rk[2].dummy_rd_bk, RK2_DUMMY_RD_BK_FREQ_RATIO_TX_7, (freq_shu1*8/freq_shu2));
+
+	SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0], PRE_TDQSCK1_SHU_PRELOAD_TX_HW, 1);
+	SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0], PRE_TDQSCK1_SHU_PRELOAD_TX_START, 0);
+	SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0], PRE_TDQSCK1_SW_UP_TX_NOW_CASE, 0);
+
+
+	SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPC_BLOCKALE_OPT, 0);
+	SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMARPIDQ_SW, 1);
+	SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_ARUIDQ_SW, 1);
+	SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 1);
+
+	SET32_BITFIELDS(&ch[chn].ao.rk[0].dqsosc, RK0_DQSOSC_DQSOSCR_RK0EN, 1);
+	SET32_BITFIELDS(&ch[chn].ao.rk[1].dqsosc, RK1_DQSOSC_DQSOSCR_RK1EN, 1);
+	SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSC_CALEN, 1);
+
+	for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
+		SET32_BITFIELDS(&ch[chn].ao.shu[shu].scintv, SHU_SCINTV_DQSOSCENDIS, 1);
+}
+
 void dramc_runtime_config(void)
 {
    clrbits32(&ch[0].ao.refctrl0, 0x1 << 29);
@@ -427,6 +472,9 @@
    transfer_pll_to_spm_control();
    setbits32(&mtk_spm->spm_power_on_val0, 0x1 << 25);
+	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+		dramc_hw_dqs_osc(chn);
+
    /* RX_TRACKING: ON */
    for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
    	dramc_rx_input_delay_tracking(chn);
diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
index 0ec0193..2e5228d 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
@@ -105,6 +105,37 @@
    		CKECTRL_CKEFIXOFF, cke_off);
 }
+static u16 dramc_mode_reg_read(u8 chn, u8 mr_idx)
+{
+	u16 value;
+	SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSMA, mr_idx);
+	SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRREN, 1);
+
+	/* Wait MRW command fired */
+	while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRR_RESPONSE)
+	       == 0)
+		udelay(1);
+
+	value = READ32_BITFIELD(&ch[chn].nao.mrr_status, MRR_STATUS_MRR_REG);
+
+	SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRREN, 0);
+	dramc_dbg("Read MR%d =0x%x\n", mr_idx, value);
+
+	return value;
+}
+
+static u16  dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx)
+{
+	u16 value;
+	u32 mrs_bak = READ32_BITFIELD(&ch[chn].ao.mrs, MRS_MRSRK);
+
+	SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank);
+	value = dramc_mode_reg_read(chn, mr_idx);
+	SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, mrs_bak);
+
+	return value;
+}
+
 void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value)
 {
    u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl);
@@ -117,7 +148,7 @@
    /* Wait MRW command fired */
    while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRW_RESPONSE)
           == 0)
-		;
+		udelay(1);
SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRWEN, 0);
    write32(&ch[chn].ao.ckectrl, ckectrl_bak);
@@ -1577,17 +1608,9 @@
    }
 }
-static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx,
-		struct win_perbit_dly *vref_dly, enum CAL_TYPE type, u8 freq_group,
-		u16 *tx_dq_precal_result, u16 dly_cell_unit, const struct sdram_params *params,
-		const bool fast_calib)
+static u32 get_freq_group_clock(u8 freq_group)
 {
-	int index, clock_rate;
-	u8 use_delay_cell;
-	u32 byte_dly_cell[DQS_NUMBER] = {0};
-	struct per_byte_dly center_dly[DQS_NUMBER];
-	u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH];
-
+	u32 clock_rate = 0;
/*
     * The clock rate is usually (frequency / 2 - delta), where the delta
@@ -1609,8 +1632,23 @@
    	break;
    default:
    	die("Invalid DDR frequency group %u\n", freq_group);
-		return;
+		break;
    }
+	return clock_rate;
+}
+
+static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx,
+		struct win_perbit_dly *vref_dly, enum CAL_TYPE type, u8 freq_group,
+		u16 *tx_dq_precal_result, u16 dly_cell_unit, const struct sdram_params *params,
+		const bool fast_calib)
+{
+	int index, clock_rate;
+	u8 use_delay_cell;
+	u32 byte_dly_cell[DQS_NUMBER] = {0};
+	struct per_byte_dly center_dly[DQS_NUMBER];
+	u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH];
+
+	clock_rate = get_freq_group_clock(freq_group);
if (type == TX_WIN_DQ_ONLY && get_freq_fsq(freq_group) == FSP_1)
    	use_delay_cell = 1;
@@ -2104,6 +2142,152 @@
    		(0xff << 8) | (0x9 << 2) | ROEN);
 }
+static void start_dqs_osc(u8 chn)
+{
+	u32 loop = 0;
+	SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSOSCENEN, 1);
+	while (!wait_us(10, read32(&ch[chn].nao.spcmdresp) & (0x1 << 10))) {
+		if (loop++ > 10)
+			dramc_err("start DQSOSC fail (time out)\n");
+			return;
+	}
+	SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSOSCENEN, 0);
+}
+
+static void dqs_osc_set(u8 chn, u8 rank, u8 freq_group)
+{
+	u8  mr23 = 0x3F;
+	u16 mr18, mr19;
+	u16 dqs_osc_cnt[2];
+
+	struct reg_value regs_bak[] = {
+		{&ch[chn].ao.mrs},
+		{&ch[chn].ao.dramc_pd_ctrl},
+		{&ch[chn].ao.ckectrl},
+	};
+
+	for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
+		regs_bak[i].value = read32(regs_bak[i].addr);
+ 	dramc_dbg("%s %d called!\n", __func__, __LINE__);
+
+	SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_DQSOSC2RK, 0);
+	SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank);
+	SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1);
+	SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank);
+	dramc_mode_reg_write(chn, 23, mr23);
+
+	for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
+		SET32_BITFIELDS(&ch[chn].ao.shu[shu].scintv, SHU_SCINTV_DQSOSCENDIS, 1);
+
+	SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_MIOCKCTRLOFF, 1);
+	dramc_cke_fix_onoff(chn, true, false);
+
+	start_dqs_osc(chn);
+	udelay(1);
+	SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rank);
+
+	for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
+		write32(regs_bak[i].addr, regs_bak[i].value);
+
+	mr18 = dramc_mode_reg_read(chn, 18);
+	mr19 = dramc_mode_reg_read(chn, 19);
+	dqs_osc_cnt[0] = (mr18 & 0xFF) | ((mr19 & 0xFF) << 8);
+	dqs_osc_cnt[1] = (mr18 >> 8) | (mr19 & 0xFF00);
+	dramc_dbg("DQSOscCnt B0=0x%X, B1=0x%X\n", dqs_osc_cnt[0] , dqs_osc_cnt[1]);
+
+	SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[rank].dqsosc,
+		SHU1RK0_DQSOSC_DQSOSC_BASE_RK0,  dqs_osc_cnt[0]);
+	SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[rank].dqsosc,
+		SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1,  dqs_osc_cnt[1]);
+}
+
+static void dqs_osc_shu_settings(u8 chn, u8 freq_group)
+{
+	u8 filt_pithrd, w2r_sel, upd_sel;
+	u8 mr23 = 0x3F;
+	u16 mr18, mr19;
+	u16 dqs_cnt, dqs_osc, prd_cnt, thrd_inc, thrd_dec;
+	u32 clock_rate, tck;
+
+	SET32_BITFIELDS(&ch[chn].ao.shu[0].scintv, SHU_SCINTV_DQS2DQ_SHU_PITHRD, 0);
+	SET32_BITFIELDS(&ch[chn].ao.rk[0].dqsosc, RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT, 0);
+
+	switch (freq_group) {
+	case LP4X_DDR1600:
+		filt_pithrd = 0x5;
+		w2r_sel = 0x5;
+		upd_sel = 0x0;
+		break;
+	case LP4X_DDR2400:
+		filt_pithrd = 0x8;
+		w2r_sel = 0x2;
+		upd_sel = 0x0;
+		break;
+	case LP4X_DDR3200:
+		filt_pithrd = 0xA;
+		w2r_sel = 0x2;
+		upd_sel = 0x0;
+		break;
+	case LP4X_DDR3600:
+		filt_pithrd = 0xB;
+		w2r_sel = 0x2;
+		upd_sel = 0x0;
+		break;
+	default:
+		die("Invalid DDR frequency group %u\n", freq_group);
+		return;
+	}
+ 	dramc_dbg("%s %d called!\n", __func__, __LINE__);
+
+	SET32_BITFIELDS(&ch[chn].ao.shu[0].scintv, SHU_SCINTV_DQS2DQ_FILT_PITHRD, filt_pithrd);
+	SET32_BITFIELDS(&ch[chn].ao.shu[0].wodt, SHU1_WODT_TXUPD_W2R_SEL, w2r_sel);
+	SET32_BITFIELDS(&ch[chn].ao.shu[0].wodt, SHU1_WODT_TXUPD_SEL, upd_sel);
+
+	prd_cnt = mr23 / 4 + 3;
+	SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsosc_prd, SHU1_DQSOSC_PRD_DQSOSC_PRDCNT, prd_cnt);
+	SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscr, SHU_DQSOSCR_DQSOSCRCNT, 0x40);
+
+	for (u8 rk = RANK_0; rk < RANK_MAX; rk++) {
+		mr18 = dramc_mode_reg_read_by_rank(chn, rk, 18);
+		mr19 = dramc_mode_reg_read_by_rank(chn, rk, 19);
+
+		clock_rate = get_freq_group_clock(freq_group);
+		tck = 1000000 /clock_rate;
+
+		dqs_cnt = (mr18 & 0xFF) | ((mr19 & 0xFF) <<8);
+		if (dqs_cnt != 0) {
+			dqs_osc = mr23*16 *1000000 / (2 * dqs_cnt * clock_rate);
+			thrd_inc = (mr23 * tck * tck) / (dqs_osc * dqs_osc * 10);
+			thrd_dec = (3 * mr23 * tck * tck) / (dqs_osc * dqs_osc * 20);
+		} else {
+ 			dqs_osc = 0;
+			thrd_inc = 0x6;
+			thrd_dec = 0x4;
+		}
+
+		dramc_dbg("CH%d_RK%d: MR19=0x%x, MR18=0x%x, DQSOSC=%d, MR23=0x%x, INC=%d, DEC=%d\n",
+			chn, rk, mr18, mr19, dqs_cnt, mr23, thrd_inc, thrd_dec);
+
+		if (rk == RANK_0) {
+			SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscthrd,
+				SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0, thrd_inc);
+			SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscthrd,
+				SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0, thrd_dec);
+		} else {
+			SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscthrd,
+				SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0,
+				thrd_inc & 0xFF);
+			SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsosc_prd,
+				SHU1_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8,
+				(thrd_inc & 0xF00) >> 8);
+			SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsosc_prd,
+				SHU1_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1, thrd_dec);
+		}
+	}
+	SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscr2, SHU_DQSOSCR2_DQSOSCENCNT, 0x1FF);
+ 	dramc_dbg("%s %d called!\n", __func__, __LINE__);
+}
+
 int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group,
    			 const struct mr_value *mr)
 {
@@ -2146,8 +2330,11 @@
    		dramc_window_perbit_cal(chn, rk, freq_group,
    			RX_WIN_TEST_ENG, pams, fast_calib);
    		dramc_auto_refresh_switch(chn, false);
+
+			dqs_osc_set(chn, rk, freq_group);
    	}
+		dqs_osc_shu_settings(chn, freq_group);
    	dramc_rx_dqs_gating_post_process(chn, freq_group);
    	dramc_dual_rank_rx_datlat_cal(chn, freq_group, rx_datlat[0], rx_datlat[1]);
    }
diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c
index cf104f8..3755d2b 100644
--- a/src/soc/mediatek/mt8183/emi.c
+++ b/src/soc/mediatek/mt8183/emi.c
@@ -22,19 +22,19 @@
 #include <soc/mt6358.h>
 #include <soc/spm.h>
-static const u8 freq_shuffle[DRAM_DFS_SHUFFLE_MAX] = {
+const u8 freq_shuffle[DRAM_DFS_SHUFFLE_MAX] = {
    [DRAM_DFS_SHUFFLE_1] = LP4X_DDR3200,
    [DRAM_DFS_SHUFFLE_2] = LP4X_DDR2400,
    [DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600,
 };
-static const u8 freq_shuffle_emcp[DRAM_DFS_SHUFFLE_MAX] = {
+const u8 freq_shuffle_emcp[DRAM_DFS_SHUFFLE_MAX] = {
    [DRAM_DFS_SHUFFLE_1] = LP4X_DDR3600,
    [DRAM_DFS_SHUFFLE_2] = LP4X_DDR3200,
    [DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600,
 };
-u32 frequency_table[LP4X_DDRFREQ_MAX] = {
+const u32 frequency_table[LP4X_DDRFREQ_MAX] = {
    [LP4X_DDR1600] = 1600,
    [LP4X_DDR2400] = 2400,
    [LP4X_DDR3200] = 3200,
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h
index b3ee6af..38e1bb2 100644
--- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h
+++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h
@@ -627,12 +627,17 @@
 check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800);
DEFINE_BITFIELD(MISC_STATUSA_REFRESH_QUEUE_CNT, 27, 24)
+DEFINE_BIT(SPCMDRESP_MRR_RESPONSE, 0)
 DEFINE_BIT(SPCMDRESP_MRW_RESPONSE, 0)
+DEFINE_BITFIELD(MRR_STATUS_MRR_REG, 15, 0)
DEFINE_BIT(DDRCONF0_DM4TO1MODE, 22)
 DEFINE_BIT(DDRCONF0_RDATRST, 0)
 DEFINE_BIT(PERFCTL0_RWOFOEN, 4)
+DEFINE_BIT(RKCFG_DQSOSC2RK, 11)
+DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 26)
+
 DEFINE_BIT(PADCTRL_DQIENLATEBEGIN, 3)
 DEFINE_BITFIELD(PADCTRL_DQIENQKEND, 1, 0)
@@ -655,16 +660,21 @@
 DEFINE_BITFIELD(MRS_MRSMA, 20, 8)
 DEFINE_BITFIELD(MRS_MRSOP, 7, 0)
+DEFINE_BIT(SPCMD_DQSOSCENEN, 10)
 DEFINE_BIT(SPCMD_DQSGCNTRST, 9)
 DEFINE_BIT(SPCMD_DQSGCNTEN, 8)
 DEFINE_BIT(SPCMD_ZQLATEN, 6)
 DEFINE_BIT(SPCMD_RDDQCEN, 7)
 DEFINE_BIT(SPCMD_ZQCEN, 4)
+DEFINE_BIT(SPCMD_MRREN, 0)
 DEFINE_BIT(SPCMD_MRWEN, 0)
DEFINE_BIT(SPCMDCTRL_RDDQCDIS, 11)
DEFINE_BIT(MPC_OPTION_MPCRKEN, 17)
+DEFINE_BIT(MPC_OPTION_MPC_BLOCKALE_OPT, 0)
+
+
DEFINE_BIT(DVFSDLL_R_BYPASS_1ST_DLL_SHU1, 1)
@@ -727,7 +737,41 @@
 DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL, 23, 20)
DEFINE_BIT(SHU1_WODT_DBIWR, 29)
+DEFINE_BIT(SHU_SCINTV_DQSOSCENDIS, 30)
+DEFINE_BITFIELD(SHU_SCINTV_DQS2DQ_SHU_PITHRD, 23, 18)
 DEFINE_BITFIELD(SHURK_DQSCTL_DQSINCTL, 3, 0)
+DEFINE_BIT(RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT, 29)
+DEFINE_BIT(RK0_DQSOSC_DQSOSCR_RK0EN, 30)
+DEFINE_BIT(RK1_DQSOSC_DQSOSCR_RK1EN, 30)
+
+DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_0, 4, 0)
+DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_1, 9, 5)
+DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_3, 19, 15)
+DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_4, 24, 20)
+DEFINE_BITFIELD(RK2_DUMMY_RD_BK_FREQ_RATIO_TX_6, 7, 3)
+DEFINE_BITFIELD(RK2_DUMMY_RD_BK_FREQ_RATIO_TX_7, 12, 8)
+
+DEFINE_BIT(PRE_TDQSCK1_SW_UP_TX_NOW_CASE, 16)
+DEFINE_BIT(PRE_TDQSCK1_SHU_PRELOAD_TX_START, 18)
+DEFINE_BIT(PRE_TDQSCK1_SHU_PRELOAD_TX_HW, 19)
+
+
+DEFINE_BITFIELD(SHU_SCINTV_DQS2DQ_FILT_PITHRD, 29, 24)
+DEFINE_BITFIELD(SHU1_WODT_TXUPD_W2R_SEL, 16, 14)
+DEFINE_BITFIELD(SHU1_WODT_TXUPD_SEL, 13, 12)
+DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSC_PRDCNT, 9, 0)
+DEFINE_BITFIELD(SHU_DQSOSCR_DQSOSCRCNT, 7, 0)
+DEFINE_BIT(DQSOSCR_ARUIDQ_SW, 7)
+DEFINE_BIT(DQSOSCR_DQSOSCRDIS, 24)
+DEFINE_BIT(DQSOSCR_DQSOSC_CALEN, 31)
+
+
+DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0, 11, 0)
+DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0, 23, 12)
+DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0, 31, 24)
+DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8, 19, 16)
+DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1, 31, 20)
+DEFINE_BITFIELD(SHU_DQSOSCR2_DQSOSCENCNT, 8, 0)
DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1, 14, 12)
 DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1, 6, 4)
@@ -736,6 +780,8 @@
 DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS1_GATED_P1, 14, 12)
 DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED_P1, 6, 4)
 DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED, 2, 0)
+DEFINE_BITFIELD(SHU1RK0_DQSOSC_DQSOSC_BASE_RK0, 15, 0)
+DEFINE_BITFIELD(SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1, 31, 16)
DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16)
 DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16)
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idcf9213a488e795df3faf64b03588cfe55cb2f81
Gerrit-Change-Number: 37996
Gerrit-PatchSet: 1
Gerrit-Owner: huayang duan huayangduan@gmail.com
Gerrit-MessageType: newchange



    

Change in coreboot[master]: soc/mediatek/mt8183: add TX tracking for DRAM DVFS