Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39259 )
Change subject: soc/intel/common/block/tco: clear TCO1_STS register, too ......................................................................
soc/intel/common/block/tco: clear TCO1_STS register, too
The register TCO1_STS is never cleared, which will cause SMIs to either retrigger over and over again (e.g. TIMEOUT) or prevent concurrent interrupt events, depending on which event triggered.
Clear both TCO2_STS and TCO1_STS.
This also fixes the issue where SECOND_TO_STS will always end up set in the SMI handler by unconditionally (re)setting it.
Tested on X11SSM-F, where enabling TCO caused the terminal to get flooded with SMI debug messages. With this patch, a message gets written every ~1 second.
Signed-off-by: Michael Niewöhner foss@mniewoehner.de Change-Id: Ia57c203a672fdd0095355a7e2a0e01aaa6657968 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39259 Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Andrey Petrov anpetrov@fb.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Aaron Durbin adurbin@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/smbus/tco.c 1 file changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Aaron Durbin: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve Andrey Petrov: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1a215eb..bd8790a 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -74,13 +74,13 @@ uint16_t tco1_sts; uint16_t tco2_sts;
- /* TCO Status 2 register */ - tco2_sts = tco_read_reg(TCO2_STS); - tco2_sts |= TCO_STS_SECOND_TO; - tco_write_reg(TCO2_STS, tco2_sts); - /* TCO Status 1 register */ tco1_sts = tco_read_reg(TCO1_STS); + tco_write_reg(TCO1_STS, tco1_sts); + + /* TCO Status 2 register */ + tco2_sts = tco_read_reg(TCO2_STS); + tco_write_reg(TCO2_STS, tco2_sts | TCO_STS_SECOND_TO);
return (tco2_sts << 16) | tco1_sts; }