Hello build bot (Jenkins), Paul Menzel, Angel Pons, Keith Hui, Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39238
to review the following change.
Change subject: Revert "i82371eb: Drop support for older PIIX chips" ......................................................................
Revert "i82371eb: Drop support for older PIIX chips"
This reverts commit 2b9004de602f98a404b17584ab3e1451f165c1f4.
Reason for revert: QEMU emulates that chipset and with that commit a Linux guest kernel can't find IDE devices anymore.
Change-Id: Iad75af4ea9993d6a2ec5433ad30d39900dab874e --- M src/southbridge/intel/i82371eb/i82371eb.c M src/southbridge/intel/i82371eb/ide.c M src/southbridge/intel/i82371eb/isa.c M src/southbridge/intel/i82371eb/usb.c 4 files changed, 83 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39238/1
diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c index 02812ce..898cdff 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.c +++ b/src/southbridge/intel/i82371eb/i82371eb.c @@ -14,9 +14,22 @@ * GNU General Public License for more details. */
-/* Note: This code supports the 82371AB/EB/MB. */ +/* Note: This code supports the 82371FB/SB/MX/AB/EB/MB and 82437MX. */
/* Datasheets: + * - Name: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR + * - URL: http://www.intel.com/design/intarch/datashts/290550.htm + * - PDF: http://download.intel.com/design/intarch/datashts/29055002.pdf + * - Date: April 1997 + * - Order Number: 290550-002 + * + * - Name: 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerator + * Specification Update + * - URL: http://www.intel.com/design/chipsets/specupdt/297658.htm + * - PDF: http://download.intel.com/design/chipsets/specupdt/29765801.pdf + * - Date: March 1998 + * - Order Number: 297658-004 + * * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) * (applies to 82371AB/EB/MB, a.k.a. PIIX4/PIIX4E/PIIX4M) * - URL: http://www.intel.com/design/intarch/datashts/290562.htm @@ -31,8 +44,10 @@ * - Order Number: 297738-017 */
+/* TODO: List the other datasheets. */ + #include <device/device.h>
const struct chip_operations southbridge_intel_i82371eb_ops = { - CHIP_NAME("Intel 82371AB/EB/MB Southbridge") + CHIP_NAME("Intel 82371FB/SB/MX/AB/EB/MB Southbridge") }; diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c index 1b8136a..7a72a65 100644 --- a/src/southbridge/intel/i82371eb/ide.c +++ b/src/southbridge/intel/i82371eb/ide.c @@ -119,6 +119,18 @@ }
/** + * IDE init for the Intel 82371FB/SB IDE controller. + * + * These devices do not support UDMA/33, so don't attempt to enable it. + * + * @param dev The device to use. + */ +static void ide_init_i82371fb_sb(struct device *dev) +{ + ide_init_enable(dev); +} + +/** * IDE init for the Intel 82371AB/EB/MB IDE controller. * * @param dev The device to use. @@ -129,6 +141,17 @@ ide_init_udma33(dev); }
+/* Intel 82371FB/SB */ +static const struct device_operations ide_ops_fb_sb = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init_i82371fb_sb, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, /* No subsystem IDs on 82371XX! */ +}; + /* Intel 82371AB/EB/MB */ static const struct device_operations ide_ops_ab_eb_mb = { .read_resources = pci_dev_read_resources, @@ -140,6 +163,34 @@ .ops_pci = 0, /* No subsystem IDs on 82371XX! */ };
+/* Intel 82371FB (PIIX) */ +static const struct pci_driver ide_driver_fb __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371FB_IDE, +}; + +/* Intel 82371SB (PIIX3) */ +static const struct pci_driver ide_driver_sb __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_IDE, +}; + +/* Intel 82371MX (MPIIX) */ +static const struct pci_driver ide_driver_mx __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371MX_ISA_IDE, +}; + +/* Intel 82437MX (part of the 430MX chipset) */ +static const struct pci_driver ide_driver_82437mx __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82437MX_ISA_IDE, +}; + /* Intel 82371AB/EB/MB */ static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = { .ops = &ide_ops_ab_eb_mb, diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index fefead0..a57d61a 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -157,3 +157,9 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82371AB_ISA, }; + +static const struct pci_driver isa_SB_driver __pci_driver = { + .ops = &isa_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_ISA, +}; diff --git a/src/southbridge/intel/i82371eb/usb.c b/src/southbridge/intel/i82371eb/usb.c index 38ab167..80b19a1 100644 --- a/src/southbridge/intel/i82371eb/usb.c +++ b/src/southbridge/intel/i82371eb/usb.c @@ -43,6 +43,15 @@ .ops_pci = 0, /* No subsystem IDs on 82371EB! */ };
+/* Note: No USB on 82371FB/MX (PIIX/MPIIX) and 82437MX. */ + +/* Intel 82371SB (PIIX3) */ +static const struct pci_driver usb_driver_sb __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_USB, +}; + /* Intel 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) */ /* The 440MX (82443MX) consists of 82443BX + 82371EB (uses same PCI IDs). */ static const struct pci_driver usb_driver_ab_eb_mb __pci_driver = {
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39238 )
Change subject: Revert "i82371eb: Drop support for older PIIX chips" ......................................................................
Patch Set 1: Code-Review+2
Forgot the signed-off-by
Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39238 )
Change subject: Revert "i82371eb: Drop support for older PIIX chips" ......................................................................
Patch Set 1: Code-Review+1
My vote is to revert too. Thanks Patrick and sorry for breaking it.
I may be back with a patch with some slight streamlining around this area.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39238 )
Change subject: Revert "i82371eb: Drop support for older PIIX chips" ......................................................................
Patch Set 1:
Why wasn't that catched by the QA? Is the default to use AHCI instead of IDE? How can this be reproduced on qemu?
Hello build bot (Jenkins), Paul Menzel, Angel Pons, Arthur Heymans, Patrick Rudolph, Keith Hui,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39238
to look at the new patch set (#2).
Change subject: Revert "i82371eb: Drop support for older PIIX chips" ......................................................................
Revert "i82371eb: Drop support for older PIIX chips"
This reverts commit 2b9004de602f98a404b17584ab3e1451f165c1f4.
Reason for revert: QEMU emulates that chipset and with that commit a Linux guest kernel can't find IDE devices anymore.
Change-Id: Iad75af4ea9993d6a2ec5433ad30d39900dab874e Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/southbridge/intel/i82371eb/i82371eb.c M src/southbridge/intel/i82371eb/ide.c M src/southbridge/intel/i82371eb/isa.c M src/southbridge/intel/i82371eb/usb.c 4 files changed, 83 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39238/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39238 )
Change subject: Revert "i82371eb: Drop support for older PIIX chips" ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39238 )
Change subject: Revert "i82371eb: Drop support for older PIIX chips" ......................................................................
Patch Set 2:
Patch Set 1:
Why wasn't that catched by the QA? Is the default to use AHCI instead of IDE? How can this be reproduced on qemu?
Paul was the one who complained about breakage. Maybe he knows?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39238 )
Change subject: Revert "i82371eb: Drop support for older PIIX chips" ......................................................................
Patch Set 2: Code-Review+1
Patch Set 1:
Why wasn't that catched by the QA? Is the default to use AHCI instead of IDE? How can this be reproduced on qemu?
What QA? QEMU i440fx failed to boot in my case.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39238 )
Change subject: Revert "i82371eb: Drop support for older PIIX chips" ......................................................................
Patch Set 2:
Patch Set 2: Code-Review+1
Patch Set 1:
Why wasn't that catched by the QA? Is the default to use AHCI instead of IDE? How can this be reproduced on qemu?
What QA? QEMU i440fx failed to boot in my case.
This QA: https://lava.9esec.io/r/1051 From there, you can get to https://lava.9esec.io/results/testcase/25317 and to that test case's log at https://lava.9esec.io/scheduler/job/1051#results_25317
A few excerpts:
IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: off ... [ 1.747754] ata1.00: ATA-7: QEMU HARDDISK, 2.5+, max UDMA/100 [ 1.749153] ata1.00: 8392704 sectors, multi 16: LBA48 [ 1.750422] ata1.01: ATA-7: QEMU HARDDISK, 2.5+, max UDMA/100 [ 1.751910] ata1.01: 1048576 sectors, multi 16: LBA48
These seem to indicate that IDE access still works on some qemu-i440fx configuration and so it would be useful to know what's different in yours.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39238 )
Change subject: Revert "i82371eb: Drop support for older PIIX chips" ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2: Code-Review+1
Patch Set 1:
Why wasn't that catched by the QA? Is the default to use AHCI instead of IDE? How can this be reproduced on qemu?
What QA? QEMU i440fx failed to boot in my case.
This QA: https://lava.9esec.io/r/1051 From there, you can get to https://lava.9esec.io/results/testcase/25317 and to that test case's log at https://lava.9esec.io/scheduler/job/1051#results_25317
A few excerpts:
IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: off ... [ 1.747754] ata1.00: ATA-7: QEMU HARDDISK, 2.5+, max UDMA/100 [ 1.749153] ata1.00: 8392704 sectors, multi 16: LBA48 [ 1.750422] ata1.01: ATA-7: QEMU HARDDISK, 2.5+, max UDMA/100 [ 1.751910] ata1.01: 1048576 sectors, multi 16: LBA48
These seem to indicate that IDE access still works on some qemu-i440fx configuration and so it would be useful to know what's different in yours.
Thank you for the research.
The used coreboot version is not even visible. It’s *unknown*. Where can I find the configuration and QEMU command?
Here you can see the last working version for me case.
https://review.coreboot.org/cgit/board-status.git/commit/emulation/qemu-i440...
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39238 )
Change subject: Revert "i82371eb: Drop support for older PIIX chips" ......................................................................
Patch Set 2:
Note, that the drive is detected by SeaBIOS, and GRUB is able to load the Linux kernel and initrd from it, so it seems to be a Linux problem. Still it worked before.
Failed boot below. No
IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: off
is visible anymore.
``` $ qemu-system-i386 -version QEMU emulator version 4.2.0 (Debian 1:4.2-3) Copyright (c) 2003-2019 Fabrice Bellard and the QEMU Project developers $ qemu-system-i386 -bios /dev/shm/coreboot/build/coreboot.rom -L /dev/shm -enable-kvm -smp cpus=2 -m 1G -hda ~/debian-32.img -serial stdio -net nic -net user,hostfwd=tcp::22222-:22 WARNING: Image format was not specified for '/home/pmenzel/debian-32.img' and probing guessed raw. Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted. Specify the 'raw' format explicitly to remove the restrictions.
coreboot-4.11-1451-g8bee86ef23 Thu Mar 5 07:48:05 UTC 2020 bootblock starting (log level: 7)... FMAP: Found "FLASH" version 1.1 at 0x0. FMAP: base = 0xfffc0000 size = 0x40000 #areas = 3 FMAP: area COREBOOT found @ 200 (261632 bytes) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 38f4 BS: bootblock times (exec / console): total (unknown) / 4 ms
coreboot-4.11-1451-g8bee86ef23 Thu Mar 5 07:48:05 UTC 2020 romstage starting (log level: 7)... QEMU: firmware config interface detected Firmware config version id: 3 CBMEM: IMD: root @ 0x3ffff000 254 entries. IMD: root @ 0x3fffec00 62 entries. MTRR Range: Start=fffc0000 End=0 (Size 40000) FMAP: area COREBOOT found @ 200 (261632 bytes) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset ff40 size 3e70 Decompressing stage fallback/postcar @ 0x3ffd3fc0 (32496 bytes) Loading module at 0x3ffd4000 with entry 0x3ffd4000. filesize: 0x3bd0 memsize: 0x7eb0 Processing 145 relocs. Offset value of 0x3dfd4000 BS: romstage times (exec / console): total (unknown) / 9 ms
coreboot-4.11-1451-g8bee86ef23 Thu Mar 5 07:48:05 UTC 2020 postcar starting (log level: 7)... FMAP: area COREBOOT found @ 200 (261632 bytes) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 3a00 size be8f Decompressing stage fallback/ramstage @ 0x3ffaffc0 (140840 bytes) Loading module at 0x3ffb0000 with entry 0x3ffb0000. filesize: 0x17b18 memsize: 0x225e8 Processing 1505 relocs. Offset value of 0x3f1b0000 BS: postcar times (exec / console): total (unknown) / 7 ms
coreboot-4.11-1451-g8bee86ef23 Thu Mar 5 07:48:05 UTC 2020 ramstage starting (log level: 7)... Enumerating buses... Root Device scanning... CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled CPU_CLUSTER: 0 scanning... QEMU: firmware config interface detected Firmware config version id: 3 QEMU: max_cpus is 2 CPU: APIC: 00 enabled CPU: APIC: 01 enabled scan_bus: bus CPU_CLUSTER: 0 finished in 1 msecs DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1237] enabled PCI: 00:01.0 [8086/7000] enabled PCI: 00:01.1 [8086/7010] enabled PCI: 00:01.3 [8086/7113] enabled PCI: 00:02.0 [1234/1111] enabled PCI: 00:03.0 [8086/100e] enabled PCI: 00:01.3 scanning... scan_bus: bus PCI: 00:01.3 finished in 0 msecs scan_bus: bus DOMAIN: 0000 finished in 10 msecs scan_bus: bus Root Device finished in 14 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 7 / 9 ms found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... QEMU: e820/res: 0xfeffc000 +0x00004000 QEMU: e820/ram: 0x00000000 + 0x40000000 QEMU: reserve ioports 0x0510-0x0511 [firmware-config] QEMU: reserve ioports 0x5658-0x5658 [vmware-port] QEMU: reserve ioports 0xae00-0xae0f [pci-hotplug] QEMU: reserve ioports 0xaf00-0xaf1f [cpu-hotplug] QEMU: reserve ioports 0xafe0-0xafe3 [piix4-gpe0] Done reading resources. Setting resources... PCI: 00:01.1 20 <- [0x0000005840 - 0x000000584f] size 0x00000010 gran 0x04 io PCI: 00:02.0 10 <- [0x00fd000000 - 0x00fdffffff] size 0x01000000 gran 0x18 prefmem PCI: 00:02.0 18 <- [0x00fe070000 - 0x00fe070fff] size 0x00001000 gran 0x0c mem PCI: 00:02.0 30 <- [0x00fe060000 - 0x00fe06ffff] size 0x00010000 gran 0x10 romem PCI: 00:03.0 10 <- [0x00fe040000 - 0x00fe05ffff] size 0x00020000 gran 0x11 mem PCI: 00:03.0 14 <- [0x0000005800 - 0x000000583f] size 0x00000040 gran 0x06 io PCI: 00:03.0 30 <- [0x00fe000000 - 0x00fe03ffff] size 0x00040000 gran 0x12 romem Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 3 / 15 ms Enabling resources... PCI: 00:00.0 cmd <- 00 PCI: 00:01.0 subsystem <- 8086/7000 PCI: 00:01.0 cmd <- 00 PCI: 00:01.1 subsystem <- 8086/7010 PCI: 00:01.1 cmd <- 01 PCI: 00:01.3 cmd <- 00 PCI: 00:02.0 cmd <- 03 PCI: 00:03.0 cmd <- 03 done. BS: BS_DEV_ENABLE run times (exec / console): 1 / 3 ms Initializing devices... Root Device init Root Device init finished in 0 msecs CPU_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Intel device 663 CPU: family 06, model 06, stepping 03 Setting up local APIC... apic_id: 0x00 done. CPU #0 initialized CPU_CLUSTER: 0 init finished in 2 msecs PCI: 00:00.0 init Assigning IRQ 10 to PCI: 00:01.3 Assigning IRQ 11 to PCI: 00:03.0 PCI: 00:00.0 init finished in 7 msecs PCI: 00:01.0 init PCI: 00:01.0 init finished in 0 msecs PCI: 00:01.1 init PCI: 00:01.1 init finished in 0 msecs PCI: 00:02.0 init PCI: 00:02.0 init finished in 29 msecs PCI: 00:03.0 init PCI: 00:03.0 init finished in 0 msecs Devices initialized BS: BS_DEV_INIT run times (exec / console): 37 / 10 ms Finalize devices... Devices finalized BS: BS_POST_DEVICE run times (exec / console): 0 / 1 ms Copying Interrupt Routing Table to 0x000f0000... done. Copying Interrupt Routing Table to 0x3ffa6000... done. PIRQ table: 128 bytes. QEMU: found ACPI tables in fw_cfg. QEMU: loading "etc/acpi/rsdp" to 0x3ff82000 (len 20) QEMU: loading "etc/acpi/tables" to 0x3ff82040 (len 131072) QEMU: loaded ACPI tables from fw_cfg. Looking on 0x3ff82000 for valid checksum Checksum 1 passed Checksum 2 passed all OK ACPI: * SSDT ACPI: added table 4/32, length now 52 ACPI tables: 131136 bytes. smbios_write_tables: 3ff81000 SMBIOS: Unknown CPU DOMAIN: 0000 (QEMU Northbridge i440fx) QEMU: found smbios tables in fw_cfg (len 389). QEMU: coreboot type0 table found at 0x3ff81020. QEMU: loading smbios tables to 0x3ff81065 SMBIOS tables: 490 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 4fe4 Writing coreboot table at 0x3ffa7000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000003ff80fff: RAM 3. 000000003ff81000-000000003ffaffff: CONFIGURATION TABLES 4. 000000003ffb0000-000000003ffd2fff: RAMSTAGE 5. 000000003ffd3000-000000003fffffff: CONFIGURATION TABLES FMAP: area COREBOOT found @ 200 (261632 bytes) Wrote coreboot table at: 0x3ffa7000, 0x278 bytes, checksum 72ca coreboot table: 656 bytes. IMD ROOT 0. 0x3ffff000 0x00001000 IMD SMALL 1. 0x3fffe000 0x00001000 CONSOLE 2. 0x3ffde000 0x00020000 TIME STAMP 3. 0x3ffdd000 0x00000910 ROMSTG STCK 4. 0x3ffdc000 0x00001000 AFTER CAR 5. 0x3ffd3000 0x00009000 RAMSTAGE 6. 0x3ffaf000 0x00024000 COREBOOT 7. 0x3ffa7000 0x00008000 IRQ TABLE 8. 0x3ffa6000 0x00001000 ACPI 9. 0x3ff82000 0x00024000 SMBIOS 10. 0x3ff81000 0x00000800 IMD small region: IMD ROOT 0. 0x3fffec00 0x00000400 FMAP 1. 0x3fffeb40 0x000000b6 BS: BS_WRITE_TABLES run times (exec / console): 3 / 29 ms FMAP: area COREBOOT found @ 200 (261632 bytes) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 14e00 size 10f62 Checking segment from ROM address 0xfffd5038 Checking segment from ROM address 0xfffd5054 Loading segment from ROM address 0xfffd5038 code (compression=1) New segment dstaddr 0x000dfd60 memsize 0x202a0 srcaddr 0xfffd5070 filesize 0x10f2a Loading Segment: addr: 0x000dfd60 memsz: 0x00000000000202a0 filesz: 0x0000000000010f2a using LZMA Loading segment from ROM address 0xfffd5054 Entry Point 0x000fd26a BS: BS_PAYLOAD_LOAD run times (exec / console): 7 / 7 ms Jumping to boot code at 0x000fd26a(0x3ffa7000) SeaBIOS (version rel-1.13.0-0-gf21b5a4) BUILD: gcc: (Debian 10-20200222-1) 10.0.1 20200222 (experimental) [master revision 01af7e0a0c2:487fe13f218:e99b18cf7101f205bfdd9f0f29ed51caaec52779] binutils: (GNU Binutils for Debian) 2.34 SeaBIOS (version rel-1.13.0-0-gf21b5a4) BUILD: gcc: (Debian 10-20200222-1) 10.0.1 20200222 (experimental) [master revision 01af7e0a0c2:487fe13f218:e99b18cf7101f205bfdd9f0f29ed51caaec52779] binutils: (GNU Binutils for Debian) 2.34 Found coreboot cbmem console @ 3ffde000 Found mainboard Emulation QEMU x86 i440fx/piix4 Relocating init from 0x000e1460 to 0x3ff33ce0 (size 53888) Found CBFS header at 0xfffc0238 multiboot: eax=3ffc76c0, ebx=3ffc7684 Found 6 PCI devices (max PCI bus is 00) Copying SMBIOS entry point from 0x3ff81000 to 0x000f63e0 Copying ACPI RSDP from 0x3ff82000 to 0x000f63c0 Copying PIR from 0x3ffa6000 to 0x000f6340 Using pmtimer, ioport 0xe408 Scan for VGA option rom Running option rom at c000:0003 pmm call arg1=0 Turning on vga text mode console SeaBIOS (version rel-1.13.0-0-gf21b5a4) ATA controller 1 at 1f0/3f4/0 (irq 14 dev 9) ATA controller 2 at 170/374/0 (irq 15 dev 9) Found 1 lpt ports Found 1 serial ports PS2 keyboard initialized ata0-0: QEMU HARDDISK ATA-7 Hard-Disk (2048 MiBytes) Searching bootorder for: /pci@i0cf8/*@1,1/drive@0/disk@0 Searching bios-geometry for: /pci@i0cf8/*@1,1/drive@0/disk@0 DVD/CD [ata1-0: QEMU DVD-ROM ATAPI-4 DVD/CD] Searching bootorder for: /pci@i0cf8/*@1,1/drive@1/disk@0 Searching bios-geometry for: /pci@i0cf8/*@1,1/drive@1/disk@0 All threads complete. Scan for option roms Running option rom at ca00:0003 pmm call arg1=1 pmm call arg1=0 pmm call arg1=1 pmm call arg1=0 Searching bootorder for: /pci@i0cf8/*@3
Press ESC for boot menu.
Select boot device:
1. DVD/CD [ata1-0: QEMU DVD-ROM ATAPI-4 DVD/CD] 2. ata0-0: QEMU HARDDISK ATA-7 Hard-Disk (2048 MiBytes) 3. iPXE (PCI 00:03.0)
Searching bootorder for: HALT drive 0x000f62d0: PCHS=4161/16/63 translation=large LCHS=520/128/63 s=4194304 Space available for UMB: cb000-ed000, f5c00-f6270 Returned 262144 bytes of ZoneHigh e820 map has 5 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000003ff81000 = 1 RAM 4: 000000003ff81000 - 0000000040000000 = 2 RESERVED enter handle_19: NULL Booting from Hard Disk... Booting from 0000:7c00 ```
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39238 )
Change subject: Revert "i82371eb: Drop support for older PIIX chips" ......................................................................
Revert "i82371eb: Drop support for older PIIX chips"
This reverts commit 2b9004de602f98a404b17584ab3e1451f165c1f4.
Reason for revert: QEMU emulates that chipset and with that commit a Linux guest kernel can't find IDE devices anymore.
Change-Id: Iad75af4ea9993d6a2ec5433ad30d39900dab874e Signed-off-by: Patrick Georgi pgeorgi@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39238 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Keith Hui buurin@gmail.com --- M src/southbridge/intel/i82371eb/i82371eb.c M src/southbridge/intel/i82371eb/ide.c M src/southbridge/intel/i82371eb/isa.c M src/southbridge/intel/i82371eb/usb.c 4 files changed, 83 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Keith Hui: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c index 02812ce..898cdff 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.c +++ b/src/southbridge/intel/i82371eb/i82371eb.c @@ -14,9 +14,22 @@ * GNU General Public License for more details. */
-/* Note: This code supports the 82371AB/EB/MB. */ +/* Note: This code supports the 82371FB/SB/MX/AB/EB/MB and 82437MX. */
/* Datasheets: + * - Name: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR + * - URL: http://www.intel.com/design/intarch/datashts/290550.htm + * - PDF: http://download.intel.com/design/intarch/datashts/29055002.pdf + * - Date: April 1997 + * - Order Number: 290550-002 + * + * - Name: 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerator + * Specification Update + * - URL: http://www.intel.com/design/chipsets/specupdt/297658.htm + * - PDF: http://download.intel.com/design/chipsets/specupdt/29765801.pdf + * - Date: March 1998 + * - Order Number: 297658-004 + * * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) * (applies to 82371AB/EB/MB, a.k.a. PIIX4/PIIX4E/PIIX4M) * - URL: http://www.intel.com/design/intarch/datashts/290562.htm @@ -31,8 +44,10 @@ * - Order Number: 297738-017 */
+/* TODO: List the other datasheets. */ + #include <device/device.h>
const struct chip_operations southbridge_intel_i82371eb_ops = { - CHIP_NAME("Intel 82371AB/EB/MB Southbridge") + CHIP_NAME("Intel 82371FB/SB/MX/AB/EB/MB Southbridge") }; diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c index 1b8136a..7a72a65 100644 --- a/src/southbridge/intel/i82371eb/ide.c +++ b/src/southbridge/intel/i82371eb/ide.c @@ -119,6 +119,18 @@ }
/** + * IDE init for the Intel 82371FB/SB IDE controller. + * + * These devices do not support UDMA/33, so don't attempt to enable it. + * + * @param dev The device to use. + */ +static void ide_init_i82371fb_sb(struct device *dev) +{ + ide_init_enable(dev); +} + +/** * IDE init for the Intel 82371AB/EB/MB IDE controller. * * @param dev The device to use. @@ -129,6 +141,17 @@ ide_init_udma33(dev); }
+/* Intel 82371FB/SB */ +static const struct device_operations ide_ops_fb_sb = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init_i82371fb_sb, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, /* No subsystem IDs on 82371XX! */ +}; + /* Intel 82371AB/EB/MB */ static const struct device_operations ide_ops_ab_eb_mb = { .read_resources = pci_dev_read_resources, @@ -140,6 +163,34 @@ .ops_pci = 0, /* No subsystem IDs on 82371XX! */ };
+/* Intel 82371FB (PIIX) */ +static const struct pci_driver ide_driver_fb __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371FB_IDE, +}; + +/* Intel 82371SB (PIIX3) */ +static const struct pci_driver ide_driver_sb __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_IDE, +}; + +/* Intel 82371MX (MPIIX) */ +static const struct pci_driver ide_driver_mx __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371MX_ISA_IDE, +}; + +/* Intel 82437MX (part of the 430MX chipset) */ +static const struct pci_driver ide_driver_82437mx __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82437MX_ISA_IDE, +}; + /* Intel 82371AB/EB/MB */ static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = { .ops = &ide_ops_ab_eb_mb, diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index bdad959..3d1970c 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -145,3 +145,9 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82371AB_ISA, }; + +static const struct pci_driver isa_SB_driver __pci_driver = { + .ops = &isa_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_ISA, +}; diff --git a/src/southbridge/intel/i82371eb/usb.c b/src/southbridge/intel/i82371eb/usb.c index 38ab167..80b19a1 100644 --- a/src/southbridge/intel/i82371eb/usb.c +++ b/src/southbridge/intel/i82371eb/usb.c @@ -43,6 +43,15 @@ .ops_pci = 0, /* No subsystem IDs on 82371EB! */ };
+/* Note: No USB on 82371FB/MX (PIIX/MPIIX) and 82437MX. */ + +/* Intel 82371SB (PIIX3) */ +static const struct pci_driver usb_driver_sb __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_USB, +}; + /* Intel 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) */ /* The 440MX (82443MX) consists of 82443BX + 82371EB (uses same PCI IDs). */ static const struct pci_driver usb_driver_ab_eb_mb __pci_driver = {
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39238 )
Change subject: Revert "i82371eb: Drop support for older PIIX chips" ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1134 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1133 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1132
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Arthur Heymans (Code Review)
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Keith Hui (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)