coreboot-gerrit February 2020

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Change in coreboot[master]: util: add support for Zork
by Paul Fagerburg (Code Review) 09 Feb '20

09 Feb '20

Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38559 ) Change subject: util: add support for Zork ...................................................................... util: add support for Zork Update the create_coreboot_variant.sh and kconfig.py to support the zork baseboard. Full template files will be added in a later CL. BUG=b:148161697 BRANCH=None TEST=`./create_coreboot_variant.sh zork dalboz` and verify that the changes staged are correct. Change-Id: Ie0a29bb9f4bb8f3bb7eaeae8799cef861c395e7d --- M util/mainboard/google/create_coreboot_variant.sh M util/mainboard/google/kconfig.py A util/mainboard/google/zork/template/Makefile.inc 3 files changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/38559/1 diff --git a/util/mainboard/google/create_coreboot_variant.sh b/util/mainboard/google/create_coreboot_variant.sh index 14b2115..c4ca1c6 100755 --- a/util/mainboard/google/create_coreboot_variant.sh +++ b/util/mainboard/google/create_coreboot_variant.sh @@ -13,7 +13,7 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -VERSION="1.0.2" +VERSION="1.0.3" SCRIPT=$(basename -- "${0}") export LC_ALL=C @@ -61,6 +61,10 @@ # Copy the template tree to the target. mkdir -p "variants/${VARIANT}/" cp -pr "${SRC}/${BASE}/template/." "variants/${VARIANT}/" +if [[ -e "variants/${VARIANT}/Kconfig" ]]; then + sed -i -e "s/BOARD_GOOGLE_TEMPLATE/BOARD_GOOGLE_${VARIANT_UPPER}/" \ + "variants/${VARIANT}/Kconfig" +fi git add "variants/${VARIANT}/" # Now add the new variant to Kconfig and Kconfig.name diff --git a/util/mainboard/google/kconfig.py b/util/mainboard/google/kconfig.py index 6f9fccf..57d9610 100755 --- a/util/mainboard/google/kconfig.py +++ b/util/mainboard/google/kconfig.py @@ -41,7 +41,7 @@ help='Name of the board variant') args = parser.parse_args() - if args.board not in ['hatch', 'volteer']: + if args.board not in ['hatch', 'volteer', 'zork']: print('Unsupported baseboard "' + args.board + '"') sys.exit(1) @@ -130,6 +130,11 @@ print('\tbool "-> ' + capitalized + '"', file=outfile) print('\tselect BOARD_GOOGLE_BASEBOARD_VOLTEER', file=outfile) + if baseboard_name == 'zork': + print('\nconfig ' + 'BOARD_GOOGLE_' + uppercase, file=outfile) + print('\tbool "-> ' + capitalized + '"', file=outfile) + print('\tselect BOARD_GOOGLE_BASEBOARD_ZORK', file=outfile) + if __name__ == '__main__': main() diff --git a/util/mainboard/google/zork/template/Makefile.inc b/util/mainboard/google/zork/template/Makefile.inc new file mode 100644 index 0000000..38cf728 --- /dev/null +++ b/util/mainboard/google/zork/template/Makefile.inc @@ -0,0 +1,13 @@ +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = -- To view, visit https://review.coreboot.org/c/coreboot/+/38559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0a29bb9f4bb8f3bb7eaeae8799cef861c395e7d Gerrit-Change-Number: 38559 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Add initial configuration for serial IO ports
by Karthik Ramasubramanian (Code Review) 09 Feb '20

09 Feb '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38775 ) Change subject: mb/google/dedede: Add initial configuration for serial IO ports ...................................................................... mb/google/dedede: Add initial configuration for serial IO ports Add initial configuration for GSPI, I2C and UART ports and leave them in disabled state. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I1cd7659337e6330a8ece34df247e399a085d21d0 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/38775/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 44d9ca2..2a0b760 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -19,6 +19,39 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_H" + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device -- To view, visit https://review.coreboot.org/c/coreboot/+/38775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cd7659337e6330a8ece34df247e399a085d21d0 Gerrit-Change-Number: 38775 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Turn on ESPI device in devicetree
by Karthik Ramasubramanian (Code Review) 09 Feb '20

09 Feb '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38739 ) Change subject: mb/google/dedede: Turn on ESPI device in devicetree ...................................................................... mb/google/dedede: Turn on ESPI device in devicetree BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I12a63e5776619e5a7684cf1edad78b0fd6fac12c --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 2 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/38739/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cdd325c..26b20fe 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -40,7 +40,11 @@ device pci 1e.1 off end # UART 1 device pci 1e.2 off end # GSPI 0 device pci 1e.3 off end # GSPI 1 - device pci 1f.0 off end # eSPI Interface + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI Interface device pci 1f.1 off end # P2SB device pci 1f.2 off end # Power Management Controller device pci 1f.3 off end # Intel HDA/cAVS diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 6c95a1d..bd2ee37 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -13,7 +13,14 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* ToDo: Fill gpio configuration */ + /* GPP_A0 thru GPP_A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET_L ==> ESPI_RST_L */ }; /* Early pad configuration in bootblock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12a63e5776619e5a7684cf1edad78b0fd6fac12c Gerrit-Change-Number: 38739 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Add GPE configuration
by Karthik Ramasubramanian (Code Review) 09 Feb '20

09 Feb '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38771 ) Change subject: mb/google/dedede: Add GPE configuration ...................................................................... mb/google/dedede: Add GPE configuration Configure the GPIO groups to be routed to the GPE0 block. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ife4d0179bd9fe1785e971686478f7c76de805e87 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/38771/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cdd325c..aedd32f 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -3,6 +3,22 @@ device lapic 0 on end end + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. + # DW0 is used by: + # - GPP_B3 - TRACKPAD_INT_ODL + # - GPP_B4 - H1_AP_INT_ODL + # DW1 is used by: + # - GPP_D3 - WLAN_PCIE_WAKE_ODL + # DW2 is used by: + # - GPP_H16 - WWAN_HOST_WAKE + # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_H" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device -- To view, visit https://review.coreboot.org/c/coreboot/+/38771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife4d0179bd9fe1785e971686478f7c76de805e87 Gerrit-Change-Number: 38771 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Add Compute & PCH Global device IDs
by Karthik Ramasubramanian (Code Review) 09 Feb '20

09 Feb '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38738 ) Change subject: mb/google/dedede: Add Compute & PCH Global device IDs ...................................................................... mb/google/dedede: Add Compute & PCH Global device IDs Add compute and PCH Global device IDs with the concerned devices turned off. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I6f226abd52d4a27535de6711e93355b5f84a1941 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38738/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index eb9dc1c..cdd325c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -2,4 +2,50 @@ device cpu_cluster 0 on device lapic 0 on end end + + device domain 0 on + device pci 00.0 off end # Host Bridge + device pci 02.0 off end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 05.0 off end # IPU + device pci 09.0 off end # Intel Trace Hub + device pci 12.6 off end # GSPI 2 + device pci 14.0 off end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM + device pci 14.3 off end # CNVi wifi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 off end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 16.0 off end # HECI 1 + device pci 16.1 off end # HECI 2 + device pci 16.4 off end # HECI 3 + device pci 16.5 off end # HECI 4 + device pci 17.0 off end # SATA + device pci 19.0 off end # I2C 4 + device pci 19.1 off end # I2C 5 + device pci 19.2 off end # UART 2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Root Port 1 + device pci 1c.1 off end # PCI Express Root Port 2 + device pci 1c.2 off end # PCI Express Root Port 3 + device pci 1c.3 off end # PCI Express Root Port 4 - WLAN + device pci 1c.4 off end # PCI Express Root Port 5 + device pci 1c.5 off end # PCI Express Root Port 6 + device pci 1c.6 off end # PCI Express Root Port 7 + device pci 1c.7 off end # PCI Express Root Port 8 + device pci 1e.0 off end # UART 0 + device pci 1e.1 off end # UART 1 + device pci 1e.2 off end # GSPI 0 + device pci 1e.3 off end # GSPI 1 + device pci 1f.0 off end # eSPI Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 off end # Intel HDA/cAVS + device pci 1f.4 off end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.7 off end # Intel Trace Hub + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/38738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f226abd52d4a27535de6711e93355b5f84a1941 Gerrit-Change-Number: 38738 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: trogdor: update python scripts for python3
by mturney mturney (Code Review) 09 Feb '20

09 Feb '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38558 ) Change subject: trogdor: update python scripts for python3 ...................................................................... trogdor: update python scripts for python3 Change-Id: I46525243729c1dbcd30b346d4603452eea14ad9d Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M util/qualcomm/createxbl.py M util/qualcomm/ipqheader.py M util/qualcomm/mbn_tools.py M util/qualcomm/mbncat.py M util/qualcomm/qgpt.py 5 files changed, 171 insertions(+), 158 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/38558/1 diff --git a/util/qualcomm/createxbl.py b/util/qualcomm/createxbl.py index 9c6a9bc..4cac0c4 100755 --- a/util/qualcomm/createxbl.py +++ b/util/qualcomm/createxbl.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 #============================================================================ # #/** @file createxbl.py @@ -237,9 +237,9 @@ target_nonsec = target_base + "_combined_hash.mbn" - #print "Input file 1:", elf_inp_file1 - #print "Input file 2:", elf_inp_file2 - #print "Output file:", binary_out + #print("Input file 1:", elf_inp_file1) + #print("Input file 2:", elf_inp_file2) + #print("Output file:", binary_out) merge_elfs([], elf_inp_file1, @@ -268,7 +268,7 @@ elf_out_file_name = target_phdr_elf, secure_type = image_header_secflag, header_version = header_version ) if rv: - raise RuntimeError, "Failed to run pboot_gen_elf" + raise RuntimeError("Failed to run pboot_gen_elf") # Create hash table header rv = mbn_tools.image_header([], @@ -279,7 +279,7 @@ elf_file_name = source_elf, header_version = header_version) if rv: - raise RuntimeError, "Failed to create image header for hash segment" + raise RuntimeError("Failed to create image header for hash segment") files_to_cat_in_order = [target_hash_hd, target_hash] mbn_tools.concat_files (target_nonsec, files_to_cat_in_order) @@ -367,7 +367,7 @@ # Create a new ELF header for the output file if is_out_elf_64_bit: - out_elf_header = mbn_tools.Elf64_Ehdr('\0' * ELF64_HDR_SIZE) + out_elf_header = mbn_tools.Elf64_Ehdr(b'\0' * ELF64_HDR_SIZE) out_elf_header.e_phoff = ELF64_HDR_SIZE out_elf_header.e_ehsize = ELF64_HDR_SIZE out_elf_header.e_phentsize = ELF64_PHDR_SIZE @@ -382,7 +382,7 @@ out_elf_header.e_entry = elf_header1.e_entry else: - out_elf_header = mbn_tools.Elf32_Ehdr('\0' * ELF32_HDR_SIZE) + out_elf_header = mbn_tools.Elf32_Ehdr(b'\0' * ELF32_HDR_SIZE) out_elf_header.e_phoff = ELF32_HDR_SIZE out_elf_header.e_ehsize = ELF32_HDR_SIZE out_elf_header.e_phentsize = ELF32_PHDR_SIZE @@ -399,7 +399,7 @@ # Address needs to be verified that it is not greater than 32 bits # as it is possible to go from a 64 bit elf to 32. if (elf_header1.e_entry > 0xFFFFFFFF): - print "ERROR: File 1's entry point is too large to convert." + print("ERROR: File 1's entry point is too large to convert.") exit() out_elf_header.e_entry = elf_header1.e_entry @@ -455,7 +455,7 @@ # Copy program header piece by piece to ensure possible conversion success if is_out_elf_64_bit == True: # Converting from 32 to 64 elf requires no data size validation - new_phdr = mbn_tools.Elf64_Phdr('\0' * ELF64_PHDR_SIZE) + new_phdr = mbn_tools.Elf64_Phdr(b'\0' * ELF64_PHDR_SIZE) new_phdr.p_type = curr_phdr.p_type new_phdr.p_offset = segment_offset new_phdr.p_vaddr = curr_phdr.p_vaddr @@ -468,7 +468,7 @@ # Converting from 64 to 32 elf requires data size validation # Note that there is an option to discard a segment if it is only ZI # and its address is greater than 32 bits - new_phdr = mbn_tools.Elf32_Phdr('\0' * ELF32_PHDR_SIZE) + new_phdr = mbn_tools.Elf32_Phdr(b'\0' * ELF32_PHDR_SIZE) new_phdr.p_type = curr_phdr.p_type new_phdr.p_offset = segment_offset @@ -476,7 +476,7 @@ if (zi_oob_enabled == True) and (curr_phdr.p_filesz == 0): continue else: - print "ERROR: File 1 VAddr is too large for conversion." + print("ERROR: File 1 VAddr is too large for conversion.") exit() new_phdr.p_vaddr = curr_phdr.p_vaddr @@ -484,33 +484,33 @@ if (zi_oob_enabled == True) and (curr_phdr.p_filesz == 0): continue else: - print "ERROR: File 1 PAddr is too large for conversion." + print("ERROR: File 1 PAddr is too large for conversion.") exit() new_phdr.p_paddr = curr_phdr.p_paddr if curr_phdr.p_filesz > 0xFFFFFFFF: - print "ERROR: File 1 Filesz is too large for conversion." + print("ERROR: File 1 Filesz is too large for conversion.") exit() new_phdr.p_filesz = curr_phdr.p_filesz if curr_phdr.p_memsz > 0xFFFFFFFF: - print "ERROR: File 1 Memsz is too large for conversion." + print("ERROR: File 1 Memsz is too large for conversion.") exit() new_phdr.p_memsz = curr_phdr.p_memsz if curr_phdr.p_flags > 0xFFFFFFFF: - print "ERROR: File 1 Flags is too large for conversion." + print("ERROR: File 1 Flags is too large for conversion.") exit() new_phdr.p_flags = curr_phdr.p_flags if curr_phdr.p_align > 0xFFFFFFFF: - print "ERROR: File 1 Align is too large for conversion." + print("ERROR: File 1 Align is too large for conversion.") exit() new_phdr.p_align = curr_phdr.p_align - #print "i=",i - #print "phdr_offset=", phdr_offset + #print("i=",i) + #print("phdr_offset=", phdr_offset) # update output file location to next phdr location elf_out_fp.seek(phdr_offset) @@ -519,14 +519,14 @@ inp_data_offset = curr_phdr.p_offset # used to read data from input file -# print "inp_data_offset=" -# print inp_data_offset +# print("inp_data_offset=") +# print(inp_data_offset) # -# print "curr_phdr.p_offset=" -# print curr_phdr.p_offset +# print("curr_phdr.p_offset=") +# print(curr_phdr.p_offset) # -# print "curr_phdr.p_filesz=" -# print curr_phdr.p_filesz +# print("curr_phdr.p_filesz=") +# print(curr_phdr.p_filesz) # output current phdr if is_out_elf_64_bit == False: @@ -553,7 +553,7 @@ # Copy program header piece by piece to ensure possible conversion success if is_out_elf_64_bit == True: # Converting from 32 to 64 elf requires no data size validation - new_phdr = mbn_tools.Elf64_Phdr('\0' * ELF64_PHDR_SIZE) + new_phdr = mbn_tools.Elf64_Phdr(b'\0' * ELF64_PHDR_SIZE) new_phdr.p_type = curr_phdr.p_type new_phdr.p_offset = segment_offset new_phdr.p_vaddr = curr_phdr.p_vaddr @@ -566,7 +566,7 @@ # Converting from 64 to 32 elf requires data size validation # Note that there is an option to discard a segment if it is only ZI # and its address is greater than 32 bits - new_phdr = mbn_tools.Elf32_Phdr('\0' * ELF32_PHDR_SIZE) + new_phdr = mbn_tools.Elf32_Phdr(b'\0' * ELF32_PHDR_SIZE) new_phdr.p_type = curr_phdr.p_type new_phdr.p_offset = segment_offset @@ -574,7 +574,7 @@ if (zi_oob_enabled == True) and (curr_phdr.p_filesz == 0): continue else: - print "ERROR: File 2 VAddr is too large for conversion." + print("ERROR: File 2 VAddr is too large for conversion.") exit() new_phdr.p_vaddr = curr_phdr.p_vaddr @@ -582,33 +582,33 @@ if (zi_oob_enabled == True) and (curr_phdr.p_filesz == 0): continue else: - print "ERROR: File 2 PAddr is too large for conversion." + print("ERROR: File 2 PAddr is too large for conversion.") exit() new_phdr.p_paddr = curr_phdr.p_paddr if curr_phdr.p_filesz > 0xFFFFFFFF: - print "ERROR: File 2 Filesz is too large for conversion." + print("ERROR: File 2 Filesz is too large for conversion.") exit() new_phdr.p_filesz = curr_phdr.p_filesz if curr_phdr.p_memsz > 0xFFFFFFFF: - print "ERROR: File 2 Memsz is too large for conversion." + print("ERROR: File 2 Memsz is too large for conversion.") exit() new_phdr.p_memsz = curr_phdr.p_memsz if curr_phdr.p_flags > 0xFFFFFFFF: - print "ERROR: File 2 Flags is too large for conversion." + print("ERROR: File 2 Flags is too large for conversion.") exit() new_phdr.p_flags = curr_phdr.p_flags if curr_phdr.p_align > 0xFFFFFFFF: - print "ERROR: File 2 Align is too large for conversion." + print("ERROR: File 2 Align is too large for conversion.") exit() new_phdr.p_align = curr_phdr.p_align -# print "i=",i -# print "phdr_offset=", phdr_offset +# print("i=",i) +# print("phdr_offset=", phdr_offset) # update output file location to next phdr location elf_out_fp.seek(phdr_offset) @@ -617,14 +617,14 @@ inp_data_offset = curr_phdr.p_offset # used to read data from input file -# print "inp_data_offset=" -# print inp_data_offset +# print("inp_data_offset=") +# print(inp_data_offset) # -# print "curr_phdr.p_offset=" -# print curr_phdr.p_offset +# print("curr_phdr.p_offset=") +# print(curr_phdr.p_offset) # -# print "curr_phdr.p_filesz=" -# print curr_phdr.p_filesz +# print("curr_phdr.p_filesz=") +# print(curr_phdr.p_filesz) # output current phdr if is_out_elf_64_bit == False: @@ -656,14 +656,14 @@ entry_seg_offset = phdr.p_offset break if entry_seg_offset == -1: - print "Error: Failed to find entry point in any segment!" + print("Error: Failed to find entry point in any segment!") exit() # magical equation for program header's phys and virt addr phys_virt_addr = entry_addr - entry_seg_offset if is_out_elf_64_bit: # Converting from 32 to 64 elf requires no data size validation - new_phdr = mbn_tools.Elf64_Phdr('\0' * ELF64_PHDR_SIZE) + new_phdr = mbn_tools.Elf64_Phdr(b'\0' * ELF64_PHDR_SIZE) new_phdr.p_type = 0x1 new_phdr.p_offset = segment_offset new_phdr.p_vaddr = phys_virt_addr @@ -671,36 +671,36 @@ new_phdr.p_filesz = os.path.getsize(elf_in_file_xbl_sec) new_phdr.p_memsz = new_phdr.p_filesz if header_version == 5 or header_version == 6: - new_phdr.p_flags = (0x5 | - (mbn_tools.MI_PBT_XBL_SEC_SEGMENT << - mbn_tools.MI_PBT_FLAG_SEGMENT_TYPE_SHIFT)); + new_phdr.p_flags = (0x5 | + (mbn_tools.MI_PBT_XBL_SEC_SEGMENT << + mbn_tools.MI_PBT_FLAG_SEGMENT_TYPE_SHIFT)); else: - new_phdr.p_flags = 0x5 + new_phdr.p_flags = 0x5 new_phdr.p_align = 0x1000 else: # Converting from 64 to 32 elf requires data size validation # Don't discard the segment containing xbl_sec, simply error out # if the address is greater than 32 bits - new_phdr = mbn_tools.Elf32_Phdr('\0' * ELF32_PHDR_SIZE) + new_phdr = mbn_tools.Elf32_Phdr(b'\0' * ELF32_PHDR_SIZE) new_phdr.p_type = 0x1 # new_phdr.p_offset = segment_offset if header_version == 5 or header_version == 6: - new_phdr.p_flags = (0x5 | - (mbn_tools.MI_PBT_XBL_SEC_SEGMENT << - mbn_tools.MI_PBT_FLAG_SEGMENT_TYPE_SHIFT)); + new_phdr.p_flags = (0x5 | + (mbn_tools.MI_PBT_XBL_SEC_SEGMENT << + mbn_tools.MI_PBT_FLAG_SEGMENT_TYPE_SHIFT)); else: - new_phdr.p_flags = 0x5 + new_phdr.p_flags = 0x5 new_phdr.p_align = 0x1000 if phys_virt_addr > 0xFFFFFFFF: if zi_oob_enabled == False or curr_phdr.p_filesz != 0: - print "ERROR: File xbl_sec VAddr or PAddr is too big for conversion." + print("ERROR: File xbl_sec VAddr or PAddr is too big for conversion.") exit() new_phdr.p_vaddr = phys_virt_addr new_phdr.p_paddr = phys_virt_addr if os.path.getsize(elf_in_file_xbl_sec) > 0xFFFFFFFF: - print "ERROR: File xbl_sec Filesz is too big for conversion." + print("ERROR: File xbl_sec Filesz is too big for conversion.") exit() new_phdr.p_filesz = os.path.getsize(elf_in_file_xbl_sec) new_phdr.p_memsz = new_phdr.p_filesz diff --git a/util/qualcomm/ipqheader.py b/util/qualcomm/ipqheader.py index 7615146..fe14e1f 100755 --- a/util/qualcomm/ipqheader.py +++ b/util/qualcomm/ipqheader.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # # Copyright (c) 2013 The Linux Foundation. All rights reserved. # @@ -97,7 +97,7 @@ if msg != None: sys.stderr.write("%s: %s\n" % (PROG_NAME, msg)) - print "Usage: %s <base-addr> <input-file> <output-file>" % PROG_NAME + print("Usage: %s <base-addr> <input-file> <output-file>" % PROG_NAME) if msg != None: exit(1) diff --git a/util/qualcomm/mbn_tools.py b/util/qualcomm/mbn_tools.py index 9c403a7..a4a2f62 100755 --- a/util/qualcomm/mbn_tools.py +++ b/util/qualcomm/mbn_tools.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 #=============================================================================== # # MBN TOOLS @@ -103,24 +103,24 @@ ELFINFO_MAG1_INDEX = 1 ELFINFO_MAG2_INDEX = 2 ELFINFO_MAG3_INDEX = 3 -ELFINFO_MAG0 = '\x7f' -ELFINFO_MAG1 = 'E' -ELFINFO_MAG2 = 'L' -ELFINFO_MAG3 = 'F' +ELFINFO_MAG0 = 127 # 0x7F +ELFINFO_MAG1 = 69 # E +ELFINFO_MAG2 = 76 # L +ELFINFO_MAG3 = 70 # F ELFINFO_CLASS_INDEX = 4 -ELFINFO_CLASS_32 = '\x01' -ELFINFO_CLASS_64 = '\x02' +ELFINFO_CLASS_32 = 1 +ELFINFO_CLASS_64 = 2 ELFINFO_VERSION_INDEX = 6 -ELFINFO_VERSION_CURRENT = '\x01' +ELFINFO_VERSION_CURRENT = 1 ELF_BLOCK_ALIGN = 0x1000 ALIGNVALUE_1MB = 0x100000 ALIGNVALUE_4MB = 0x400000 -ELFINFO_DATA2LSB = '\x01' -ELFINFO_EXEC_ETYPE = '\x02\x00' -ELFINFO_ARM_MACHINETYPE = '\x28\x00' -ELFINFO_VERSION_EV_CURRENT = '\x01\x00\x00\x00' +ELFINFO_DATA2LSB = b'\x01' +ELFINFO_EXEC_ETYPE = b'\x02\x00' +ELFINFO_ARM_MACHINETYPE = b'\x28\x00' +ELFINFO_VERSION_EV_CURRENT = b'\x01\x00\x00\x00' ELFINFO_SHOFF = 0x00 -ELFINFO_PHNUM = '\x01\x00' +ELFINFO_PHNUM = b'\x01\x00' ELFINFO_RESERVED = 0x00 # ELF Program Header Types @@ -334,9 +334,9 @@ self.e_version = unpacked_data[3] def printValues(self): - print "ATTRIBUTE / VALUE" - for attr, value in self.__dict__.iteritems(): - print attr, value + print("ATTRIBUTE / VALUE") + for attr, value in self.__dict__.items(): + print(attr, value) @@ -366,9 +366,9 @@ self.e_shstrndx = unpacked_data[13] def printValues(self): - print "ATTRIBUTE / VALUE" - for attr, value in self.__dict__.iteritems(): - print attr, value + print("ATTRIBUTE / VALUE") + for attr, value in self.__dict__.items(): + print(attr, value) def getPackedData(self): values = [self.e_ident, @@ -410,9 +410,9 @@ self.p_align = unpacked_data[7] def printValues(self): - print "ATTRIBUTE / VALUE" - for attr, value in self.__dict__.iteritems(): - print attr, value + print("ATTRIBUTE / VALUE") + for attr, value in self.__dict__.items(): + print(attr, value) def getPackedData(self): values = [self.p_type, @@ -453,12 +453,16 @@ self.e_shstrndx = unpacked_data[13] def printValues(self): - print "ATTRIBUTE / VALUE" - for attr, value in self.__dict__.iteritems(): - print attr, value + print("ATTRIBUTE / VALUE") + for attr, value in self.__dict__.items(): + print(attr, value) def getPackedData(self): - values = [self.e_ident, + if type(self.e_ident) == str: + packvalue = bytes(self.e_ident, 'utf-8') + else: + packvalue = self.e_ident + values = [packvalue, self.e_type, self.e_machine, self.e_version, @@ -497,9 +501,9 @@ self.p_align = unpacked_data[7] def printValues(self): - print "ATTRIBUTE / VALUE" - for attr, value in self.__dict__.iteritems(): - print attr, value + print("ATTRIBUTE / VALUE") + for attr, value in self.__dict__.items(): + print(attr, value) def getPackedData(self): values = [self.p_type, @@ -522,7 +526,7 @@ def __init__(self): self.flag = 0 def printValues(self): - print 'Flag: ' + str(self.flag) + print('Flag: ' + str(self.flag)) #---------------------------------------------------------------------------- # Regular Boot Header Class @@ -744,7 +748,7 @@ xml_target_file.close() else: xml_target_file.close() - raise RuntimeError, "XML Size too large: " + str(xml_header_size) + raise RuntimeError("XML Size too large: " + str(xml_header_size)) #---------------------------------------------------------------------------- # encrypt_mbn @@ -835,7 +839,7 @@ is_elf_64_bit = False): if (output_file_name is None): - raise RuntimeError, "Requires a ELF header file" + raise RuntimeError("Requires a ELF header file") # Create a elf header and program header # Write the headers to the output file @@ -926,13 +930,13 @@ # Preliminary checks if (requires_preamble is True) and (preamble_file_name is None): - raise RuntimeError, "Image Header requires a preamble file" + raise RuntimeError("Image Header requires a preamble file") if (gen_dict['IMAGE_KEY_MBN_TYPE'] == 'elf') and (elf_file_name is None): - raise RuntimeError, "ELF Image Headers require an elf file" + raise RuntimeError("ELF Image Headers require an elf file") if (in_code_size is None) and (os.path.exists(code_file_name) is False): - raise RuntimeError, "Code size unavailable, and input file does not exist" + raise RuntimeError("Code size unavailable, and input file does not exist") # Initialize if in_code_size is not None: @@ -1024,7 +1028,7 @@ boot_header.writePackedData(target = output_file_name, write_full_hdr = write_full_hdr) else: - raise RuntimeError, "Header format not supported: " + str(header_format) + raise RuntimeError("Header format not supported: " + str(header_format)) return 0 @@ -1073,15 +1077,15 @@ hashtable_shift = 0 if elf_header.e_ident[ELFINFO_CLASS_INDEX] == ELFINFO_CLASS_64: - new_phdr = Elf64_Phdr('\0' * ELF64_PHDR_SIZE) + new_phdr = Elf64_Phdr(b'\0' * ELF64_PHDR_SIZE) elf_header_size = ELF64_HDR_SIZE is_elf64 = True else: - new_phdr = Elf32_Phdr('\0' * ELF32_PHDR_SIZE) + new_phdr = Elf32_Phdr(b'\0' * ELF32_PHDR_SIZE) elf_header_size = ELF32_HDR_SIZE is_elf64 = False - hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE + hash = b'\0' * MI_PROG_BOOT_DIGEST_SIZE phdr_start = 0 bytes_to_pad = 0 hash_seg_end = 0 @@ -1090,7 +1094,7 @@ if elf_out_file_name is not None: # Assert limit on number of program headers in input ELF if num_phdrs > MAX_PHDR_COUNT: - raise RuntimeError, "Input ELF has exceeded maximum number of program headers" + raise RuntimeError("Input ELF has exceeded maximum number of program headers") # Create new program header for the ELF Header + Program Headers new_phdr.p_type = NULL_TYPE @@ -1100,11 +1104,11 @@ elf_header.e_phnum += 2 # Create an empty hash entry for PHDR_TYPE - hash_out_fp.write('\0' * MI_PROG_BOOT_DIGEST_SIZE) + hash_out_fp.write(b'\0' * MI_PROG_BOOT_DIGEST_SIZE) hashtable_size += MI_PROG_BOOT_DIGEST_SIZE # Create an empty hash entry for the hash segment itself - hash_out_fp.write('\0' * MI_PROG_BOOT_DIGEST_SIZE) + hash_out_fp.write(b'\0' * MI_PROG_BOOT_DIGEST_SIZE) hashtable_size += MI_PROG_BOOT_DIGEST_SIZE # Begin hash table generation @@ -1124,7 +1128,7 @@ # Seg_size should be page aligned if (seg_size & (ELF_BLOCK_ALIGN - 1)) > 0: - raise RuntimeError, "seg_size: " + hex(seg_size) + " is not ELF page aligned!" + raise RuntimeError("seg_size: " + hex(seg_size) + " is not ELF page aligned!") off = seg_offset + seg_size @@ -1141,7 +1145,7 @@ if MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True: hash = generate_hash(fbuf, sha_algo) else: - hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE + hash = b'\0' * MI_PROG_BOOT_DIGEST_SIZE # Write hash to file hash_out_fp.write(hash) @@ -1160,7 +1164,7 @@ if (MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True) and (data_len > 0): hash = generate_hash(file_buff, sha_algo) else: - hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE + hash = b'\0' * MI_PROG_BOOT_DIGEST_SIZE # Write hash to file hash_out_fp.write(hash) @@ -1186,9 +1190,9 @@ if (hash_seg_max_size is not None): # Error checking for hash segment size validity if hashtable_size > hash_seg_max_size: - raise RuntimeError, "Hash table exceeds maximum hash segment size: " + hex(hash_seg_max_size) + raise RuntimeError("Hash table exceeds maximum hash segment size: " + hex(hash_seg_max_size)) if (hash_seg_max_size & (ELF_BLOCK_ALIGN-1)) is not 0: - raise RuntimeError, "Hash segment size passed is not ELF Block Aligned: " + hex(hash_seg_max_size) + raise RuntimeError("Hash segment size passed is not ELF Block Aligned: " + hex(hash_seg_max_size)) # Check if hash physical address parameter was passed if last_phys_addr is not None: @@ -1331,7 +1335,7 @@ file_copy_offset(hash_tbl_fp, 0, elf_out_fp, hash_hdr_offset, hash_size) else: - raise RuntimeError, "Hash segment program header not found in file " + elf_in_file_name + raise RuntimeError("Hash segment program header not found in file " + elf_in_file_name) # Close files elf_in_fp.close() @@ -1346,7 +1350,7 @@ def image_auth(env, *args): if len(args) < 7 or len(args) > 8: - raise RuntimeError, "Usage Invalid" + raise RuntimeError("Usage Invalid") # Initialize File Names binary_in = args[0] @@ -1376,7 +1380,7 @@ num_certs = num_certs + 1 if (num_certs == 0): - raise RuntimeError, "Missing file(s) required for signing.\n" + raise RuntimeError("Missing file(s) required for signing.\n") # Create the Certificate Chain concat_files (cert_chain_out, cert_list) @@ -1390,7 +1394,7 @@ pad_file(cert_fp, bytes_to_pad, PAD_BYTE_1) cert_fp.close() else: - raise RuntimeError, "Certificate Size too large: " + str(cert_size) + raise RuntimeError("Certificate Size too large: " + str(cert_size)) # Create the Final Signed Image File concat_files (signed_image_out, [binary_in, signature, cert_chain_out]) @@ -1495,7 +1499,7 @@ # Check for corresponding number of segments if len(segment_list) is not elf_header.e_phnum: - raise RuntimeError, 'SCL file and ELF file have different number of segments!' + raise RuntimeError('SCL file and ELF file have different number of segments!') # Go to the start of the p_flag entry in the first program header file_offset = elf_header.e_phoff + phdr_flag_off @@ -1602,11 +1606,11 @@ (curr_phdr.p_flags & PH_PERM_MASK) == PH_PERM_RX and curr_pages == code_seg_pages): if (code_seg_idx != -1): - raise RuntimeError, 'Multiple code segments match for: ' + code_seg_pages + ' pages' + raise RuntimeError('Multiple code segments match for: ' + code_seg_pages + ' pages') code_seg_idx = i if (code_seg_idx == -1): - raise RuntimeError, 'No matching code segment found' + raise RuntimeError('No matching code segment found') code_phdr = phdr_table[code_seg_idx] @@ -1680,7 +1684,7 @@ # Token 1: Segment Name # Token 2: Start Address -- not used in MBN tools if len(tokens) < 2: - raise RuntimeError, 'SCL Segment Syntax malformed: ' + previous_line + raise RuntimeError('SCL Segment Syntax malformed: ' + previous_line) # Get the segment flags corresponding to the segment name description new_scl_entry.flag = getSegmentFlag(tokens[0].strip(strip_chars)) @@ -1727,7 +1731,7 @@ UNSECURE = "UNSECURE" if seg_info is None or len(seg_info) is 0: - raise RuntimeError, 'Invalid segment information passed: ' + seg_info + raise RuntimeError('Invalid segment information passed: ' + seg_info) # Conditional checks and assignments of the corresponding segment flag values if NOTPAGEABLE in seg_info: @@ -1789,7 +1793,7 @@ ret_val = MI_PBT_ELF_UNSECURE_SEGMENT else: - raise RuntimeError, 'The segment name is wrongly defined in the SCL file: ' + seg_info + raise RuntimeError('The segment name is wrongly defined in the SCL file: ' + seg_info) return ret_val @@ -1800,7 +1804,7 @@ def pad_file(fp, num_bytes, value): if num_bytes < 0: - raise RuntimeError, "Number of bytes to pad must be greater than zero" + raise RuntimeError("Number of bytes to pad must be greater than zero") while num_bytes > 0: fp.write('%c' % value) @@ -1869,7 +1873,7 @@ def populate_dictionary(*args): if len(args) < 1: - raise RuntimeError, "At least 1 file must be specified as an input" + raise RuntimeError("At least 1 file must be specified as an input") global_dict = {} Fields = ["Define", "Key", "Value"] @@ -1922,11 +1926,11 @@ # Check for Image Type # If IMAGE_TYPE parameter is not provided, raise error if not kwargs.has_key('IMAGE_TYPE'): - raise RuntimeError, "IMAGE_TYPE must be defined to use FilterDictionary." + raise RuntimeError("IMAGE_TYPE must be defined to use FilterDictionary.") else: image_type = kwargs.get('IMAGE_TYPE') if type(image_type) is not str: - raise RuntimeError, "IMAGE_TYPE must be of string type." + raise RuntimeError("IMAGE_TYPE must be of string type.") # Check for Flash Type # If FLASH_TYPE parameter is not provided, default to 'nand' @@ -1935,7 +1939,7 @@ else: flash_type = kwargs.get('FLASH_TYPE') if type(flash_type) is not str: - raise RuntimeError, "FLASH_TYPE must be of string type. " + raise RuntimeError("FLASH_TYPE must be of string type. ") # Check for MBN Type # If MBN_TYPE parameter is not provided, default to 'elf' @@ -1944,7 +1948,7 @@ else: mbn_type = kwargs.get('MBN_TYPE') if mbn_type != 'elf' and mbn_type != 'bin': - raise RuntimeError, "MBN_TYPE currently not supported: " + mbn_type + raise RuntimeError("MBN_TYPE currently not supported: " + mbn_type) # Check for Image ID # If IMAGE_ID parameter is not provided, default to ID 0 @@ -1953,7 +1957,7 @@ else: image_id = kwargs.get('IMAGE_ID') if type(image_id) is not int: - raise RuntimeError, "IMAGE_ID must be of integer type." + raise RuntimeError("IMAGE_ID must be of integer type.") # Initialize gen_dict = {} @@ -1978,9 +1982,9 @@ if template_key_match in global_dict: image_dest = global_dict[template_key_match] else: - raise RuntimeError, "Builds file does not have IMAGE_KEY pair for: " + image_type + raise RuntimeError("Builds file does not have IMAGE_KEY pair for: " + image_type) else: - raise RuntimeError, "MBN_TYPE currently not supported: " + mbn_type + raise RuntimeError("MBN_TYPE currently not supported: " + mbn_type) # Assign generic dictionary key/value pairs gen_dict['IMAGE_KEY_IMAGE_ID'] = id @@ -2011,7 +2015,7 @@ gen_dict['IMAGE_KEY_OEM_NUM_ROOT_CERTS'] = oem_num_root_certs else: - raise RuntimeError, "Invalid OEM root certificate configuration values" + raise RuntimeError("Invalid OEM root certificate configuration values") # Assign additional dictionary key/values pair as needed by tools. @@ -2041,7 +2045,7 @@ elf_header = Elf_Ehdr_common(elf_fp.read(ELF_HDR_COMMON_SIZE)) if verify_elf_header(elf_header) is False: - raise RuntimeError, "ELF file failed verification: " + elf_file_name + raise RuntimeError("ELF file failed verification: " + elf_file_name) elf_fp.seek(0) @@ -2054,7 +2058,7 @@ # Verify ELF header information if verify_elf_header(elf_header) is False: - raise RuntimeError, "ELF file failed verification: " + elf_file_name + raise RuntimeError("ELF file failed verification: " + elf_file_name) # Get program header size phdr_size = elf_header.e_phentsize @@ -2104,17 +2108,26 @@ # Verify ELF header contents from an input ELF file #---------------------------------------------------------------------------- def verify_elf_header(elf_header): - if (elf_header.e_ident[ELFINFO_MAG0_INDEX] != ELFINFO_MAG0) or \ - (elf_header.e_ident[ELFINFO_MAG1_INDEX] != ELFINFO_MAG1) or \ - (elf_header.e_ident[ELFINFO_MAG2_INDEX] != ELFINFO_MAG2) or \ - (elf_header.e_ident[ELFINFO_MAG3_INDEX] != ELFINFO_MAG3) or \ - ((elf_header.e_ident[ELFINFO_CLASS_INDEX] != ELFINFO_CLASS_64) and \ - (elf_header.e_ident[ELFINFO_CLASS_INDEX] != ELFINFO_CLASS_32)) or \ - (elf_header.e_ident[ELFINFO_VERSION_INDEX] != ELFINFO_VERSION_CURRENT): - + if (elf_header.e_ident[ELFINFO_MAG0_INDEX] != ELFINFO_MAG0): + print("MAG0[{:d}]\n".format((elf_header.e_ident[ELFINFO_MAG0_INDEX]))) return False - else: - return True + if (elf_header.e_ident[ELFINFO_MAG1_INDEX] != ELFINFO_MAG1): + print("MAG1[{:d}]\n".format((elf_header.e_ident[ELFINFO_MAG1_INDEX]))) + return False + if (elf_header.e_ident[ELFINFO_MAG2_INDEX] != ELFINFO_MAG2): + print("MAG2[{:d}]\n".format((elf_header.e_ident[ELFINFO_MAG2_INDEX]))) + return False + if (elf_header.e_ident[ELFINFO_MAG3_INDEX] != ELFINFO_MAG3): + print("MAG3[{:d}]\n".format((elf_header.e_ident[ELFINFO_MAG3_INDEX]))) + return False + if ((elf_header.e_ident[ELFINFO_CLASS_INDEX] != ELFINFO_CLASS_64) and \ + (elf_header.e_ident[ELFINFO_CLASS_INDEX] != ELFINFO_CLASS_32)): + print("ELFINFO_CLASS_INDEX[{:d}]\n".format((elf_header.e_ident[ELFINFO_CLASS_INDEX]))) + return False + if (elf_header.e_ident[ELFINFO_VERSION_INDEX] != ELFINFO_VERSION_CURRENT): + print("ELFINFO_VERSION_INDEX[{:d}]\n".format((elf_header.e_ident[ELFINFO_VERSION_INDEX]))) + return False + return True #---------------------------------------------------------------------------- # Perform file copy given offsets and the number of bytes to copy @@ -2166,9 +2179,9 @@ # Update the hash table program header if is_elf64 is True: - hash_Phdr = Elf64_Phdr('\0'*ELF64_PHDR_SIZE) + hash_Phdr = Elf64_Phdr(b'\0'*ELF64_PHDR_SIZE) else: - hash_Phdr = Elf32_Phdr('\0'*ELF32_PHDR_SIZE) + hash_Phdr = Elf32_Phdr(b'\0'*ELF32_PHDR_SIZE) hash_Phdr.p_flags = MI_PBT_ELF_HASH_SEGMENT hash_Phdr.p_align = ELF_BLOCK_ALIGN hash_Phdr.p_offset = hash_hdr_offset @@ -2250,7 +2263,7 @@ try: fp = open(file_name, mode) except IOError: - raise RuntimeError, "The file could not be opened: " + file_name + raise RuntimeError("The file could not be opened: " + file_name) # File open has succeeded with the given mode, return the file object return fp diff --git a/util/qualcomm/mbncat.py b/util/qualcomm/mbncat.py index c4da265..4113bc2 100755 --- a/util/qualcomm/mbncat.py +++ b/util/qualcomm/mbncat.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # Copyright (c) 2014, The Linux Foundation. All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -75,27 +75,27 @@ self.verbose = verbose self.mbn_file_names = [] if self.verbose: - print 'Reading ' + sbl1 + print('Reading ' + sbl1) try: self.sbl1 = open(sbl1, 'rb').read() except IOError as e: - print 'I/O error({0}): {1}'.format(e.errno, e.strerror) + print('I/O error({0}): {1}'.format(e.errno, e.strerror)) raise (codeword, magic, _) = struct.unpack_from( self.NOR_SBL1_HEADER, self.sbl1) if codeword != self.NOR_CODE_WORD: - print '\n\nError: Unexpected Codeword!' - print 'Codeword : ' + ('0x%x' % self.NOR_CODE_WORD) + \ - ' != ' + ('0x%x' % codeword) + print('\n\nError: Unexpected Codeword!') + print('Codeword : ' + ('0x%x' % self.NOR_CODE_WORD) + \ + ' != ' + ('0x%x' % codeword)) sys.exit(-1) if magic != self.MAGIC_NUM: - print '\n\nError: Unexpected Magic!' - print 'Magic : ' + ('0x%x' % self.MAGIC_NUM) + \ - ' != ' + ('0x%x' % magic) + print('\n\nError: Unexpected Magic!') + print('Magic : ' + ('0x%x' % self.MAGIC_NUM) + \ + ' != ' + ('0x%x' % magic)) sys.exit(-1) def Append(self, src): @@ -122,7 +122,7 @@ pad = '\377' * pad_size outfile.write(pad) if self.verbose: - print 'Added %d byte padding' % pad_size + print('Added %d byte padding' % pad_size) return pad_size return 0 @@ -145,8 +145,8 @@ mbn_file_data = open(mbn_file_name, 'r').read() outfile.write(mbn_file_data) if self.verbose: - print 'Added %s (%d bytes)' % (mbn_file_name, - len(mbn_file_data)) + print('Added %s (%d bytes)' % (mbn_file_name, + len(mbn_file_data))) total_size += len(mbn_file_data) outfile.seek(28) @@ -155,13 +155,13 @@ def Usage(v): - print '%s: [-v] [-h] [-o Output MBN] sbl1 sbl2 [bootblock]' % ( - os.path.basename(sys.argv[0])) - print - print 'Concatenates up to three mbn files: two SBLs and a coreboot bootblock' - print ' -h This message' - print ' -v verbose' - print ' -o Output file name, (default: %s)\n' % DEFAULT_OUTPUT_FILE_NAME + print('%s: [-v] [-h] [-o Output MBN] sbl1 sbl2 [bootblock]' % ( + os.path.basename(sys.argv[0]))) + print() + print('Concatenates up to three mbn files: two SBLs and a coreboot bootblock') + print(' -h This message') + print(' -v verbose') + print(' -o Output file name, (default: %s)\n' % DEFAULT_OUTPUT_FILE_NAME) sys.exit(v) def main(): diff --git a/util/qualcomm/qgpt.py b/util/qualcomm/qgpt.py index 0b096b9..fbf6d10 100755 --- a/util/qualcomm/qgpt.py +++ b/util/qualcomm/qgpt.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 #============================================================================ # #/** @file qgpt.py -- To view, visit https://review.coreboot.org/c/coreboot/+/38558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46525243729c1dbcd30b346d4603452eea14ad9d Gerrit-Change-Number: 38558 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: soc/intel/tigerlake: add memory configuration support
by Nick Vaccaro (Code Review) 09 Feb '20

09 Feb '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38606 ) Change subject: soc/intel/tigerlake: add memory configuration support ...................................................................... soc/intel/tigerlake: add memory configuration support Move some of the common memory code that was being performed in mainboard into the soc to reduce redundant code going forward. BUG=b:145642089 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel and verify memory size shows 8GB. Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/include/soc/meminit.h A src/soc/intel/tigerlake/meminit.c 3 files changed, 205 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/38606/1 diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 532861d..c1bac36 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += espi.c romstage-y += gpio.c +romstage-y += meminit.c romstage-y += reset.c ramstage-y += acpi.c diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h new file mode 100644 index 0000000..a99b033 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_MEMINIT_H_ +#define _SOC_TIGERLAKE_MEMINIT_H_ + +#include <stddef.h> +#include <stdint.h> +#include <fsp/soc_binding.h> + +#define BYTES_PER_CHANNEL 2 +#define BITS_PER_BYTE 8 +#define DQS_PER_CHANNEL 2 +#define NUM_CHANNELS 8 + +struct spd_by_pointer { + size_t spd_data_len; + uintptr_t spd_data_ptr; +}; + +enum lpddr4x_mem_info_read_type { + NOT_EXISTING, /* No memory in this channel */ + READ_SPD_CBFS, /* Find spd file in CBFS. */ + READ_SPD_MEMPTR /* Find spd data from pointer. */ +}; + +struct lpddr4x_spd_info { + enum lpddr4x_mem_info_read_type read_type; + union spd_data_by { + /* To identify spd file when read_type is READ_SPD_CBFS. */ + int spd_index; + + /* To find spd data when read_type is READ_SPD_MEMPTR. */ + struct spd_by_pointer spd_data_ptr_info; + } spd_spec; +}; + +/* Board-specific memory configuration information */ +struct mb_lpddr4x_cfg { + /* SPD info */ + struct lpddr4x_spd_info spd; + + /* DQ mapping */ + uint8_t dq_map[NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; + + /* + * DQS CPU<>DRAM map MC0 and MC1. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + */ + uint8_t dqs_map[NUM_CHANNELS][DQS_PER_CHANNEL]; + + /* + * Early Command Training Enable/Disable Control + * 1 = enable, 0 = disable + */ + uint8_t ect; + + /* Set to true if only populating half the DRAM */ + bool half_populated; +}; + +/* Initialize default memory configurations for lpddr4x */ +void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, struct mb_lpddr4x_cfg *board_cfg); + +#endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c new file mode 100644 index 0000000..4c2199b --- /dev/null +++ b/src/soc/intel/tigerlake/meminit.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <assert.h> +#include <console/console.h> +#include <fsp/util.h> +#include <soc/meminit.h> +#include <spd_bin.h> +#include <string.h> + +/* If half populating DRAM, those channels would be 0 thru 3 */ +#define HALF_POPULATED_COUNT 4 + +enum dimm_enable_options { + ENABLE_BOTH_DIMMS = 0, + DISABLE_DIMM0 = 1, + DISABLE_DIMM1 = 2, + DISABLE_BOTH_DIMMS = 3 +}; + +/* Configure memory channel as unpopulated */ +#define MEM_CFG_EMPTY(_mem_cfg, _mc, _ch) \ + do { \ + _mem_cfg->DisableDimmMc ## _mc ## Ch ## _ch = DISABLE_BOTH_DIMMS; \ + _mem_cfg->MemorySpdPtr ## _mc ## _ch ## 0 = 0; \ + _mem_cfg->MemorySpdPtr ## _mc ## _ch ## 1 = 0; \ + } while (0) + +/* Configure memory channel with only dimm0 used */ +#define MEM_CFG_DIMM0(_mem_cfg, _mc, _ch, _data, _b_cfg) \ + do { \ + _mem_cfg->DisableDimmMc ## _mc ## Ch ## _ch = DISABLE_DIMM1; \ + _mem_cfg->MemorySpdPtr ## _mc ## _ch ## 0 = _data; \ + _mem_cfg->MemorySpdPtr ## _mc ## _ch ## 1 = 0; \ + memcpy(&_mem_cfg->DqMapCpu2DramMc ## _mc ## Ch ## _ch, \ + &_b_cfg->dq_map[_mc * NUM_CHANNELS / 2 + _ch], \ + sizeof(_b_cfg->dq_map[_mc * NUM_CHANNELS / 2 + _ch])); \ + memcpy(&_mem_cfg->DqsMapCpu2DramMc ## _mc ## Ch ## _ch, \ + &_b_cfg->dqs_map[_mc * NUM_CHANNELS / 2 + _ch], \ + sizeof(_b_cfg->dqs_map[_mc * NUM_CHANNELS / 2 + _ch])); \ + } while (0) + + +static void spd_read_from_cbfs(const struct lpddr4x_spd_info *spd, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + struct region_device spd_rdev; + size_t spd_index = spd->spd_spec.spd_index; + + printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + *spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); +} + +static void get_spd_data(const struct lpddr4x_spd_info *spd, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + if (spd->read_type == READ_SPD_MEMPTR) { + *spd_data_ptr = spd->spd_spec.spd_data_ptr_info.spd_data_ptr; + *spd_data_len = spd->spd_spec.spd_data_ptr_info.spd_data_len; + return; + } + + if (spd->read_type == READ_SPD_CBFS) { + spd_read_from_cbfs(spd, spd_data_ptr, spd_data_len); + return; + } + + die("no valid way to read SPD info"); +} + +/* Initialize onboard memory configurations for lpddr4x */ +void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, struct mb_lpddr4x_cfg *board_cfg) +{ + const struct lpddr4x_spd_info *spd = &board_cfg->spd; + size_t spd_data_len; + uintptr_t spd_data_ptr; + + get_spd_data(spd, &spd_data_ptr, &spd_data_len); + print_spd_info((unsigned char *)spd_data_ptr); + + mem_cfg->MemorySpdDataLen = spd_data_len; + + MEM_CFG_DIMM0(mem_cfg, 0, 0, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 0, 1, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 0, 2, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 0, 3, spd_data_ptr, board_cfg); + + if (board_cfg->half_populated) { + printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); + MEM_CFG_EMPTY(mem_cfg, 1, 0); + MEM_CFG_EMPTY(mem_cfg, 1, 1); + MEM_CFG_EMPTY(mem_cfg, 1, 2); + MEM_CFG_EMPTY(mem_cfg, 1, 3); + } else { + MEM_CFG_DIMM0(mem_cfg, 1, 0, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 1, 1, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 1, 2, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 1, 3, spd_data_ptr, board_cfg); + } + + /* LPDDR4 does not allow interleaved memory */ + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->ECT = board_cfg->ect; + mem_cfg->MrcSafeConfig = 0x1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Gerrit-Change-Number: 38606 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: mb/google/drallion: Add new SPD files for drallion
by Ian Feng (Code Review) 09 Feb '20

09 Feb '20

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38731 ) Change subject: mb/google/drallion: Add new SPD files for drallion ...................................................................... mb/google/drallion: Add new SPD files for drallion Add new SPD files for drallion: 1. Hynix H5AN8G6NDJR-XNC 2. Samung K4AAG165WA-BCWE 3. Samung K4A8G165WC-BCWE BUG=b:148642500 TEST=Compile successfully. Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I0e9b444f6f1e0c7e1da197fbd2e70e686568ab47 --- A src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NDJR-XNC.spd.hex A src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCWE.spd.hex A src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WA-BCWE.spd.hex M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/memory.c 5 files changed, 101 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/38731/1 diff --git a/src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NDJR-XNC.spd.hex b/src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NDJR-XNC.spd.hex new file mode 100644 index 0000000..dec132b --- /dev/null +++ b/src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NDJR-XNC.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B4 00 00 00 00 E7 00 75 20 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 4D 41 38 35 31 53 +36 44 4A 52 36 4E 2D 58 4E 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCWE.spd.hex b/src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCWE.spd.hex new file mode 100644 index 0000000..2440c75 --- /dev/null +++ b/src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCWE.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 14 98 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36 +35 57 43 2D 42 43 57 45 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WA-BCWE.spd.hex b/src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WA-BCWE.spd.hex new file mode 100644 index 0000000..8c98da1 --- /dev/null +++ b/src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WA-BCWE.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36 +35 57 41 2D 42 43 57 45 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 954c9d5..b584a91 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -23,6 +23,9 @@ SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b10011 SPD_SOURCES += samsung_dimm_K4AAG165WB-MCTD # 0b11011 SPD_SOURCES += micron_dimm_MT40A1G16KD-062EE # 0b11010 +SPD_SOURCES += hynix_dimm_H5AN8G6NDJR-XNC # 0b01100 +SPD_SOURCES += samsung_dimm_K4AAG165WA-BCWE # 0b00000 +SPD_SOURCES += samsung_dimm_K4A8G165WC-BCWE # 0b00100 bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c index 9c4135d..0fb64d3 100644 --- a/src/mainboard/google/drallion/variants/drallion/memory.c +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -21,8 +21,8 @@ /* Use spd_index array to save mem_id */ static const int spd_index[32] = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, + 10, 0, 0, 0,11, 0, 0, 0, + 0, 0, 0, 0, 9, 0, 0, 0, 0, 4, 3, 6, 1, 0, 0, 0, 0, 5, 8, 7, 2, 0, 0, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/38731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e9b444f6f1e0c7e1da197fbd2e70e686568ab47 Gerrit-Change-Number: 38731 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion: Tuning WWAN power sequence
by EricR Lai (Code Review) 09 Feb '20

09 Feb '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38742 ) Change subject: mb/google/drallion: Tuning WWAN power sequence ...................................................................... mb/google/drallion: Tuning WWAN power sequence Change GPP_C10 from pltrst to deep to meet the warnboot power sequence. BUG=b:146935222 TEST=measure WWAN power sequence is meet spec Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ia1513ed38fbc1c99a10a5fa531a78cc92a3ebfc2 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38742/1 diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 1c864ca..85de173 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -88,7 +88,7 @@ /* SML0CLK */ PAD_NC(GPP_C3, NONE), /* SML0DATA */ PAD_NC(GPP_C4, NONE), /* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), -/* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_FULL_PWR_EN */ +/* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_FULL_PWR_EN */ /* UART0_CTS# */ PAD_NC(GPP_C11, NONE), /* UART1_RXD */ PAD_NC(GPP_C12, NONE), /* UART1_TXD */ PAD_NC(GPP_C13, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/38742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1513ed38fbc1c99a10a5fa531a78cc92a3ebfc2 Gerrit-Change-Number: 38742 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/dedede: Log mainboard SMI events to elog
by Karthik Ramasubramanian (Code Review) 09 Feb '20

09 Feb '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38724 ) Change subject: mb/google/dedede: Log mainboard SMI events to elog ...................................................................... mb/google/dedede: Log mainboard SMI events to elog BUG=b:148410914 TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I7dffa5c021787dca75786ead42164bd29ba56828 --- M src/mainboard/google/dedede/smihandler.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38724/1 diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 2c2230f..deb2223 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -8,7 +8,9 @@ #include <baseboard/variants.h> #include <cpu/x86/smm.h> +#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> +#include <elog.h> #include <intelblocks/smihandler.h> #include <variant/ec.h> @@ -35,3 +37,9 @@ MAINBOARD_EC_SMI_EVENTS); return 0; } + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S0IX_WAKE_EVENTS); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dffa5c021787dca75786ead42164bd29ba56828 Gerrit-Change-Number: 38724 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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