Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
soc/intel/tigerlake: add memory configuration support
Move some of the common memory code that was being performed in mainboard into the soc to reduce redundant code going forward.
BUG=b:145642089 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel and verify memory size shows 8GB.
Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/include/soc/meminit.h A src/soc/intel/tigerlake/meminit.c 3 files changed, 205 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/38606/1
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 532861d..c1bac36 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -25,6 +25,7 @@
romstage-y += espi.c romstage-y += gpio.c +romstage-y += meminit.c romstage-y += reset.c
ramstage-y += acpi.c diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h new file mode 100644 index 0000000..a99b033 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_MEMINIT_H_ +#define _SOC_TIGERLAKE_MEMINIT_H_ + +#include <stddef.h> +#include <stdint.h> +#include <fsp/soc_binding.h> + +#define BYTES_PER_CHANNEL 2 +#define BITS_PER_BYTE 8 +#define DQS_PER_CHANNEL 2 +#define NUM_CHANNELS 8 + +struct spd_by_pointer { + size_t spd_data_len; + uintptr_t spd_data_ptr; +}; + +enum lpddr4x_mem_info_read_type { + NOT_EXISTING, /* No memory in this channel */ + READ_SPD_CBFS, /* Find spd file in CBFS. */ + READ_SPD_MEMPTR /* Find spd data from pointer. */ +}; + +struct lpddr4x_spd_info { + enum lpddr4x_mem_info_read_type read_type; + union spd_data_by { + /* To identify spd file when read_type is READ_SPD_CBFS. */ + int spd_index; + + /* To find spd data when read_type is READ_SPD_MEMPTR. */ + struct spd_by_pointer spd_data_ptr_info; + } spd_spec; +}; + +/* Board-specific memory configuration information */ +struct mb_lpddr4x_cfg { + /* SPD info */ + struct lpddr4x_spd_info spd; + + /* DQ mapping */ + uint8_t dq_map[NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; + + /* + * DQS CPU<>DRAM map MC0 and MC1. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + */ + uint8_t dqs_map[NUM_CHANNELS][DQS_PER_CHANNEL]; + + /* + * Early Command Training Enable/Disable Control + * 1 = enable, 0 = disable + */ + uint8_t ect; + + /* Set to true if only populating half the DRAM */ + bool half_populated; +}; + +/* Initialize default memory configurations for lpddr4x */ +void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, struct mb_lpddr4x_cfg *board_cfg); + +#endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c new file mode 100644 index 0000000..4c2199b --- /dev/null +++ b/src/soc/intel/tigerlake/meminit.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <assert.h> +#include <console/console.h> +#include <fsp/util.h> +#include <soc/meminit.h> +#include <spd_bin.h> +#include <string.h> + +/* If half populating DRAM, those channels would be 0 thru 3 */ +#define HALF_POPULATED_COUNT 4 + +enum dimm_enable_options { + ENABLE_BOTH_DIMMS = 0, + DISABLE_DIMM0 = 1, + DISABLE_DIMM1 = 2, + DISABLE_BOTH_DIMMS = 3 +}; + +/* Configure memory channel as unpopulated */ +#define MEM_CFG_EMPTY(_mem_cfg, _mc, _ch) \ + do { \ + _mem_cfg->DisableDimmMc ## _mc ## Ch ## _ch = DISABLE_BOTH_DIMMS; \ + _mem_cfg->MemorySpdPtr ## _mc ## _ch ## 0 = 0; \ + _mem_cfg->MemorySpdPtr ## _mc ## _ch ## 1 = 0; \ + } while (0) + +/* Configure memory channel with only dimm0 used */ +#define MEM_CFG_DIMM0(_mem_cfg, _mc, _ch, _data, _b_cfg) \ + do { \ + _mem_cfg->DisableDimmMc ## _mc ## Ch ## _ch = DISABLE_DIMM1; \ + _mem_cfg->MemorySpdPtr ## _mc ## _ch ## 0 = _data; \ + _mem_cfg->MemorySpdPtr ## _mc ## _ch ## 1 = 0; \ + memcpy(&_mem_cfg->DqMapCpu2DramMc ## _mc ## Ch ## _ch, \ + &_b_cfg->dq_map[_mc * NUM_CHANNELS / 2 + _ch], \ + sizeof(_b_cfg->dq_map[_mc * NUM_CHANNELS / 2 + _ch])); \ + memcpy(&_mem_cfg->DqsMapCpu2DramMc ## _mc ## Ch ## _ch, \ + &_b_cfg->dqs_map[_mc * NUM_CHANNELS / 2 + _ch], \ + sizeof(_b_cfg->dqs_map[_mc * NUM_CHANNELS / 2 + _ch])); \ + } while (0) + + +static void spd_read_from_cbfs(const struct lpddr4x_spd_info *spd, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + struct region_device spd_rdev; + size_t spd_index = spd->spd_spec.spd_index; + + printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + *spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); +} + +static void get_spd_data(const struct lpddr4x_spd_info *spd, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + if (spd->read_type == READ_SPD_MEMPTR) { + *spd_data_ptr = spd->spd_spec.spd_data_ptr_info.spd_data_ptr; + *spd_data_len = spd->spd_spec.spd_data_ptr_info.spd_data_len; + return; + } + + if (spd->read_type == READ_SPD_CBFS) { + spd_read_from_cbfs(spd, spd_data_ptr, spd_data_len); + return; + } + + die("no valid way to read SPD info"); +} + +/* Initialize onboard memory configurations for lpddr4x */ +void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, struct mb_lpddr4x_cfg *board_cfg) +{ + const struct lpddr4x_spd_info *spd = &board_cfg->spd; + size_t spd_data_len; + uintptr_t spd_data_ptr; + + get_spd_data(spd, &spd_data_ptr, &spd_data_len); + print_spd_info((unsigned char *)spd_data_ptr); + + mem_cfg->MemorySpdDataLen = spd_data_len; + + MEM_CFG_DIMM0(mem_cfg, 0, 0, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 0, 1, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 0, 2, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 0, 3, spd_data_ptr, board_cfg); + + if (board_cfg->half_populated) { + printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); + MEM_CFG_EMPTY(mem_cfg, 1, 0); + MEM_CFG_EMPTY(mem_cfg, 1, 1); + MEM_CFG_EMPTY(mem_cfg, 1, 2); + MEM_CFG_EMPTY(mem_cfg, 1, 3); + } else { + MEM_CFG_DIMM0(mem_cfg, 1, 0, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 1, 1, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 1, 2, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 1, 3, spd_data_ptr, board_cfg); + } + + /* LPDDR4 does not allow interleaved memory */ + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->ECT = board_cfg->ect; + mem_cfg->MrcSafeConfig = 0x1; +}
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
Patch Set 1: Code-Review-2
Not yet ready for review.
Hello Srinidhi N Kaushik, Patrick Rudolph, Caveh Jalali, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38606
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
soc/intel/tigerlake: add memory configuration support
Move some of the common memory code that was being performed in mainboard into the soc to reduce redundant code going forward.
BUG=b:145642089 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel and verify memory size shows 8GB.
Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/include/soc/meminit.h A src/soc/intel/tigerlake/meminit.c 3 files changed, 248 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/38606/2
Nick Vaccaro has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
Removed Code-Review-2 by Nick Vaccaro nvaccaro@google.com
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
Patch Set 7:
This change is ready for review.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/mem... File src/soc/intel/tigerlake/meminit_tgl.c:
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/mem... PS8, Line 153: board_cfg->half_populated, Why is this required if board_cfg is already passed into meminit_channels_dimm0()?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... PS8, Line 26: lpddr4x_ nit: I don't think this prefix is required. This can be just named: enum spd_read_type.
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... PS8, Line 32: lpddr4x_ nit: This structure can be just named struct spd_info
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... PS8, Line 71: meminit_lpddr4x_dimm0 Just a thought: If struct mb_lpddr4x_config is restricted to contain only dq_map, dqs_map, ect and then if the signature of this function is changed to something like: void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, const struct mb_lpddr4x_cfg *board_cfg, const struct spd_info *spd, bool half_populated)
Then, it will allow you to avoid memcpy()s in the mainboard code and also you can easily make structures static const. Thoughts?
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
Patch Set 11:
(2 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... PS8, Line 26: lpddr4x_
nit: I don't think this prefix is required. This can be just named: enum spd_read_type.
I added "lpddr4x" because we dropped READ_SMBUS from this list, but I wasn't sure if it could potentially be needeed by other memory types (DDR4 ?). Is the fact volteer won't need READ_SMBUS due to tigerlake architecture, or the fact volteer is using lpddr4x?
Should I still drop the prefix?
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... PS8, Line 71: meminit_lpddr4x_dimm0
Just a thought: […]
Yes, I like your idea. I had been thinking about how to reduce the double-memcpy of the current scheme to make this more efficient, now would be a good time to do so.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
Patch Set 13:
This change is ready for review.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... PS8, Line 32: lpddr4x_
nit: This structure can be just named struct spd_info
Given comment above, should I drop the lpddr4x in both of these structure names?
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/mem... File src/soc/intel/tigerlake/meminit_tgl.c:
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/mem... PS8, Line 153: board_cfg->half_populated,
Why is this required if board_cfg is already passed into meminit_channels_dimm0()?
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... PS8, Line 26: lpddr4x_
I added "lpddr4x" because we dropped READ_SMBUS from this list, but I wasn't sure if it could potent […]
Even if READ_SMBUS is dropped, I think we can still keep this as spd_read_type. In the future, once we add support for more memory types, we can potentially reuse the same enum. I think we can always add READ_SMBUS back at that point.
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... PS8, Line 32: lpddr4x_
Given comment above, should I drop the lpddr4x in both of these structure names?
Yes, I think spd_info can be used by any memory type.
Hello Srinidhi N Kaushik, Patrick Rudolph, Caveh Jalali, Wonkyu Kim, Ravishankar Sarawadi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38606
to look at the new patch set (#14).
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
soc/intel/tigerlake: add memory configuration support
Move some of the common memory code that was being performed in mainboard into the soc to reduce redundant code going forward.
BUG=b:145642089 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel and verify memory size shows 8GB.
Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/include/soc/meminit_tgl.h A src/soc/intel/tigerlake/meminit_tgl.c 3 files changed, 235 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/38606/14
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
Patch Set 13:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... PS8, Line 26: lpddr4x_
Even if READ_SMBUS is dropped, I think we can still keep this as spd_read_type. […]
Done
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... PS8, Line 32: lpddr4x_
Yes, I think spd_info can be used by any memory type.
Done
https://review.coreboot.org/c/coreboot/+/38606/8/src/soc/intel/tigerlake/inc... PS8, Line 71: meminit_lpddr4x_dimm0
Yes, I like your idea. […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
Patch Set 14: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
soc/intel/tigerlake: add memory configuration support
Move some of the common memory code that was being performed in mainboard into the soc to reduce redundant code going forward.
BUG=b:145642089 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel and verify memory size shows 8GB.
Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Signed-off-by: Nick Vaccaro nvaccaro@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38606 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/include/soc/meminit_tgl.h A src/soc/intel/tigerlake/meminit_tgl.c 3 files changed, 235 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 532861d..56119f5 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -25,6 +25,7 @@
romstage-y += espi.c romstage-y += gpio.c +romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += meminit_tgl.c romstage-y += reset.c
ramstage-y += acpi.c diff --git a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h new file mode 100644 index 0000000..dd05418 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef _SOC_MEMINIT_TGL_H_ +#define _SOC_MEMINIT_TGL_H_ + +#include <stddef.h> +#include <stdint.h> +#include <fsp/soc_binding.h> + +#define BYTES_PER_CHANNEL 2 +#define BITS_PER_BYTE 8 +#define DQS_PER_CHANNEL 2 +#define NUM_CHANNELS 8 + +struct spd_by_pointer { + size_t spd_data_len; + uintptr_t spd_data_ptr; +}; + +enum mem_info_read_type { + NOT_EXISTING, /* No memory in this channel */ + READ_SPD_CBFS, /* Find spd file in CBFS. */ + READ_SPD_MEMPTR /* Find spd data from pointer. */ +}; + +struct spd_info { + enum mem_info_read_type read_type; + union spd_data_by { + /* To identify spd file when read_type is READ_SPD_CBFS. */ + int spd_index; + + /* To find spd data when read_type is READ_SPD_MEMPTR. */ + struct spd_by_pointer spd_data_ptr_info; + } spd_spec; +}; + +/* Board-specific memory configuration information */ +struct mb_lpddr4x_cfg { + /* DQ mapping */ + uint8_t dq_map[NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; + + /* + * DQS CPU<>DRAM map. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + */ + uint8_t dqs_map[NUM_CHANNELS][DQS_PER_CHANNEL]; + + /* + * Early Command Training Enable/Disable Control + * 1 = enable, 0 = disable + */ + uint8_t ect; +}; + +/* Initialize default memory configurations for dimm0-only lpddr4x */ +void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, + const struct mb_lpddr4x_cfg *board_cfg, + const struct spd_info *spd, + bool half_populated); + +#endif /* _SOC_MEMINIT_TGL_H_ */ diff --git a/src/soc/intel/tigerlake/meminit_tgl.c b/src/soc/intel/tigerlake/meminit_tgl.c new file mode 100644 index 0000000..922f66a --- /dev/null +++ b/src/soc/intel/tigerlake/meminit_tgl.c @@ -0,0 +1,164 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <assert.h> +#include <console/console.h> +#include <fsp/util.h> +#include <soc/meminit_tgl.h> +#include <spd_bin.h> +#include <string.h> + +enum dimm_enable_options { + ENABLE_BOTH_DIMMS = 0, + DISABLE_DIMM0 = 1, + DISABLE_DIMM1 = 2, + DISABLE_BOTH_DIMMS = 3 +}; + +#define MEM_INIT_CH_DQ_DQS_MAP(_mem_cfg, _b_cfg, _ch) \ + do { \ + memcpy(&_mem_cfg->DqMapCpu2DramCh ## _ch, \ + &_b_cfg->dq_map[_ch], \ + sizeof(_b_cfg->dq_map[_ch])); \ + memcpy(&_mem_cfg->DqsMapCpu2DramCh ## _ch, \ + &_b_cfg->dqs_map[_ch], \ + sizeof(_b_cfg->dqs_map[_ch])); \ + } while (0) + + +static void spd_read_from_cbfs(const struct spd_info *spd, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + struct region_device spd_rdev; + size_t spd_index = spd->spd_spec.spd_index; + + printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + *spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); +} + +static void get_spd_data(const struct spd_info *spd, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + if (spd->read_type == READ_SPD_MEMPTR) { + *spd_data_ptr = spd->spd_spec.spd_data_ptr_info.spd_data_ptr; + *spd_data_len = spd->spd_spec.spd_data_ptr_info.spd_data_len; + return; + } + + if (spd->read_type == READ_SPD_CBFS) { + spd_read_from_cbfs(spd, spd_data_ptr, spd_data_len); + return; + } + + die("no valid way to read SPD info"); +} + +static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, + const struct mb_lpddr4x_cfg *board_cfg, + bool half_populated) +{ + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 0); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 1); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 2); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 3); + + if (half_populated) + return; + + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 4); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 5); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 6); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 7); +} + +static void meminit_channels_dimm0(FSP_M_CONFIG *mem_cfg, + const struct mb_lpddr4x_cfg *board_cfg, + uintptr_t spd_data_ptr, + bool half_populated) +{ + uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */ + + /* Channel 0 */ + mem_cfg->Reserved9[0] = dimm_cfg; + mem_cfg->MemorySpdPtr00 = spd_data_ptr; + mem_cfg->MemorySpdPtr01 = 0; + + /* Channel 1 */ + mem_cfg->Reserved9[1] = dimm_cfg; + mem_cfg->MemorySpdPtr02 = spd_data_ptr; + mem_cfg->MemorySpdPtr03 = 0; + + /* Channel 2 */ + mem_cfg->Reserved9[2] = dimm_cfg; + mem_cfg->MemorySpdPtr04 = spd_data_ptr; + mem_cfg->MemorySpdPtr05 = 0; + + /* Channel 3 */ + mem_cfg->Reserved9[3] = dimm_cfg; + mem_cfg->MemorySpdPtr06 = spd_data_ptr; + mem_cfg->MemorySpdPtr07 = 0; + + if (half_populated) { + printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); + dimm_cfg = DISABLE_BOTH_DIMMS; + spd_data_ptr = 0; + } + + /* Channel 4 */ + mem_cfg->Reserved9[4] = dimm_cfg; + mem_cfg->MemorySpdPtr08 = spd_data_ptr; + mem_cfg->MemorySpdPtr09 = 0; + + /* Channel 5 */ + mem_cfg->Reserved9[5] = dimm_cfg; + mem_cfg->MemorySpdPtr10 = spd_data_ptr; + mem_cfg->MemorySpdPtr11 = 0; + + /* Channel 6 */ + mem_cfg->Reserved9[6] = dimm_cfg; + mem_cfg->MemorySpdPtr12 = spd_data_ptr; + mem_cfg->MemorySpdPtr13 = 0; + + /* Channel 7 */ + mem_cfg->Reserved9[7] = dimm_cfg; + mem_cfg->MemorySpdPtr14 = spd_data_ptr; + mem_cfg->MemorySpdPtr15 = 0; + + meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); +} + +/* Initialize onboard memory configurations for lpddr4x */ +void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, + const struct mb_lpddr4x_cfg *board_cfg, + const struct spd_info *spd, + bool half_populated) + +{ + size_t spd_data_len; + uintptr_t spd_data_ptr; + + get_spd_data(spd, &spd_data_ptr, &spd_data_len); + print_spd_info((unsigned char *)spd_data_ptr); + + mem_cfg->MemorySpdDataLen = spd_data_len; + meminit_channels_dimm0(mem_cfg, board_cfg, spd_data_ptr, + half_populated); + + /* LPDDR4 does not allow interleaved memory */ + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->ECT = board_cfg->ect; + mem_cfg->MrcSafeConfig = 0x1; +}
-
Furquan Shaikh (Code Review) -
Nick Vaccaro (Code Review)
-
Patrick Georgi (Code Review)