Nick Vaccaro uploaded patch set #14 to this change.

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soc/intel/tigerlake: add memory configuration support

Move some of the common memory code that was being performed in
mainboard into the soc to reduce redundant code going forward.

BUG=b:145642089
BRANCH=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, log into kernel and verify memory size shows 8GB.

Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
---
M src/soc/intel/tigerlake/Makefile.inc
A src/soc/intel/tigerlake/include/soc/meminit_tgl.h
A src/soc/intel/tigerlake/meminit_tgl.c
3 files changed, 235 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/38606/14

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